Commit message (Collapse) | Author | Age | Files | Lines | |
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* | cad/Makefile: Fix | Michael Reifenberger | 11 days | 1 | -1/+0 |
| | | | | delete unwanted line | ||||
* | cad/Clipper2: add A Polygon Clipping and Offsetting library (in C++, C# & ↵ | Michael Reifenberger | 11 days | 1 | -0/+2 |
| | | | | | | | | | | | | | | | | Delphi) It will be used by openscad. Clipper2: The Clipper2 library performs intersection, union, difference and XOR boolean operations on both simple and complex polygons. It also performs polygon offsetting. This is a major update of my original Clipper library that was written over 10 years ago. That library I'm now calling Clipper1, and while it still works very well, Clipper2 is better in just about every way. | ||||
* | cad/py-csxcad: New port: C++ library to describe geometrical objects | Yuri Victorovich | 2024-08-28 | 1 | -0/+1 |
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* | cad/libbgcode: new port | Michael Zhilin | 2024-03-28 | 1 | -0/+1 |
| | | | | | | | | | | It is required by PrusaSlicer 2.7+. This port provides library and binary to work with g-code (read/write/convert) Reported by: Teodor Sigaev <teodorsigaev@gmail.com> Reviewed by: lwhsu (mentor) Sponsored by: Postgres Professional Differential Revision: https://reviews.freebsd.org/D44257 | ||||
* | cad/symbiyosys: New port: SymbiYosys (sby): Front-end for Yosys-based formal ↵ | Yuri Victorovich | 2024-01-10 | 1 | -0/+1 |
| | | | | verification flows | ||||
* | cad/apio: New port: Open source ecosystem for open FPGA boards | Yuri Victorovich | 2024-01-06 | 1 | -0/+1 |
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* | cad/jspice3: Remove expired port | Muhammad Moinur Rahman | 2023-12-31 | 1 | -1/+0 |
| | | | | 2023-12-31 cad/jspice3: BROKEN for more than 2 years on all supported versions after the EOL of 12 | ||||
* | cad/freehdl: resurrect | Thierry Thomas | 2023-11-21 | 1 | -0/+1 |
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* | cad/freehdl: Remove expired port | Rene Ladan | 2023-11-21 | 1 | -1/+0 |
| | | | | 2023-11-21 cad/freehdl: Upstream vaporized and SF site do not have dists anymore | ||||
* | cad/yosys-ghdl-plugin: Add new port | Nico Sonack | 2023-10-19 | 1 | -0/+1 |
| | | | | | | | This allows performing synthesis of VHDL using ghdl with yosys. Signed-off-by: Nico Sonack <nsonack@herrhotzenplotz.de> PR: 274243 | ||||
* | cad/py-ocp: Remove expired port | Muhammad Moinur Rahman | 2023-09-11 | 1 | -1/+0 |
| | | | | 2023-03-21 cad/py-ocp: Broken since 2021 | ||||
* | cad/py-cadquery: Remove expired port | Muhammad Moinur Rahman | 2023-09-01 | 1 | -1/+0 |
| | | | | 2023-06-21 cad/py-cadquery: Depends on exppired cad/py-ocp | ||||
* | cad/py-cq-editor: Remove expired port | Muhammad Moinur Rahman | 2023-09-01 | 1 | -1/+0 |
| | | | | 2023-06-21 cad/py-cq-editor: Depends on expiring cad/py-cadquery | ||||
* | cad/py-gdstk: New port: Library for creation and manipulation of GDSII and ↵ | Yuri Victorovich | 2023-08-28 | 1 | -0/+1 |
| | | | | OASIS files | ||||
* | cad/gdstk: New port: C++ library for creation and manipulation of GDSII and ↵ | Yuri Victorovich | 2023-08-28 | 1 | -0/+1 |
| | | | | OASIS files | ||||
* | cad/py-amaranth: New port: Amaranth hardware definition language | Yuri Victorovich | 2023-07-28 | 1 | -0/+1 |
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* | cad/py-pyvcd: New port: Python VCD file support | Yuri Victorovich | 2023-07-27 | 1 | -0/+1 |
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* | cad/qspeakers: Add new port | Thomas Zander | 2023-06-21 | 1 | -0/+1 |
| | | | | | | | QSpeakers is an open source DIY (do it yourself) speakers enclosure design software written in C++ with Qt for the UI. This program simulates common acoustical enclosures behaviour in the mean to help users to design their own loudspeaker systems. | ||||
* | cad/yosys-systemverilog: New port: SystemVerilog support for Yosys | Yuri Victorovich | 2023-06-06 | 1 | -0/+1 |
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* | cad/NASTRAN-95: Remove expired port: | Muhammad Moinur Rahman | 2023-03-19 | 1 | -1/+0 |
| | | | | 2023-03-20 cad/NASTRAN-95: Broken since 2020 | ||||
* | cad/gdscpp: New port: C++ library to create and read GDSII file | Yuri Victorovich | 2023-03-02 | 1 | -0/+1 |
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* | cad/ghdl: Re-add port: GNU VHDL simulator | Yuri Victorovich | 2023-02-23 | 1 | -0/+1 |
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* | cad/hs-verismith: New port: Verilog fuzzer | Yuri Victorovich | 2023-02-17 | 1 | -0/+1 |
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* | cad/py-cocotb: New port: Coroutine based cosimulation library for writing ↵ | Yuri Victorovich | 2023-02-03 | 1 | -0/+1 |
| | | | | VHDL and Verilog | ||||
* | cad/antimony: New port: CAD from a parallel universe | Yuri Victorovich | 2023-01-16 | 1 | -0/+1 |
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* | cad/silice: New port: Language that simplifies prototyping and writing ↵ | Yuri Victorovich | 2023-01-08 | 1 | -0/+1 |
| | | | | algorithms for FPGAs | ||||
* | cad/py-edalize: New port: Library for interfacing EDA tools | Yuri Victorovich | 2023-01-08 | 1 | -0/+1 |
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* | cad/py-vunit-hdl: New pert: Open source unit testing framework for ↵ | Yuri Victorovich | 2023-01-08 | 1 | -0/+1 |
| | | | | VHDL/SystemVerilog | ||||
* | cad/veryl: New port: Veryl: A modern Hardware Description Language (HDL) | Yuri Victorovich | 2023-01-05 | 1 | -0/+1 |
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* | cad/svls: New port: SystemVerilog language server | Yuri Victorovich | 2023-01-05 | 1 | -0/+1 |
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* | cad/svlint: New port: SystemVerilog linter | Yuri Victorovich | 2023-01-02 | 1 | -0/+1 |
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* | cad/basicdsp: Cleanup EXPIRED ports | Muhammad Moinur Rahman | 2022-12-31 | 1 | -1/+0 |
| | | | | Approved by: portmgr | ||||
* | cleanup: Remove expired ports: | Rene Ladan | 2022-12-31 | 1 | -1/+0 |
| | | | | 2022-12-31 cad/linux-eagle5: Deprecated upstream, superseded by Autodesk EAGLE 9 | ||||
* | cad/py-pygmsh: New port: Python frontend for Gmsh (on top of Gmsh's own binding) | Yuri Victorovich | 2022-12-20 | 1 | -0/+1 |
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* | cad/py-gmsh: New port: Automatic 3D finite element mesh generator (gmsh's ↵ | Yuri Victorovich | 2022-12-19 | 1 | -0/+1 |
| | | | | own binding) | ||||
* | cad/libgdsii: New port: C++ library and command-line utility for reading ↵ | Yuri Victorovich | 2022-11-19 | 1 | -0/+1 |
| | | | | GDSII geometry files | ||||
* | cad/qucsator: New port: Circuit simulator of the Qucs project | Yuri Victorovich | 2022-07-09 | 1 | -0/+1 |
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* | cad/xyce: New port: Xyce electronic simulator | Yuri Victorovich | 2022-07-08 | 1 | -0/+1 |
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* | cad/qucs-s: New port: Quite Universal Circuit Simulator: GUI for circuit ↵ | Yuri Victorovich | 2022-07-08 | 1 | -0/+1 |
| | | | | simulation kernels | ||||
* | Add cad/pcb-rnd: Flexible, modular Printed Circuit Board editor | Robert Clausecker | 2022-06-05 | 1 | -0/+1 |
| | | | | PR: 264289 | ||||
* | Add cad/pcb-rnd: Flexible, modular Printed Circuit Board editor | Robert Clausecker | 2022-06-05 | 1 | -0/+1 |
| | | | | PR: 264289 | ||||
* | cad/camotics: adding CAMotics, Simulation & Computer Aided Machining | Thierry Thomas | 2022-05-21 | 1 | -0/+1 |
| | | | | | | | | | The latest stable release, v1.2.0, is for Python-2.7, this is why I ported this -RC1, but it is somewhat buggy. Do not hesitate to report any problem! PR: 262763 Requested by: luzpaz (at) pm.me | ||||
* | cleanup: Remove ports depending on expired lang/gcc6-aux | Rene Ladan | 2022-02-28 | 1 | -1/+0 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Keep ports-mgmt/synth and dependencies (including lang/gcc6-aux itself) for now as synth is the only Ada port still maintained and might be somewhat high-profile. Removed ports: archivers/zip-ada cad/ghdl databases/adabase databases/apq databases/apq-mysql databases/apq-odbc databases/apq-pgsql devel/ada-util devel/adabooch devel/adaid devel/ahven devel/alog devel/aunit devel/florist-gpl devel/gprbuild devel/libspark2012 devel/matreshka devel/pcsc-ada devel/pragmarcs devel/sdl_gnat dns/ironsides graphics/generic_image_decoder lang/adacontrol lang/asis lang/gnat_util lang/lua-ada math/plplot-ada misc/excel-writer net/adasockets net/anet security/libadacrypt textproc/adabrowse textproc/templates_parser textproc/words textproc/xmlada x11-toolkits/gtkada x11-toolkits/gtkada3 | ||||
* | cad/opencascade740: Resurrect cad/opencascade @ version 7.4.0 | Yuri Victorovich | 2022-01-29 | 1 | -0/+1 |
| | | | | This is needed for science/chrono. | ||||
* | cad/padring: New port: Padring generator for ASICs | Yuri Victorovich | 2021-12-29 | 1 | -0/+1 |
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* | cad/cvc: New port: Circuit Validity Checker | Yuri Victorovich | 2021-12-28 | 1 | -0/+1 |
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* | cad/uhdm: New port: Universal Hardware Data Model | Yuri Victorovich | 2021-12-27 | 1 | -0/+1 |
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* | cad/surelog: New port: SystemVerilog 2017 Pre-processor, Parser, Elaborator, etc | Yuri Victorovich | 2021-12-27 | 1 | -0/+1 |
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* | cad/py-pymtl: New port: Python-based hardware generation, simulation, ↵ | Yuri Victorovich | 2021-12-26 | 1 | -0/+1 |
| | | | | verification framework | ||||
* | cad/gds3d: New port: Application for rendering IC (chip) layouts in 3D | Yuri Victorovich | 2021-10-04 | 1 | -0/+1 |
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