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* cad/surfer: Add new portJoel Bodenmann5 days1-0/+1
* cad/tkgate: Remove expired portRene Ladan2024-10-311-1/+0
* cad/Makefile: FixMichael Reifenberger2024-10-131-1/+0
* cad/Clipper2: add A Polygon Clipping and Offsetting library (in C++, C# & Del...Michael Reifenberger2024-10-131-0/+2
* cad/py-csxcad: New port: C++ library to describe geometrical objectsYuri Victorovich2024-08-281-0/+1
* cad/libbgcode: new portMichael Zhilin2024-03-281-0/+1
* cad/symbiyosys: New port: SymbiYosys (sby): Front-end for Yosys-based formal ...Yuri Victorovich2024-01-101-0/+1
* cad/apio: New port: Open source ecosystem for open FPGA boardsYuri Victorovich2024-01-061-0/+1
* cad/jspice3: Remove expired portMuhammad Moinur Rahman2023-12-311-1/+0
* cad/freehdl: resurrectThierry Thomas2023-11-211-0/+1
* cad/freehdl: Remove expired portRene Ladan2023-11-211-1/+0
* cad/yosys-ghdl-plugin: Add new portNico Sonack2023-10-191-0/+1
* cad/py-ocp: Remove expired portMuhammad Moinur Rahman2023-09-111-1/+0
* cad/py-cadquery: Remove expired portMuhammad Moinur Rahman2023-09-011-1/+0
* cad/py-cq-editor: Remove expired portMuhammad Moinur Rahman2023-09-011-1/+0
* cad/py-gdstk: New port: Library for creation and manipulation of GDSII and OA...Yuri Victorovich2023-08-281-0/+1
* cad/gdstk: New port: C++ library for creation and manipulation of GDSII and O...Yuri Victorovich2023-08-281-0/+1
* cad/py-amaranth: New port: Amaranth hardware definition languageYuri Victorovich2023-07-281-0/+1
* cad/py-pyvcd: New port: Python VCD file supportYuri Victorovich2023-07-271-0/+1
* cad/qspeakers: Add new portThomas Zander2023-06-211-0/+1
* cad/yosys-systemverilog: New port: SystemVerilog support for YosysYuri Victorovich2023-06-061-0/+1
* cad/NASTRAN-95: Remove expired port:Muhammad Moinur Rahman2023-03-191-1/+0
* cad/gdscpp: New port: C++ library to create and read GDSII fileYuri Victorovich2023-03-021-0/+1
* cad/ghdl: Re-add port: GNU VHDL simulatorYuri Victorovich2023-02-231-0/+1
* cad/hs-verismith: New port: Verilog fuzzerYuri Victorovich2023-02-171-0/+1
* cad/py-cocotb: New port: Coroutine based cosimulation library for writing VHD...Yuri Victorovich2023-02-031-0/+1
* cad/antimony: New port: CAD from a parallel universeYuri Victorovich2023-01-161-0/+1
* cad/silice: New port: Language that simplifies prototyping and writing algori...Yuri Victorovich2023-01-081-0/+1
* cad/py-edalize: New port: Library for interfacing EDA toolsYuri Victorovich2023-01-081-0/+1
* cad/py-vunit-hdl: New pert: Open source unit testing framework for VHDL/Syste...Yuri Victorovich2023-01-081-0/+1
* cad/veryl: New port: Veryl: A modern Hardware Description Language (HDL)Yuri Victorovich2023-01-051-0/+1
* cad/svls: New port: SystemVerilog language serverYuri Victorovich2023-01-051-0/+1
* cad/svlint: New port: SystemVerilog linterYuri Victorovich2023-01-021-0/+1
* cad/basicdsp: Cleanup EXPIRED portsMuhammad Moinur Rahman2022-12-311-1/+0
* cleanup: Remove expired ports:Rene Ladan2022-12-311-1/+0
* cad/py-pygmsh: New port: Python frontend for Gmsh (on top of Gmsh's own binding)Yuri Victorovich2022-12-201-0/+1
* cad/py-gmsh: New port: Automatic 3D finite element mesh generator (gmsh's own...Yuri Victorovich2022-12-191-0/+1
* cad/libgdsii: New port: C++ library and command-line utility for reading GDSI...Yuri Victorovich2022-11-191-0/+1
* cad/qucsator: New port: Circuit simulator of the Qucs projectYuri Victorovich2022-07-091-0/+1
* cad/xyce: New port: Xyce electronic simulatorYuri Victorovich2022-07-081-0/+1
* cad/qucs-s: New port: Quite Universal Circuit Simulator: GUI for circuit simu...Yuri Victorovich2022-07-081-0/+1
* Add cad/pcb-rnd: Flexible, modular Printed Circuit Board editorRobert Clausecker2022-06-051-0/+1
* Add cad/pcb-rnd: Flexible, modular Printed Circuit Board editorRobert Clausecker2022-06-051-0/+1
* cad/camotics: adding CAMotics, Simulation & Computer Aided MachiningThierry Thomas2022-05-211-0/+1
* cleanup: Remove ports depending on expired lang/gcc6-auxRene Ladan2022-02-281-1/+0
* cad/opencascade740: Resurrect cad/opencascade @ version 7.4.0Yuri Victorovich2022-01-291-0/+1
* cad/padring: New port: Padring generator for ASICsYuri Victorovich2021-12-291-0/+1
* cad/cvc: New port: Circuit Validity CheckerYuri Victorovich2021-12-281-0/+1
* cad/uhdm: New port: Universal Hardware Data ModelYuri Victorovich2021-12-271-0/+1
* cad/surelog: New port: SystemVerilog 2017 Pre-processor, Parser, Elaborator, etcYuri Victorovich2021-12-271-0/+1
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