diff options
| author | Ying-Chieh Liao <ijliao@FreeBSD.org> | 2001-02-13 11:02:15 +0000 |
|---|---|---|
| committer | Ying-Chieh Liao <ijliao@FreeBSD.org> | 2001-02-13 11:02:15 +0000 |
| commit | 7bf8e1d6ec95024af62dd3fd9af5eeff15b0fedb (patch) | |
| tree | a90b1970ffb0bb245333087f5be7a1ebfc60bb19 /cad/Makefile | |
| parent | Update to 5.6.5. (diff) | |
add iverilog, a Verilog simulation and synthesis tool
Notes
Notes:
svn path=/head/; revision=38298
Diffstat (limited to 'cad/Makefile')
| -rw-r--r-- | cad/Makefile | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/cad/Makefile b/cad/Makefile index c890bbd60e6f..1432f3131abe 100644 --- a/cad/Makefile +++ b/cad/Makefile @@ -8,6 +8,7 @@ SUBDIR += felt SUBDIR += geda SUBDIR += irsim + SUBDIR += iverilog SUBDIR += kaskade SUBDIR += magic SUBDIR += mars |