summaryrefslogtreecommitdiff
path: root/cad (follow)
Commit message (Expand)AuthorAgeFilesLines
* multimedia/libvpx: update 1.13.0Jan Beich2023-02-111-0/+1
* cad/openvsp: drop unused libpthread-stubsJan Beich2023-02-111-2/+1
* cad/yosys: Update 0.25 → 0.26Yuri Victorovich2023-02-102-5/+5
* cad/veryl: Update 0.3.2 → 0.3.4Yuri Victorovich2023-02-102-16/+16
* cad/k40-whisperer: Replace reference to PY_PILLOW with its valueYasuhiro Kimura2023-02-101-1/+1
* */*: Update fuz@fuz.su to fuz@FreeBSD.orgRobert Clausecker2023-02-092-2/+2
* cad/veryl: Update 0.3.1 → 0.3.2Yuri Victorovich2023-02-072-37/+37
* cad/py-cocotb: Add test dependencyYuri Victorovich2023-02-051-1/+2
* cad/py-cocotb: Add test dependencyYuri Victorovich2023-02-051-1/+2
* Revert "Mk/Uses/python.mk: Fix USE_PYTHON=pep517: always compile and install ...Charlie Li2023-02-051-1/+0
* Mk/Uses/python.mk: Fix USE_PYTHON=pep517: always compile and install bytecodePo-Chuan Hsieh2023-02-061-0/+1
* cad/py-cocotb: Fix the test targetYuri Victorovich2023-02-051-4/+12
* cad/py-cocotb: New port: Coroutine based cosimulation library for writing VHD...Yuri Victorovich2023-02-034-0/+49
* cad/brlcad: update to version 7.32.6Pedro F. Giffuni2023-02-013-108/+10
* cad/veryl: Update 0.3.0 → 0.3.1Yuri Victorovich2023-01-312-55/+58
* cad/veryl: Update 0.2.2 → 0.3.0Yuri Victorovich2023-01-292-31/+43
* cad/veryl: Update 0.2.1 → 0.2.2Yuri Victorovich2023-01-252-52/+394
* cad/kicad: update KiCad and libraries to 6.0.11Christoph Moench-Tegeder2023-01-2513-24/+26
* cad/nvc: Update 1.7.1 → 1.8.1Yuri Victorovich2023-01-233-5/+50
* cad/verilator: Update 5.004 → 5.006Yuri Victorovich2023-01-233-6/+15
* cad/freecad: fix build after ebbef4b5f8Christoph Moench-Tegeder2023-01-214-0/+41
* cad/veryl: Update 0.2.0 -> 0.2.1Yuri Victorovich2023-01-192-10/+13
* math/suitesparse*: bump PORTREVISION of dependant portsThierry Thomas2023-01-191-1/+1
* graphics/proj: Update to 9.1.1Loïc Bartoletti2023-01-181-1/+1
* cad/veryl: Update 0.1.13 -> 0.2.0Yuri Victorovich2023-01-172-79/+364
* cad/antimony: New port: CAD from a parallel universeYuri Victorovich2023-01-167-0/+160
* */*: bump libboost*.so libraries consumert after Boost upgradeDima Panov2023-01-163-2/+3
* Mk/**ruby.mk: Switch from USE_RUBY=yes to USES=rubyMuhammad Moinur Rahman2023-01-142-3/+1
* cad/klayout: Update to 0.28.3Hiroki Sato2023-01-143-150/+151
* cad/veryl: Update 0.1.8 -> 0.1.13Yuri Victorovich2023-01-112-7/+7
* cad/netgen: Update to 6.2.2031Stephen Montgomery-Smith2023-01-113-5/+4
* */*: rename CHEESESHOP to PYPI in MASTER_SITESDmitry Marakasov2023-01-116-6/+6
* cad/veryl: Update 0.1.3 -> 0.1.8Yuri Victorovich2023-01-092-35/+40
* cad/ngspice_rework: fix packagingChristoph Moench-Tegeder2023-01-091-1/+1
* cad/kicad-library-*-devel: Update to the latest commitsMichael Reifenberger2023-01-0812-47/+907
* cad/kicad-devel: Update to the latest commitMichael Reifenberger2023-01-087-21/+64
* cad/ngspice_rework: Update to 38Kevin Zheng2023-01-082-4/+4
* cad/silice: New port: Language that simplifies prototyping and writing algori...Yuri Victorovich2023-01-085-0/+160
* cad/py-edalize: New port: Library for interfacing EDA toolsYuri Victorovich2023-01-084-0/+43
* cad/py-vunit-hdl: New pert: Open source unit testing framework for VHDL/Syste...Yuri Victorovich2023-01-084-0/+30
* */*: Bump rust (cargo) ports to reflect on WITH_LTODaniel Engberg2023-01-073-0/+3
* cad/qelectrotech: Update to 0.9.0Gleb Popov2023-01-073-2214/+5554
* cad/veryl: New port: Veryl: A modern Hardware Description Language (HDL)Yuri Victorovich2023-01-054-0/+629
* cad/svls: New port: SystemVerilog language serverYuri Victorovich2023-01-054-0/+437
* cad/yosys: Update 0.24 -> 0.25Yuri Victorovich2023-01-043-4/+31
* cad/svlint: New port: SystemVerilog linterYuri Victorovich2023-01-024-0/+287
* cad/klayout: Update to 0.28.2Hiroki Sato2023-01-0333-299/+369
* cad/freecad: fix desktop integrationMax Brazhnikov2023-01-022-16/+27
* cad/basicdsp: Cleanup EXPIRED portsMuhammad Moinur Rahman2022-12-316-61/+0
* cleanup: Remove expired ports:Rene Ladan2022-12-317-789/+0