| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | cad/yosys-systemverilog: New port: SystemVerilog support for Yosys | Yuri Victorovich | 2023-06-06 | 2 | -0/+25 |
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index : freebsd/ports.git | |
| Unnamed repository; edit this file 'description' to name the repository. | git |
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