| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | cad/py-verilog-parser: [NEW PORT] Lark-based parser for structural Verilog ne... | Aryan Karamtoth | 2025-10-30 | 3 | -0/+28 |
 |
index : freebsd/ports.git | |
| Unnamed repository; edit this file 'description' to name the repository. | git |
| summaryrefslogtreecommitdiff |