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Diffstat (limited to 'cad/verilator/Makefile')
| -rw-r--r-- | cad/verilator/Makefile | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/cad/verilator/Makefile b/cad/verilator/Makefile index cd4845914542..525a8bf99b42 100644 --- a/cad/verilator/Makefile +++ b/cad/verilator/Makefile @@ -5,6 +5,7 @@ CATEGORIES= cad MAINTAINER= yuri@FreeBSD.org COMMENT= Synthesizable Verilog to C++ compiler +WWW= https://www.veripool.org/projects/verilator/wiki/Intro LICENSE= GPLv3 LICENSE_FILE= ${WRKSRC}/LICENSE |