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-rw-r--r--cad/verilator/Makefile6
1 files changed, 1 insertions, 5 deletions
diff --git a/cad/verilator/Makefile b/cad/verilator/Makefile
index e876a7ce4d5b..26645e6a6aa3 100644
--- a/cad/verilator/Makefile
+++ b/cad/verilator/Makefile
@@ -1,12 +1,8 @@
PORTNAME= verilator
DISTVERSIONPREFIX= v
-DISTVERSION= 5.036
-PORTREVISION= 1
+DISTVERSION= 5.038
CATEGORIES= cad
-PATCH_SITES= https://github.com/${GH_ACCOUNT}/${PORTNAME}/commit/
-PATCHFILES= d94ed785888614cd53379b9faf58dfbde8f06b6f.patch:-p1 # https://github.com/verilator/verilator/pull/6028
-
MAINTAINER= yuri@FreeBSD.org
COMMENT= Synthesizable Verilog to C++ compiler
WWW= https://www.veripool.org/verilator/ \