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-rw-r--r--cad/p5-Verilog-Perl/Makefile3
1 files changed, 0 insertions, 3 deletions
diff --git a/cad/p5-Verilog-Perl/Makefile b/cad/p5-Verilog-Perl/Makefile
index ef676c8a61e1..bba6a7b18bc5 100644
--- a/cad/p5-Verilog-Perl/Makefile
+++ b/cad/p5-Verilog-Perl/Makefile
@@ -24,7 +24,4 @@ post-install:
${STRIP_CMD} ${STAGEDIR}${PREFIX}/${SITE_ARCH_REL}/auto/Verilog/Parser/*.so
${STRIP_CMD} ${STAGEDIR}${PREFIX}/${SITE_ARCH_REL}/auto/Verilog/Preproc/*.so
-regression-test: build
- make test -C ${WRKSRC}
-
.include <bsd.port.mk>