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-rw-r--r--cad/p5-Verilog-Perl/Makefile11
1 files changed, 6 insertions, 5 deletions
diff --git a/cad/p5-Verilog-Perl/Makefile b/cad/p5-Verilog-Perl/Makefile
index 208fc175b8d6..675c569794a7 100644
--- a/cad/p5-Verilog-Perl/Makefile
+++ b/cad/p5-Verilog-Perl/Makefile
@@ -1,12 +1,13 @@
PORTNAME= Verilog-Perl
-PORTVERSION= 3.478
+PORTVERSION= 3.482
CATEGORIES= cad perl5
MASTER_SITES= CPAN
PKGNAMEPREFIX= p5-
MAINTAINER= otacilio.neto@bsd.com.br
COMMENT= Building point for Verilog support in the Perl language
-WWW= https://www.veripool.org/wiki/verilog-perl
+WWW= https://www.veripool.org/wiki/verilog-perl/ \
+ https://github.com/veripool/verilog-perl/
LICENSE= ART20 LGPL3
LICENSE_COMB= dual
@@ -14,9 +15,9 @@ LICENSE_FILE_ART20= ${WRKSRC}/COPYING
USES= bison:wrapper gmake perl5
USE_PERL5= configure
-CONFIGURE_ENV= CXX=${CXX}\
- CPP=${CPP}\
- CC=${CC}
+CONFIGURE_ENV= CC=${CC} \
+ CPP=${CPP} \
+ CXX=${CXX}
post-install:
@${STRIP_CMD} ${STAGEDIR}${PREFIX}/${SITE_ARCH_REL}/auto/Verilog/Parser/*.so