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-rw-r--r--cad/iverilog/Makefile2
1 files changed, 2 insertions, 0 deletions
diff --git a/cad/iverilog/Makefile b/cad/iverilog/Makefile
index ca06116e2638..e805d41232e4 100644
--- a/cad/iverilog/Makefile
+++ b/cad/iverilog/Makefile
@@ -15,6 +15,8 @@ DISTNAME= verilog-20031009
MAINTAINER= watchman@ludd.luth.se
COMMENT= A Verilog simulation and synthesis tool
+BROKEN= "fails to compile - missing definition of TIME_FMT"
+
USE_BISON= yes
USE_GMAKE= yes
GNU_CONFIGURE= yes