lang/rust: Update to 1.73.0

Announce:	https://blog.rust-lang.org/2023/10/05/Rust-1.73.0.html
ChangeLog:	https://github.com/rust-lang/rust/releases/tag/1.73.0

PR:		274499
Tested by:	mikael,pkubaj

1 files changed, 34 insertions, 0 deletions

diff --git a/lang/rust/files/patch-bug116845 b/lang/rust/files/patch-bug116845
new file mode 100644
index 000000000000..a8ed00dfa805
--- /dev/null
+++ b/lang/rust/files/patch-bug116845
@@ -0,0 +1,34 @@
+From 491a91e8eea27fab4d8123cbfbb01bf1cf251b9c Mon Sep 17 00:00:00 2001
+From: Nikita Popov <npopov@redhat.com>
+Date: Thu, 12 Oct 2023 09:32:17 +0200
+Subject: [PATCH] [PowerPC] Use zext instead of anyext in custom and combine
+ (#68784)
+
+This custom combine currently converts `and(anyext(x),c)` into
+`anyext(and(x,c))`. This is not correct, because the original expression
+guaranteed that the high bits are zero, while the new one sets them to
+undef.
+
+Emit `zext(and(x,c))` instead.
+
+Fixes https://github.com/llvm/llvm-project/issues/68783.
+
+(cherry picked from commit 127ed9ae266ead58aa525f74f4c86841f6674793)
+---
+ llvm/lib/Target/PowerPC/PPCISelLowering.cpp     | 2 +-
+ llvm/test/CodeGen/PowerPC/and-extend-combine.ll | 3 ++-
+ 2 files changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+index 3ed0a261eb769a1..d4d2da55160e552 100644
+--- src/llvm-project/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
++++ src/llvm-project/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+@@ -15527,7 +15527,7 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
+       break;
+     SDValue ConstOp = DAG.getConstant(Imm, dl, MVT::i32);
+     SDValue NarrowAnd = DAG.getNode(ISD::AND, dl, MVT::i32, NarrowOp, ConstOp);
+-    return DAG.getAnyExtOrTrunc(NarrowAnd, dl, N->getValueType(0));
++    return DAG.getZExtOrTrunc(NarrowAnd, dl, N->getValueType(0));
+   }
+   case ISD::SHL:
+     return combineSHL(N, DCI);