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authorYuri Victorovich <yuri@FreeBSD.org>2023-06-06 14:09:16 -0700
committerYuri Victorovich <yuri@FreeBSD.org>2023-06-06 14:10:58 -0700
commit2fde22d5d05d8c75c5cc93cf98247c837ff43120 (patch)
tree54c6a4ab8d4e5969b7f0bfbd2060e518746286f3 /cad/yosys-systemverilog/files/install.sh
parentcad/yosys: Update 0.29 → 0.30; Add TCMALLOC option (diff)
cad/yosys-systemverilog: New port: SystemVerilog support for Yosys
Diffstat (limited to 'cad/yosys-systemverilog/files/install.sh')
-rwxr-xr-xcad/yosys-systemverilog/files/install.sh14
1 files changed, 14 insertions, 0 deletions
diff --git a/cad/yosys-systemverilog/files/install.sh b/cad/yosys-systemverilog/files/install.sh
new file mode 100755
index 000000000000..7962e5c28942
--- /dev/null
+++ b/cad/yosys-systemverilog/files/install.sh
@@ -0,0 +1,14 @@
+#!/bin/sh
+
+##
+## workaround for
+## * https://github.com/chipsalliance/yosys-f4pga-plugins/issues/527
+##
+##
+
+if [ "$1" != "-D" ]; then
+ exit 1
+fi
+
+#/usr/bin/install -m 0644 $2 ${DESTDIR}$3
+/usr/bin/install $2 $3