diff options
| author | Stefan Eßer <se@FreeBSD.org> | 2022-09-07 23:30:14 +0200 |
|---|---|---|
| committer | Stefan Eßer <se@FreeBSD.org> | 2022-09-07 23:58:51 +0200 |
| commit | fb16dfecae4a6efac9f3a78e0b759fb7a3c53de4 (patch) | |
| tree | 4bfc4b617ac23047eb736c72fb80d2b4f9069605 /cad/p5-Verilog-Perl | |
| parent | net/beanstalkd: update to 1.12 (diff) | |
Remove WWW entries moved into port Makefiles
Commit b7f05445c00f has added WWW entries to port Makefiles based on
WWW: lines in pkg-descr files.
This commit removes the WWW: lines of moved-over URLs from these
pkg-descr files.
Approved by: portmgr (tcberner)
Diffstat (limited to 'cad/p5-Verilog-Perl')
| -rw-r--r-- | cad/p5-Verilog-Perl/pkg-descr | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/cad/p5-Verilog-Perl/pkg-descr b/cad/p5-Verilog-Perl/pkg-descr index 69719b466c56..71fc00f6372e 100644 --- a/cad/p5-Verilog-Perl/pkg-descr +++ b/cad/p5-Verilog-Perl/pkg-descr @@ -15,5 +15,3 @@ language. It includes: First, you run vrename to create a list of signals in the design. You then edit this list, changing as many symbols as you wish. Vrename is then run a second time to apply the changes. - -WWW: https://www.veripool.org/wiki/verilog-perl |