- Update to 3.251

PR:		ports/148726
Submitted by:	Otacilio de Araujo Ramos Neto <otacilio.neto@ee.ufcg.edu.br> (maintainer)

3 files changed, 9 insertions, 7 deletions

diff --git a/cad/p5-Verilog-Perl/Makefile b/cad/p5-Verilog-Perl/Makefile
index 4381e094eabb..c3db29108304 100644
--- a/cad/p5-Verilog-Perl/Makefile
+++ b/cad/p5-Verilog-Perl/Makefile
@@ -6,7 +6,7 @@
 #
 
 PORTNAME=	Verilog-Perl
-PORTVERSION=	3.223
+PORTVERSION=	3.251
 CATEGORIES=	cad perl5
 MASTER_SITES=	CPAN
 PKGNAMEPREFIX=	p5-
@@ -28,9 +28,9 @@ MAN3=	Verilog::EditFiles.3 Verilog::Netlist::Logger.3 \
 	Verilog::Parser.3 Verilog::Getopt.3 Verilog::Netlist::Module.3 \
 	Verilog::Preproc.3 Verilog::Language.3 Verilog::Netlist::Net.3 \
 	Verilog::SigParser.3 Verilog::Netlist.3 Verilog::Netlist::Pin.3 \
-	Verilog::Netlist::Cell.3 Verilog::Netlist::Port.3 \
+	Verilog::Netlist::Cell.3 Verilog::Netlist::Port.3 Verilog::Netlist::Defparam.3 \
 	Verilog::Netlist::File.3 Verilog::Netlist::Subclass.3 \
-	Verilog::Netlist::ContAssign.3 \
+	Verilog::Netlist::ContAssign.3 Verilog::Netlist::ModPort.3 \
 	Verilog::Verilog-Perl.3 Verilog::Netlist::Interface.3 Verilog::Std.3
 
 .include <bsd.port.pre.mk>
diff --git a/cad/p5-Verilog-Perl/distinfo b/cad/p5-Verilog-Perl/distinfo
index ed4f23eb70cd..549b7329b1f8 100644
--- a/cad/p5-Verilog-Perl/distinfo
+++ b/cad/p5-Verilog-Perl/distinfo
@@ -1,3 +1,3 @@
-MD5 (Verilog-Perl-3.223.tar.gz) = 54405173d5796dc8dee6a630ae1583c2
-SHA256 (Verilog-Perl-3.223.tar.gz) = 9dc9a42938173580c8cbf5bb46760de53d950f3d2f44ceb3c4d6cad787443df6
-SIZE (Verilog-Perl-3.223.tar.gz) = 212651
+MD5 (Verilog-Perl-3.251.tar.gz) = ff7bbae6e7d2c3e8c8e1f7eee948b08e
+SHA256 (Verilog-Perl-3.251.tar.gz) = ee4742c36f84a6170340a1c79b5e5ebaa230d2fb08f85edde479dfd56cd0b708
+SIZE (Verilog-Perl-3.251.tar.gz) = 232475
diff --git a/cad/p5-Verilog-Perl/pkg-plist b/cad/p5-Verilog-Perl/pkg-plist
index 0a6ae7708d2f..3c4e572c2e3c 100644
--- a/cad/p5-Verilog-Perl/pkg-plist
+++ b/cad/p5-Verilog-Perl/pkg-plist
@@ -7,15 +7,17 @@ bin/vrename
 %%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Language.pm
 %%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist.pm
 %%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Cell.pm
+%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/ContAssign.pm
+%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Defparam.pm
 %%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/File.pm
 %%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Interface.pm
 %%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Logger.pm
+%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/ModPort.pm
 %%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Module.pm
 %%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Net.pm
 %%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Pin.pm
 %%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Port.pm
 %%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Subclass.pm
-%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/ContAssign.pm
 %%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Parser.pm
 %%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Preproc.pm
 %%SITE_PERL%%/%%PERL_ARCH%%/Verilog/SigParser.pm