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authorMark Linimon <linimon@FreeBSD.org>2003-12-17 16:02:50 +0000
committerMark Linimon <linimon@FreeBSD.org>2003-12-17 16:02:50 +0000
commit4805bf3d84ba064796fcaa9a3870afe3fe1ba365 (patch)
tree50d02062db46443032904134f207720485ba8bbb /cad/iverilog
parent- update COMMENT (diff)
Update to 20031202 snapshot. Summary of changes listed on
ftp://icarus.com/pub/eda/verilog/snapshots/verilog-20031202.txt: Combination 64bit/32bit runtime support now works fully on AMD64 systems; wait on lists of named events now works; there is no longer a common iverilog.conf, instead there are target specific foo.conf files with a new and cleaner format; 64bit values are more portably handled; several synthesis bugs related to the control inputs of flip-flops have been fixed. Committer is marking this BROKEN on 4.x while we investigate install problems. It works on 5.x only for now. PR: ports/60162 Submitted by: Joachim Strombergson <watchman@ludd.luth.se> (maintainer)
Notes
Notes: svn path=/head/; revision=96058
Diffstat (limited to 'cad/iverilog')
-rw-r--r--cad/iverilog/Makefile16
-rw-r--r--cad/iverilog/distinfo2
-rw-r--r--cad/iverilog/pkg-plist10
3 files changed, 20 insertions, 8 deletions
diff --git a/cad/iverilog/Makefile b/cad/iverilog/Makefile
index e805d41232e4..d52bdbf98235 100644
--- a/cad/iverilog/Makefile
+++ b/cad/iverilog/Makefile
@@ -7,20 +7,24 @@
#
PORTNAME= iverilog
-PORTVERSION= 0.7.20031009
+PORTVERSION= 0.7.20031202
CATEGORIES= cad
MASTER_SITES= ftp://icarus.com/pub/eda/verilog/snapshots/
-DISTNAME= verilog-20031009
+DISTNAME= verilog-20031202
MAINTAINER= watchman@ludd.luth.se
COMMENT= A Verilog simulation and synthesis tool
-BROKEN= "fails to compile - missing definition of TIME_FMT"
-
USE_BISON= yes
USE_GMAKE= yes
GNU_CONFIGURE= yes
-MAN1= iverilog-vpi.1 iverilog.1 vvp.1
+MAN1= iverilog-vpi.1 iverilog.1 vvp.1 iverilog-fpga.1
+
+.include <bsd.port.pre.mk>
+
+.if ${OSVERSION} <= 500000
+BROKEN= "Does not install on FreeBSD ${OSVERSION}"
+.endif
-.include <bsd.port.mk>
+.include <bsd.port.post.mk>
diff --git a/cad/iverilog/distinfo b/cad/iverilog/distinfo
index e8856032b242..79f67819869f 100644
--- a/cad/iverilog/distinfo
+++ b/cad/iverilog/distinfo
@@ -1 +1 @@
-MD5 (verilog-20031009.tar.gz) = d4d78212b4f7dde22555cdac5a52b468
+MD5 (verilog-20031202.tar.gz) = 14401d3da60ee3da3043523684fbb442
diff --git a/cad/iverilog/pkg-plist b/cad/iverilog/pkg-plist
index dd107f35a86f..00d41c3316ce 100644
--- a/cad/iverilog/pkg-plist
+++ b/cad/iverilog/pkg-plist
@@ -5,14 +5,22 @@ include/acc_user.h
include/ivl_target.h
include/veriuser.h
include/vpi_user.h
+include/_pli_types.h
lib/ivl/cadpli.vpl
+lib/ivl/fpga-s.conf
+lib/ivl/fpga.conf
lib/ivl/fpga.tgt
-lib/ivl/iverilog.conf
lib/ivl/ivl
lib/ivl/ivlpp
+lib/ivl/null-s.conf
+lib/ivl/null.conf
lib/ivl/null.tgt
lib/ivl/system.vpi
+lib/ivl/vvp-s.conf
+lib/ivl/vvp.conf
lib/ivl/vvp.tgt
+lib/ivl/xnf-s.conf
+lib/ivl/xnf.conf
lib/libveriuser.a
lib/libvpi.a
@dirrm lib/ivl