diff options
author | Robert Clausecker <fuz@fuz.su> | 2022-08-01 22:26:50 +0200 |
---|---|---|
committer | Kurt Jaeger <pi@FreeBSD.org> | 2022-08-01 22:28:49 +0200 |
commit | fc3a761d2cfc293c26264d2fc126914943e2e839 (patch) | |
tree | 18def850de9de3cbbb7f100d861ec1bb39953326 | |
parent | math/py-brial: upgrade to 1.2.11 (diff) |
benchmarks/uica: New port: uops.info Code Analyzer
uiCA is a simulator that can predict the throughput of basic blocks on
recent Intel microarchitectures. In addition to that, it also provides
insights into how the code is executed.
uiCA is based on data from uops.info, combined with a detailed pipeline
model. Like related tools, it assumes that all memory accesses result in
cache hits.
WWW: https://uops.info/uiCA.html
Author: Robert Clausecker <fuz@fuz.su>
PR: 265368
-rw-r--r-- | benchmarks/Makefile | 1 | ||||
-rw-r--r-- | benchmarks/uica/Makefile | 60 | ||||
-rw-r--r-- | benchmarks/uica/distinfo | 9 | ||||
-rw-r--r-- | benchmarks/uica/files/patch-mbuild_mbuild_env.py | 11 | ||||
-rw-r--r-- | benchmarks/uica/files/patch-uiCA.py | 11 | ||||
-rw-r--r-- | benchmarks/uica/pkg-descr | 9 | ||||
-rw-r--r-- | benchmarks/uica/pkg-plist | 36 |
7 files changed, 137 insertions, 0 deletions
diff --git a/benchmarks/Makefile b/benchmarks/Makefile index e69aff16bfd2..227bd227ef85 100644 --- a/benchmarks/Makefile +++ b/benchmarks/Makefile @@ -106,6 +106,7 @@ SUBDIR += ttcp SUBDIR += typometer SUBDIR += ubench + SUBDIR += uica SUBDIR += unixbench SUBDIR += uperf SUBDIR += vegeta diff --git a/benchmarks/uica/Makefile b/benchmarks/uica/Makefile new file mode 100644 index 000000000000..cde83e77dd50 --- /dev/null +++ b/benchmarks/uica/Makefile @@ -0,0 +1,60 @@ +PORTNAME= uiCA +PORTVERSION= g20220630+${INSTRVERSION} +CATEGORIES= benchmarks devel +MASTER_SITES= https://uops.info/instructions.xml?dummy=/:instructions \ + https://uops.info/:instructions +PKGNAMEPREFIX= ${PYTHON_PKGNAMEPREFIX} +DISTFILES= ${INSTRUCTIONS}:instructions +EXTRACT_ONLY= ${DISTFILES:C,:[^:]*$,,:N*.xml} + +MAINTAINER= fuz@fuz.su +COMMENT= Code Analyzer from the uops.info project + +LICENSE= AGPLv3 APACHE20 +LICENSE_COMB= multi + +BUILD_DEPENDS= ${PYTHON_PKGNAMEPREFIX}setuptools>0:devel/py-setuptools@${PY_FLAVOR} +RUN_DEPENDS= ${PYTHON_PKGNAMEPREFIX}plotly>0:graphics/py-plotly@${PY_FLAVOR} + +USES= compiler python shebangfix +USE_GITHUB= yes +GH_ACCOUNT= andreas-abel +GH_TAGNAME= ba6ad5557ebd96a10fa0d0e076c9961ec5024574 +GH_TUPLE= andreas-abel:XED-to-XML:c71679ee893ae91db677056d542f305fcc433cb1:xed/XED-to-XML \ + intelxed:mbuild:09b6654be0c52bf1df44e88c88b411a67b624cbd:mbuild/mbuild +USE_PYTHON= concurrent flavors +SHEBANG_FILES= uiCA.py + +# manually build a file name like instructions_Apr2022.xml from +# the machine-sortable INSTRVERSION. Use := to have date run only once +INSTRVERSION= 2022.04 +INSTRUCTIONS:= instructions_${LC_ALL=C date -j -f %Y.%m ${INSTRVERSION} +%b%Y:L:sh}.xml + +MFLAGS= --compiler=${COMPILER_TYPE:S/gcc/gnu/} \ + --cc=${CC} \ + --cxx=${CXX} \ + --strip=${STRIP_CMD} \ + --extra-ccflags='${CFLAGS}' \ + --extra-cxxflags='${CXXFLAGS}' \ + --extra-linkflags='${LDFLAGS}' + +do-configure: + ${REINPLACE_CMD} -e 's,%%DATADIR%%,${DATADIR},' ${WRKSRC}/uiCA.py + +do-build: + (cd ${WRKSRC}/XED-to-XML && ${PYTHON_CMD} mfile.py ${MFLAGS} --no-encoder pymodule) + ${LN} -f ${WRKSRC}/XED-to-XML/xed.* ${WRKSRC}/ + (cd ${WRKSRC} && ${PYTHON_CMD} convertXML.py ${DISTDIR}/${INSTRUCTIONS}) + ${RM} -r ${WRKSRC}/__pycache__ +.for f in microArchConfigs.py uiCA.py x64_lib.py instrData + ${PYTHON_CMD} -m compileall ${WRKSRC}/$f +.endfor + +do-install: + ${MKDIR} ${STAGEDIR}${DATADIR} ${STAGEDIR}${PYTHON_LIBDIR}/lib-dynload/ + ${INSTALL_DATA} ${WRKSRC}/traceTemplate.html ${STAGEDIR}${DATADIR}/ + ${INSTALL_LIB} ${WRKSRC}/xed${PYTHON_EXT_SUFFIX}.so ${STAGEDIR}${PYTHON_LIBDIR}/lib-dynload/ + (cd ${WRKSRC} && ${COPYTREE_SHARE} '__pycache__ instrData microArchConfigs.py x64_lib.py' ${STAGEDIR}${PYTHON_LIBDIR}) + ${INSTALL_SCRIPT} ${WRKSRC}/uiCA.py ${STAGEDIR}${PREFIX}/bin/uiCA + +.include <bsd.port.mk> diff --git a/benchmarks/uica/distinfo b/benchmarks/uica/distinfo new file mode 100644 index 000000000000..ecdee48dc4bb --- /dev/null +++ b/benchmarks/uica/distinfo @@ -0,0 +1,9 @@ +TIMESTAMP = 1658429663 +SHA256 (instructions_Apr2022.xml) = 5f495e61df55443f06de73b7567d29ec3f3d097db135ee55b9ab89fcae75d4fc +SIZE (instructions_Apr2022.xml) = 109323644 +SHA256 (andreas-abel-uiCA-g20220630+2022.04-ba6ad5557ebd96a10fa0d0e076c9961ec5024574_GH0.tar.gz) = 93d78e9d380eed1a7f8828b762e60e371898a8b3d6bc0cf3cfca8d3bed199872 +SIZE (andreas-abel-uiCA-g20220630+2022.04-ba6ad5557ebd96a10fa0d0e076c9961ec5024574_GH0.tar.gz) = 46859 +SHA256 (andreas-abel-XED-to-XML-c71679ee893ae91db677056d542f305fcc433cb1_GH0.tar.gz) = b610897d541cf808cfbf53c5a9abe384e7ca2cac25939e994a737d3bcfa00c35 +SIZE (andreas-abel-XED-to-XML-c71679ee893ae91db677056d542f305fcc433cb1_GH0.tar.gz) = 1286967 +SHA256 (intelxed-mbuild-09b6654be0c52bf1df44e88c88b411a67b624cbd_GH0.tar.gz) = 5af6b3f0394df1332dd2f09d842719bd2ece1037c09cd042f18e417dddf1e54e +SIZE (intelxed-mbuild-09b6654be0c52bf1df44e88c88b411a67b624cbd_GH0.tar.gz) = 81598 diff --git a/benchmarks/uica/files/patch-mbuild_mbuild_env.py b/benchmarks/uica/files/patch-mbuild_mbuild_env.py new file mode 100644 index 000000000000..45cb5d02ebe1 --- /dev/null +++ b/benchmarks/uica/files/patch-mbuild_mbuild_env.py @@ -0,0 +1,11 @@ +--- mbuild/mbuild/env.py.orig 2021-04-16 20:40:24 UTC ++++ mbuild/mbuild/env.py +@@ -1237,6 +1237,8 @@ class env_t(object): + return 'ia32' + elif name in ['aarch64', 'arm64']: + return 'aarch64' ++ elif name[0:3] == 'arm': ++ return 'arm' + else: + die("Unknown cpu " + name) + diff --git a/benchmarks/uica/files/patch-uiCA.py b/benchmarks/uica/files/patch-uiCA.py new file mode 100644 index 000000000000..b8dfa686b899 --- /dev/null +++ b/benchmarks/uica/files/patch-uiCA.py @@ -0,0 +1,11 @@ +--- uiCA.py.orig 2022-07-21 20:16:37 UTC ++++ uiCA.py +@@ -2077,7 +2077,7 @@ def generateHTMLTraceTable(filename, instructions, ins + uopData['events'][evCycle] = ev + prevInstrI = instrI + +- with open(os.path.join(os.path.dirname(os.path.realpath(__file__)), 'traceTemplate.html'), 'r') as t: ++ with open('%%DATADIR%%/traceTemplate.html', 'r') as t: + html = t.read() + html = html.replace('var tableData = {}', 'var tableData = ' + json.dumps(tableDataForRnd)) + diff --git a/benchmarks/uica/pkg-descr b/benchmarks/uica/pkg-descr new file mode 100644 index 000000000000..6e14e16b741a --- /dev/null +++ b/benchmarks/uica/pkg-descr @@ -0,0 +1,9 @@ +uiCA is a simulator that can predict the throughput of basic blocks on +recent Intel microarchitectures. In addition to that, it also provides +insights into how the code is executed. + +uiCA is based on data from uops.info, combined with a detailed pipeline +model. Like related tools, it assumes that all memory accesses result in +cache hits. + +WWW: https://uops.info/uiCA.html diff --git a/benchmarks/uica/pkg-plist b/benchmarks/uica/pkg-plist new file mode 100644 index 000000000000..fe9a4d5cf32d --- /dev/null +++ b/benchmarks/uica/pkg-plist @@ -0,0 +1,36 @@ +bin/uiCA +%%PYTHON_LIBDIR%%/__pycache__/microArchConfigs%%PYTHON_EXT_SUFFIX%%.pyc +%%PYTHON_LIBDIR%%/__pycache__/uiCA%%PYTHON_EXT_SUFFIX%%.pyc +%%PYTHON_LIBDIR%%/__pycache__/x64_lib%%PYTHON_EXT_SUFFIX%%.pyc +%%PYTHON_LIBDIR%%/instrData/BDW.py +%%PYTHON_LIBDIR%%/instrData/CFL.py +%%PYTHON_LIBDIR%%/instrData/CLX.py +%%PYTHON_LIBDIR%%/instrData/HSW.py +%%PYTHON_LIBDIR%%/instrData/ICL.py +%%PYTHON_LIBDIR%%/instrData/IVB.py +%%PYTHON_LIBDIR%%/instrData/KBL.py +%%PYTHON_LIBDIR%%/instrData/RKL.py +%%PYTHON_LIBDIR%%/instrData/SKL.py +%%PYTHON_LIBDIR%%/instrData/SKX.py +%%PYTHON_LIBDIR%%/instrData/SNB.py +%%PYTHON_LIBDIR%%/instrData/TGL.py +%%PYTHON_LIBDIR%%/instrData/__init__.py +%%PYTHON_LIBDIR%%/instrData/__pycache__/BDW%%PYTHON_EXT_SUFFIX%%.pyc +%%PYTHON_LIBDIR%%/instrData/__pycache__/CFL%%PYTHON_EXT_SUFFIX%%.pyc +%%PYTHON_LIBDIR%%/instrData/__pycache__/CLX%%PYTHON_EXT_SUFFIX%%.pyc +%%PYTHON_LIBDIR%%/instrData/__pycache__/HSW%%PYTHON_EXT_SUFFIX%%.pyc +%%PYTHON_LIBDIR%%/instrData/__pycache__/ICL%%PYTHON_EXT_SUFFIX%%.pyc +%%PYTHON_LIBDIR%%/instrData/__pycache__/IVB%%PYTHON_EXT_SUFFIX%%.pyc +%%PYTHON_LIBDIR%%/instrData/__pycache__/KBL%%PYTHON_EXT_SUFFIX%%.pyc +%%PYTHON_LIBDIR%%/instrData/__pycache__/RKL%%PYTHON_EXT_SUFFIX%%.pyc +%%PYTHON_LIBDIR%%/instrData/__pycache__/SKL%%PYTHON_EXT_SUFFIX%%.pyc +%%PYTHON_LIBDIR%%/instrData/__pycache__/SKX%%PYTHON_EXT_SUFFIX%%.pyc +%%PYTHON_LIBDIR%%/instrData/__pycache__/SNB%%PYTHON_EXT_SUFFIX%%.pyc +%%PYTHON_LIBDIR%%/instrData/__pycache__/TGL%%PYTHON_EXT_SUFFIX%%.pyc +%%PYTHON_LIBDIR%%/instrData/__pycache__/__init__%%PYTHON_EXT_SUFFIX%%.pyc +%%PYTHON_LIBDIR%%/instrData/__pycache__/uArchInfo%%PYTHON_EXT_SUFFIX%%.pyc +%%PYTHON_LIBDIR%%/instrData/uArchInfo.py +%%PYTHON_LIBDIR%%/lib-dynload/xed%%PYTHON_EXT_SUFFIX%%.so +%%PYTHON_LIBDIR%%/microArchConfigs.py +%%PYTHON_LIBDIR%%/x64_lib.py +%%DATADIR%%/traceTemplate.html |