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--- v8/src/wasm/baseline/ia32/liftoff-assembler-ia32.h.orig 2023-11-04 07:08:51 UTC
+++ v8/src/wasm/baseline/ia32/liftoff-assembler-ia32.h
@@ -492,7 +492,7 @@ void LiftoffAssembler::StoreTaggedPointer(Register dst
}
void LiftoffAssembler::Load(LiftoffRegister dst, Register src_addr,
- Register offset_reg, uint32_t offset_imm,
+ Register offset_reg, uintptr_t offset_imm,
LoadType type, uint32_t* protected_load_pc,
bool /* is_load_mem */, bool /* i64_offset */,
bool needs_shift) {
@@ -572,7 +572,7 @@ void LiftoffAssembler::Load(LiftoffRegister dst, Regis
}
void LiftoffAssembler::Store(Register dst_addr, Register offset_reg,
- uint32_t offset_imm, LiftoffRegister src,
+ uintptr_t offset_imm, LiftoffRegister src,
StoreType type, LiftoffRegList pinned,
uint32_t* protected_store_pc,
bool /* is_store_mem */, bool /* i64_offset */) {
@@ -652,7 +652,7 @@ void LiftoffAssembler::Store(Register dst_addr, Regist
}
void LiftoffAssembler::AtomicLoad(LiftoffRegister dst, Register src_addr,
- Register offset_reg, uint32_t offset_imm,
+ Register offset_reg, uintptr_t offset_imm,
LoadType type, LiftoffRegList /* pinned */,
bool /* i64_offset */) {
if (type.value() != LoadType::kI64Load) {
@@ -672,7 +672,7 @@ void LiftoffAssembler::AtomicLoad(LiftoffRegister dst,
}
void LiftoffAssembler::AtomicStore(Register dst_addr, Register offset_reg,
- uint32_t offset_imm, LiftoffRegister src,
+ uintptr_t offset_imm, LiftoffRegister src,
StoreType type, LiftoffRegList pinned,
bool /* i64_offset */) {
DCHECK_NE(offset_reg, no_reg);
@@ -742,7 +742,7 @@ enum Binop { kAdd, kSub, kAnd, kOr, kXor, kExchange };
inline void AtomicAddOrSubOrExchange32(LiftoffAssembler* lasm, Binop binop,
Register dst_addr, Register offset_reg,
- uint32_t offset_imm,
+ uintptr_t offset_imm,
LiftoffRegister value,
LiftoffRegister result, StoreType type) {
DCHECK_EQ(value, result);
@@ -809,7 +809,7 @@ inline void AtomicAddOrSubOrExchange32(LiftoffAssemble
}
inline void AtomicBinop32(LiftoffAssembler* lasm, Binop op, Register dst_addr,
- Register offset_reg, uint32_t offset_imm,
+ Register offset_reg, uintptr_t offset_imm,
LiftoffRegister value, LiftoffRegister result,
StoreType type) {
DCHECK_EQ(value, result);
@@ -921,7 +921,7 @@ inline void AtomicBinop32(LiftoffAssembler* lasm, Bino
}
inline void AtomicBinop64(LiftoffAssembler* lasm, Binop op, Register dst_addr,
- Register offset_reg, uint32_t offset_imm,
+ Register offset_reg, uintptr_t offset_imm,
LiftoffRegister value, LiftoffRegister result) {
// We need {ebx} here, which is the root register. As the root register it
// needs special treatment. As we use {ebx} directly in the code below, we
@@ -1013,7 +1013,7 @@ inline void AtomicBinop64(LiftoffAssembler* lasm, Bino
} // namespace liftoff
void LiftoffAssembler::AtomicAdd(Register dst_addr, Register offset_reg,
- uint32_t offset_imm, LiftoffRegister value,
+ uintptr_t offset_imm, LiftoffRegister value,
LiftoffRegister result, StoreType type,
bool /* i64_offset */) {
if (type.value() == StoreType::kI64Store) {
@@ -1027,7 +1027,7 @@ void LiftoffAssembler::AtomicAdd(Register dst_addr, Re
}
void LiftoffAssembler::AtomicSub(Register dst_addr, Register offset_reg,
- uint32_t offset_imm, LiftoffRegister value,
+ uintptr_t offset_imm, LiftoffRegister value,
LiftoffRegister result, StoreType type,
bool /* i64_offset */) {
if (type.value() == StoreType::kI64Store) {
@@ -1040,7 +1040,7 @@ void LiftoffAssembler::AtomicSub(Register dst_addr, Re
}
void LiftoffAssembler::AtomicAnd(Register dst_addr, Register offset_reg,
- uint32_t offset_imm, LiftoffRegister value,
+ uintptr_t offset_imm, LiftoffRegister value,
LiftoffRegister result, StoreType type,
bool /* i64_offset */) {
if (type.value() == StoreType::kI64Store) {
@@ -1054,7 +1054,7 @@ void LiftoffAssembler::AtomicAnd(Register dst_addr, Re
}
void LiftoffAssembler::AtomicOr(Register dst_addr, Register offset_reg,
- uint32_t offset_imm, LiftoffRegister value,
+ uintptr_t offset_imm, LiftoffRegister value,
LiftoffRegister result, StoreType type,
bool /* i64_offset */) {
if (type.value() == StoreType::kI64Store) {
@@ -1068,7 +1068,7 @@ void LiftoffAssembler::AtomicOr(Register dst_addr, Reg
}
void LiftoffAssembler::AtomicXor(Register dst_addr, Register offset_reg,
- uint32_t offset_imm, LiftoffRegister value,
+ uintptr_t offset_imm, LiftoffRegister value,
LiftoffRegister result, StoreType type,
bool /* i64_offset */) {
if (type.value() == StoreType::kI64Store) {
@@ -1082,7 +1082,7 @@ void LiftoffAssembler::AtomicXor(Register dst_addr, Re
}
void LiftoffAssembler::AtomicExchange(Register dst_addr, Register offset_reg,
- uint32_t offset_imm,
+ uintptr_t offset_imm,
LiftoffRegister value,
LiftoffRegister result, StoreType type,
bool /* i64_offset */) {
@@ -1097,7 +1097,7 @@ void LiftoffAssembler::AtomicExchange(Register dst_add
}
void LiftoffAssembler::AtomicCompareExchange(
- Register dst_addr, Register offset_reg, uint32_t offset_imm,
+ Register dst_addr, Register offset_reg, uintptr_t offset_imm,
LiftoffRegister expected, LiftoffRegister new_value, LiftoffRegister result,
StoreType type, bool /* i64_offset */) {
// We expect that the offset has already been added to {dst_addr}, and no
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