| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | add iverilog, a Verilog simulation and synthesis tool | Ying-Chieh Liao | 2001-02-13 | 1 | -0/+1 |
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index : freebsd/ports.git | |
| Unnamed repository; edit this file 'description' to name the repository. | git |
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