| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | upgrade to 2.12.a | Ying-Chieh Liao | 2007-07-21 | 1 | -3/+3 |
| * | [NEW PORT] cad/gplcver: A Verilog HDL simulator | Edwin Groothuis | 2005-12-29 | 1 | -0/+3 |
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index : freebsd/ports.git | |
| Unnamed repository; edit this file 'description' to name the repository. | git |
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