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-rw-r--r--cad/yosys-systemverilog/Makefile1
1 files changed, 1 insertions, 0 deletions
diff --git a/cad/yosys-systemverilog/Makefile b/cad/yosys-systemverilog/Makefile
index f7b6e2d8c631..a65978527163 100644
--- a/cad/yosys-systemverilog/Makefile
+++ b/cad/yosys-systemverilog/Makefile
@@ -1,5 +1,6 @@
PORTNAME= yosys-systemverilog
DISTVERSION= 2023-06-14
+PORTREVISION= 1
CATEGORIES= cad
PKGNAMEPREFIX=