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-rw-r--r--cad/verilog-mode.el/Makefile2
1 files changed, 0 insertions, 2 deletions
diff --git a/cad/verilog-mode.el/Makefile b/cad/verilog-mode.el/Makefile
index f7ac3f6dced2..ec591ce34f7e 100644
--- a/cad/verilog-mode.el/Makefile
+++ b/cad/verilog-mode.el/Makefile
@@ -1,5 +1,3 @@
-# Created by: stas
-
PORTNAME= verilog-mode.el
PORTVERSION= 801
PORTREVISION= 13