summaryrefslogtreecommitdiff
path: root/cad/verilog-mode.el/Makefile
diff options
context:
space:
mode:
Diffstat (limited to 'cad/verilog-mode.el/Makefile')
-rw-r--r--cad/verilog-mode.el/Makefile8
1 files changed, 3 insertions, 5 deletions
diff --git a/cad/verilog-mode.el/Makefile b/cad/verilog-mode.el/Makefile
index 07c6d8c9265b..1f5810760781 100644
--- a/cad/verilog-mode.el/Makefile
+++ b/cad/verilog-mode.el/Makefile
@@ -1,9 +1,5 @@
-# New ports collection makefile for: verilog-mode.el
-# Date created: 12 January 2009
-# Whom: stas
-#
+# Created by: stas
# $FreeBSD$
-#
PORTNAME= verilog-mode.el
PORTVERSION= 801
@@ -18,6 +14,8 @@ COMMENT= Emacs lisp modules for the Verilog language
LICENSE= GPLv3 # (or later)
+EXTRACT_CMD= ${GZCAT}
+EXTRACT_BEFORE_ARGS= #
EXTRACT_AFTER_ARGS= > ${PORTNAME}
NO_WRKSUBDIR= yes