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-rw-r--r--cad/iverilog/Makefile4
-rw-r--r--cad/iverilog/distinfo4
2 files changed, 4 insertions, 4 deletions
diff --git a/cad/iverilog/Makefile b/cad/iverilog/Makefile
index 2f4fe2e4635f..c7e3001dc9ad 100644
--- a/cad/iverilog/Makefile
+++ b/cad/iverilog/Makefile
@@ -7,10 +7,10 @@
#
PORTNAME= iverilog
-PORTVERSION= 0.7.20040220
+PORTVERSION= 0.7.20040606
CATEGORIES= cad
MASTER_SITES= ftp://icarus.com/pub/eda/verilog/snapshots/
-DISTNAME= verilog-20040220
+DISTNAME= verilog-20040606
MAINTAINER= watchman@ludd.luth.se
COMMENT= A Verilog simulation and synthesis tool
diff --git a/cad/iverilog/distinfo b/cad/iverilog/distinfo
index 1030f8c3da09..c8740fa834c1 100644
--- a/cad/iverilog/distinfo
+++ b/cad/iverilog/distinfo
@@ -1,2 +1,2 @@
-MD5 (verilog-20040220.tar.gz) = 208d579866e9904a385296220104dcb2
-SIZE (verilog-20040220.tar.gz) = 1354505
+MD5 (verilog-20040606.tar.gz) = 92704dec05a832dc9bf1cb3ba399176a
+SIZE (verilog-20040606.tar.gz) = 1361219