diff options
| -rw-r--r-- | cad/Makefile | 1 | ||||
| -rw-r--r-- | cad/iverilog/Makefile | 23 | ||||
| -rw-r--r-- | cad/iverilog/distinfo | 1 | ||||
| -rw-r--r-- | cad/iverilog/pkg-comment | 1 | ||||
| -rw-r--r-- | cad/iverilog/pkg-descr | 15 | ||||
| -rw-r--r-- | cad/iverilog/pkg-plist | 19 |
6 files changed, 60 insertions, 0 deletions
diff --git a/cad/Makefile b/cad/Makefile index c890bbd60e6f..1432f3131abe 100644 --- a/cad/Makefile +++ b/cad/Makefile @@ -8,6 +8,7 @@ SUBDIR += felt SUBDIR += geda SUBDIR += irsim + SUBDIR += iverilog SUBDIR += kaskade SUBDIR += magic SUBDIR += mars diff --git a/cad/iverilog/Makefile b/cad/iverilog/Makefile new file mode 100644 index 000000000000..a85697016343 --- /dev/null +++ b/cad/iverilog/Makefile @@ -0,0 +1,23 @@ +# ex:ts=8 +# New ports collection makefile for: iverilog +# Date created: Feb 13, 2001 +# Whom: Ying-Chieh Liao <ijliao@FreeBSD.org> +# +# $FreeBSD$ +# + +PORTNAME= iverilog +PORTVERSION= 0.4 +CATEGORIES= cad +MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v${PORTVERSION}/ +DISTNAME= verilog-${PORTVERSION} + +MAINTAINER= ijliao@FreeBSD.org + +GNU_CONFIGURE= yes + +USE_GMAKE= yes + +MAN1= iverilog.1 + +.include <bsd.port.mk> diff --git a/cad/iverilog/distinfo b/cad/iverilog/distinfo new file mode 100644 index 000000000000..1d357d6b33f0 --- /dev/null +++ b/cad/iverilog/distinfo @@ -0,0 +1 @@ +MD5 (verilog-0.4.tar.gz) = d2b0c7c1480ffb2ad1b440bded97e419 diff --git a/cad/iverilog/pkg-comment b/cad/iverilog/pkg-comment new file mode 100644 index 000000000000..55674ec9ee77 --- /dev/null +++ b/cad/iverilog/pkg-comment @@ -0,0 +1 @@ +Icarus Verilog is a Verilog simulation and synthesis tool diff --git a/cad/iverilog/pkg-descr b/cad/iverilog/pkg-descr new file mode 100644 index 000000000000..39739afe9bc5 --- /dev/null +++ b/cad/iverilog/pkg-descr @@ -0,0 +1,15 @@ +Icarus Verilog is a Verilog simulation and synthesis tool. It +operates as a compiler, compiling source code writen in Verilog +(IEEE-1364) into some target format. For batch simulation, the +compiler can generate C++ code that is compiled and linked with +a run time library (called "vvm") then executed as a command to +run the simulation. For synthesis, the compiler generates netlists +in the desired format. + +The compiler proper is intended to parse and elaborate design +descriptions written to the IEEE standard IEEE Std 1364-2000. The +standard proper is due to be release towards the middle of the +year 2000. This is a fairly large and complex standard, so it will +take some time for it to get there, but that's the goal. + +WWW: http://www.icarus.com/eda/verilog/ diff --git a/cad/iverilog/pkg-plist b/cad/iverilog/pkg-plist new file mode 100644 index 000000000000..ef6c70e229b1 --- /dev/null +++ b/cad/iverilog/pkg-plist @@ -0,0 +1,19 @@ +bin/iverilog +include/ivl_target.h +include/vvm.h +include/vpi_priv.h +include/vvm_func.h +include/vvm_gates.h +include/vvm_nexus.h +include/vvm_signal.h +include/vvm_thread.h +include/vvm_calltf.h +include/vpi_user.h +lib/ivl/ivl +lib/ivl/iverilog.conf +lib/ivl/system.vpi +lib/ivl/ivlpp +lib/ivl/null.tgt +lib/libvvm.a +lib/libvpip.a +@dirrm lib/ivl |