Add sjog 0.5, a userland daemon for Sony Vaio Jog Dial.

PR:		41905
Submitted by:	Bruce M Simpson <bms@spc.org>

15 files changed, 1186 insertions, 0 deletions

diff --git a/sysutils/sjog/Makefile b/sysutils/sjog/Makefile
new file mode 100644
index 000000000000..60e7ae4b1a2d
--- /dev/null
+++ b/sysutils/sjog/Makefile
@@ -0,0 +1,23 @@
+# New ports collection makefile for:	sjog
+# Date created:		17 August 2002
+# Whom:			Bruce M Simpson <bms@spc.org>
+#
+# $FreeBSD$
+#
+
+PORTNAME=	sjog
+PORTVERSION=	0.5
+CATEGORIES=	sysutils
+MASTER_SITES=	${MASTER_SITE_SOURCEFORGE}
+MASTER_SITE_SUBDIR=	${PORTNAME}
+
+MAINTAINER=	bms@spc.org
+
+USE_AUTOMAKE=	yes
+GNU_CONFIGURE=  yes
+USE_GTK=        yes
+USE_GMAKE=      yes
+
+NOMAN=
+
+.include <bsd.port.mk>
diff --git a/sysutils/sjog/distinfo b/sysutils/sjog/distinfo
new file mode 100644
index 000000000000..d691c8948198
--- /dev/null
+++ b/sysutils/sjog/distinfo
@@ -0,0 +1 @@
+MD5 (sjog-0.5.tar.gz) = 54c79675e5feb4a16a97901f6c7c5677
diff --git a/sysutils/sjog/files/patch-setbrightness::Makefile.am b/sysutils/sjog/files/patch-setbrightness::Makefile.am
new file mode 100644
index 000000000000..3f32f29e6b3c
--- /dev/null
+++ b/sysutils/sjog/files/patch-setbrightness::Makefile.am
@@ -0,0 +1,13 @@
+--- setbrightness/Makefile.am.orig	Wed Apr  4 11:20:07 2001
++++ setbrightness/Makefile.am	Sat Aug 17 20:38:56 2002
+@@ -2,7 +2,9 @@
+ 
+ bin_PROGRAMS = setbrightness
+  
+-setbrightness_SOURCES = setbrightness.c
++setbrightness_SOURCES = setbrightness.c 
++
++LDADD = ../src/sonypi.o ../src/pci_freebsd.o
+ 
+ MAINTAINERCLEANFILES = Makefile.in Makefile
+ 
diff --git a/sysutils/sjog/files/patch-setbrightness::setbrightness.c b/sysutils/sjog/files/patch-setbrightness::setbrightness.c
new file mode 100644
index 000000000000..c1a8962fd0e4
--- /dev/null
+++ b/sysutils/sjog/files/patch-setbrightness::setbrightness.c
@@ -0,0 +1,86 @@
+--- setbrightness/setbrightness.c.orig	Sat Jul 28 18:16:22 2001
++++ setbrightness/setbrightness.c	Sat Aug 17 20:38:56 2002
+@@ -1,44 +1,58 @@
++/* FreeBSD modifications by Jay Kuri jk@oneway.com 08/13/01 */
++
+ #define _XOPEN_SOURCE 500
+ #include <stdio.h>
+ #include <stdlib.h>
+ #include <unistd.h>
+ #include <fcntl.h>
+ #include <errno.h>
++#ifndef __FreeBSD__
+ #include <sys/io.h>
++#endif
+ #include <sys/mman.h>
+ #include <dirent.h>
+ #include <ctype.h>
+ #include <malloc.h>
+ #include <string.h>
+ #include <signal.h>
++#ifndef __FreeBSD__
+ #include <getopt.h>
+ #include <linux/pci.h>
++#endif
+ #include <sys/time.h>
++#ifdef __FreeBSD__
++#include <machine/cpufunc.h>
++#include "../src/sonypi.h"
++#endif
+ 
+ 
+ #define BRIGHTNESS 0x96
+ #define DATA_REG 0x62
+ #define CST_REG  0x66
+ 
++#ifndef __FreeBSD__
+ typedef unsigned short u16;
++#define OUTW outw
++#define OUTB outb
++#endif
+ 
+ static void ecr_set(u16 value)
+ {
+ 	while (inw(CST_REG) & 3) usleep(1);
+-	outw(0x81, CST_REG);
++	OUTW(0x81, CST_REG);
+ 	while (inw(CST_REG) & 2) usleep(1);
+-	outw(BRIGHTNESS, DATA_REG);
++	OUTW(BRIGHTNESS, DATA_REG);
+ 	while (inw(CST_REG) & 2) usleep(1);
+-	outw(value, DATA_REG);
++	OUTW(value, DATA_REG);
+ 	while (inw(CST_REG) & 2) usleep(1);
+ }
+ 
+ static u16 ecr_get()
+ {
+ 	while (inw(CST_REG) & 3) usleep(1);
+-	outb(0x80, CST_REG);
++	OUTB(0x80, CST_REG);
+ 	while (inw(CST_REG) & 2) usleep(1);
+-	outb(BRIGHTNESS, DATA_REG);
++	OUTB(BRIGHTNESS, DATA_REG);
+ 	while (inw(CST_REG) & 2) usleep(1);
+ 	return (inw(DATA_REG)&255);
+ }
+@@ -52,14 +66,17 @@
+ int main(int argc, char *argv[])
+ {
+ 
++#ifndef __FreeBSD__
+ 	ioperm(DATA_REG, 0x08, 1); 
++#endif
+         if( geteuid() != 0 )
+                 fprintf(stdout, "You must be root to use %s\n", argv[0]);
+ 
+         else if( argc == 2 && strcmp(argv[1], "--read") == 0) 
++	{
++	    iopl(3);
+ 	    printf("%d\n", ecr_get());
+-
+-        else if( argc != 2 || !isdigit(argv[1][0])) 
++	} else if( argc != 2 || !isdigit(argv[1][0])) 
+                 usage();
+ 
+         else
diff --git a/sysutils/sjog/files/patch-src::Makefile.am b/sysutils/sjog/files/patch-src::Makefile.am
new file mode 100644
index 000000000000..8128a6d989e9
--- /dev/null
+++ b/sysutils/sjog/files/patch-src::Makefile.am
@@ -0,0 +1,15 @@
+--- src/Makefile.am.orig	Fri Aug  3 08:29:27 2001
++++ src/Makefile.am	Sat Aug 17 20:43:55 2002
+@@ -28,7 +28,11 @@
+                 sjog_volume_callbacks.c \
+                 sjog_volume_callbacks.h \
+                 sjog_scroll.c \
+-                sjog_scroll.h
++                sjog_scroll.h \
++		sonypi.h \
++		sonypi.c \
++		pci_freebsd.c \
++		pci.h
+ 
+ sjog_LDADD = @GTK_LIBS@ @GLIB_LIBS@ @X_LIBS@
+ 
diff --git a/sysutils/sjog/files/patch-src::pci.h b/sysutils/sjog/files/patch-src::pci.h
new file mode 100644
index 000000000000..9cf41de5e5cc
--- /dev/null
+++ b/sysutils/sjog/files/patch-src::pci.h
@@ -0,0 +1,278 @@
+--- src/pci.h.orig	Sat Aug 17 20:38:56 2002
++++ src/pci.h	Sat Aug 17 20:38:56 2002
+@@ -0,0 +1,275 @@
++/*
++ *	$Id: pci.h,v 1.87 1998/10/11 15:13:12 mj Exp $
++ *
++ *	PCI defines and function prototypes
++ *	Copyright 1994, Drew Eckhardt
++ *	Copyright 1997--1999 Martin Mares <mj@suse.cz>
++ *
++ *	For more information, please consult the following manuals (look at
++ *	http://www.pcisig.com/ for how to get them):
++ *
++ *	PCI BIOS Specification
++ *	PCI Local Bus Specification
++ *	PCI to PCI Bridge Specification
++ *	PCI System Design Guide
++ */
++
++#ifndef LINUX_PCI_H
++#define LINUX_PCI_H
++
++/*
++ * Under PCI, each device has 256 bytes of configuration address space,
++ * of which the first 64 bytes are standardized as follows:
++ */
++#define PCI_VENDOR_ID		0x00	/* 16 bits */
++#define PCI_DEVICE_ID		0x02	/* 16 bits */
++#define PCI_COMMAND		0x04	/* 16 bits */
++#define  PCI_COMMAND_IO		0x1	/* Enable response in I/O space */
++#define  PCI_COMMAND_MEMORY	0x2	/* Enable response in Memory space */
++#define  PCI_COMMAND_MASTER	0x4	/* Enable bus mastering */
++#define  PCI_COMMAND_SPECIAL	0x8	/* Enable response to special cycles */
++#define  PCI_COMMAND_INVALIDATE	0x10	/* Use memory write and invalidate */
++#define  PCI_COMMAND_VGA_PALETTE 0x20	/* Enable palette snooping */
++#define  PCI_COMMAND_PARITY	0x40	/* Enable parity checking */
++#define  PCI_COMMAND_WAIT 	0x80	/* Enable address/data stepping */
++#define  PCI_COMMAND_SERR	0x100	/* Enable SERR */
++#define  PCI_COMMAND_FAST_BACK	0x200	/* Enable back-to-back writes */
++
++#define PCI_STATUS		0x06	/* 16 bits */
++#define  PCI_STATUS_CAP_LIST	0x10	/* Support Capability List */
++#define  PCI_STATUS_66MHZ	0x20	/* Support 66 Mhz PCI 2.1 bus */
++#define  PCI_STATUS_UDF		0x40	/* Support User Definable Features [obsolete] */
++#define  PCI_STATUS_FAST_BACK	0x80	/* Accept fast-back to back */
++#define  PCI_STATUS_PARITY	0x100	/* Detected parity error */
++#define  PCI_STATUS_DEVSEL_MASK	0x600	/* DEVSEL timing */
++#define  PCI_STATUS_DEVSEL_FAST	0x000	
++#define  PCI_STATUS_DEVSEL_MEDIUM 0x200
++#define  PCI_STATUS_DEVSEL_SLOW 0x400
++#define  PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
++#define  PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
++#define  PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
++#define  PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
++#define  PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
++
++#define PCI_CLASS_REVISION	0x08	/* High 24 bits are class, low 8
++					   revision */
++#define PCI_REVISION_ID         0x08    /* Revision ID */
++#define PCI_CLASS_PROG          0x09    /* Reg. Level Programming Interface */
++#define PCI_CLASS_DEVICE        0x0a    /* Device class */
++
++#define PCI_CACHE_LINE_SIZE	0x0c	/* 8 bits */
++#define PCI_LATENCY_TIMER	0x0d	/* 8 bits */
++#define PCI_HEADER_TYPE		0x0e	/* 8 bits */
++#define  PCI_HEADER_TYPE_NORMAL	0
++#define  PCI_HEADER_TYPE_BRIDGE 1
++#define  PCI_HEADER_TYPE_CARDBUS 2
++
++#define PCI_BIST		0x0f	/* 8 bits */
++#define PCI_BIST_CODE_MASK	0x0f	/* Return result */
++#define PCI_BIST_START		0x40	/* 1 to start BIST, 2 secs or less */
++#define PCI_BIST_CAPABLE	0x80	/* 1 if BIST capable */
++
++/*
++ * Base addresses specify locations in memory or I/O space.
++ * Decoded size can be determined by writing a value of 
++ * 0xffffffff to the register, and reading it back.  Only 
++ * 1 bits are decoded.
++ */
++#define PCI_BASE_ADDRESS_0	0x10	/* 32 bits */
++#define PCI_BASE_ADDRESS_1	0x14	/* 32 bits [htype 0,1 only] */
++#define PCI_BASE_ADDRESS_2	0x18	/* 32 bits [htype 0 only] */
++#define PCI_BASE_ADDRESS_3	0x1c	/* 32 bits */
++#define PCI_BASE_ADDRESS_4	0x20	/* 32 bits */
++#define PCI_BASE_ADDRESS_5	0x24	/* 32 bits */
++#define  PCI_BASE_ADDRESS_SPACE	0x01	/* 0 = memory, 1 = I/O */
++#define  PCI_BASE_ADDRESS_SPACE_IO 0x01
++#define  PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
++#define  PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
++#define  PCI_BASE_ADDRESS_MEM_TYPE_32	0x00	/* 32 bit address */
++#define  PCI_BASE_ADDRESS_MEM_TYPE_1M	0x02	/* Below 1M [obsolete] */
++#define  PCI_BASE_ADDRESS_MEM_TYPE_64	0x04	/* 64 bit address */
++#define  PCI_BASE_ADDRESS_MEM_PREFETCH	0x08	/* prefetchable? */
++#define  PCI_BASE_ADDRESS_MEM_MASK	(~0x0fUL)
++#define  PCI_BASE_ADDRESS_IO_MASK	(~0x03UL)
++/* bit 1 is reserved if address_space = 1 */
++
++/* Header type 0 (normal devices) */
++#define PCI_CARDBUS_CIS		0x28
++#define PCI_SUBSYSTEM_VENDOR_ID	0x2c
++#define PCI_SUBSYSTEM_ID	0x2e  
++#define PCI_ROM_ADDRESS		0x30	/* Bits 31..11 are address, 10..1 reserved */
++#define  PCI_ROM_ADDRESS_ENABLE	0x01
++#define PCI_ROM_ADDRESS_MASK	(~0x7ffUL)
++
++#define PCI_CAPABILITY_LIST	0x34	/* Offset of first capability list entry */
++
++/* 0x35-0x3b are reserved */
++#define PCI_INTERRUPT_LINE	0x3c	/* 8 bits */
++#define PCI_INTERRUPT_PIN	0x3d	/* 8 bits */
++#define PCI_MIN_GNT		0x3e	/* 8 bits */
++#define PCI_MAX_LAT		0x3f	/* 8 bits */
++
++/* Header type 1 (PCI-to-PCI bridges) */
++#define PCI_PRIMARY_BUS		0x18	/* Primary bus number */
++#define PCI_SECONDARY_BUS	0x19	/* Secondary bus number */
++#define PCI_SUBORDINATE_BUS	0x1a	/* Highest bus number behind the bridge */
++#define PCI_SEC_LATENCY_TIMER	0x1b	/* Latency timer for secondary interface */
++#define PCI_IO_BASE		0x1c	/* I/O range behind the bridge */
++#define PCI_IO_LIMIT		0x1d
++#define  PCI_IO_RANGE_TYPE_MASK	0x0f	/* I/O bridging type */
++#define  PCI_IO_RANGE_TYPE_16	0x00
++#define  PCI_IO_RANGE_TYPE_32	0x01
++#define  PCI_IO_RANGE_MASK	~0x0f
++#define PCI_SEC_STATUS		0x1e	/* Secondary status register, only bit 14 used */
++#define PCI_MEMORY_BASE		0x20	/* Memory range behind */
++#define PCI_MEMORY_LIMIT	0x22
++#define  PCI_MEMORY_RANGE_TYPE_MASK 0x0f
++#define  PCI_MEMORY_RANGE_MASK	~0x0f
++#define PCI_PREF_MEMORY_BASE	0x24	/* Prefetchable memory range behind */
++#define PCI_PREF_MEMORY_LIMIT	0x26
++#define  PCI_PREF_RANGE_TYPE_MASK 0x0f
++#define  PCI_PREF_RANGE_TYPE_32	0x00
++#define  PCI_PREF_RANGE_TYPE_64	0x01
++#define  PCI_PREF_RANGE_MASK	~0x0f
++#define PCI_PREF_BASE_UPPER32	0x28	/* Upper half of prefetchable memory range */
++#define PCI_PREF_LIMIT_UPPER32	0x2c
++#define PCI_IO_BASE_UPPER16	0x30	/* Upper half of I/O addresses */
++#define PCI_IO_LIMIT_UPPER16	0x32
++/* 0x34 same as for htype 0 */
++/* 0x35-0x3b is reserved */
++#define PCI_ROM_ADDRESS1	0x38	/* Same as PCI_ROM_ADDRESS, but for htype 1 */
++/* 0x3c-0x3d are same as for htype 0 */
++#define PCI_BRIDGE_CONTROL	0x3e
++#define  PCI_BRIDGE_CTL_PARITY	0x01	/* Enable parity detection on secondary interface */
++#define  PCI_BRIDGE_CTL_SERR	0x02	/* The same for SERR forwarding */
++#define  PCI_BRIDGE_CTL_NO_ISA	0x04	/* Disable bridging of ISA ports */
++#define  PCI_BRIDGE_CTL_VGA	0x08	/* Forward VGA addresses */
++#define  PCI_BRIDGE_CTL_MASTER_ABORT 0x20  /* Report master aborts */
++#define  PCI_BRIDGE_CTL_BUS_RESET 0x40	/* Secondary bus reset */
++#define  PCI_BRIDGE_CTL_FAST_BACK 0x80	/* Fast Back2Back enabled on secondary interface */
++
++/* Header type 2 (CardBus bridges) */
++/* 0x14-0x15 reserved */
++#define PCI_CB_SEC_STATUS	0x16	/* Secondary status */
++#define PCI_CB_PRIMARY_BUS	0x18	/* PCI bus number */
++#define PCI_CB_CARD_BUS		0x19	/* CardBus bus number */
++#define PCI_CB_SUBORDINATE_BUS	0x1a	/* Subordinate bus number */
++#define PCI_CB_LATENCY_TIMER	0x1b	/* CardBus latency timer */
++#define PCI_CB_MEMORY_BASE_0	0x1c
++#define PCI_CB_MEMORY_LIMIT_0	0x20
++#define PCI_CB_MEMORY_BASE_1	0x24
++#define PCI_CB_MEMORY_LIMIT_1	0x28
++#define PCI_CB_IO_BASE_0	0x2c
++#define PCI_CB_IO_BASE_0_HI	0x2e
++#define PCI_CB_IO_LIMIT_0	0x30
++#define PCI_CB_IO_LIMIT_0_HI	0x32
++#define PCI_CB_IO_BASE_1	0x34
++#define PCI_CB_IO_BASE_1_HI	0x36
++#define PCI_CB_IO_LIMIT_1	0x38
++#define PCI_CB_IO_LIMIT_1_HI	0x3a
++#define  PCI_CB_IO_RANGE_MASK	~0x03
++/* 0x3c-0x3d are same as for htype 0 */
++#define PCI_CB_BRIDGE_CONTROL	0x3e
++#define  PCI_CB_BRIDGE_CTL_PARITY	0x01	/* Similar to standard bridge control register */
++#define  PCI_CB_BRIDGE_CTL_SERR		0x02
++#define  PCI_CB_BRIDGE_CTL_ISA		0x04
++#define  PCI_CB_BRIDGE_CTL_VGA		0x08
++#define  PCI_CB_BRIDGE_CTL_MASTER_ABORT	0x20
++#define  PCI_CB_BRIDGE_CTL_CB_RESET	0x40	/* CardBus reset */
++#define  PCI_CB_BRIDGE_CTL_16BIT_INT	0x80	/* Enable interrupt for 16-bit cards */
++#define  PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100	/* Prefetch enable for both memory regions */
++#define  PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
++#define  PCI_CB_BRIDGE_CTL_POST_WRITES	0x400
++#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
++#define PCI_CB_SUBSYSTEM_ID	0x42
++#define PCI_CB_LEGACY_MODE_BASE	0x44	/* 16-bit PC Card legacy mode base address (ExCa) */
++/* 0x48-0x7f reserved */
++
++/* Capability lists */
++
++#define PCI_CAP_LIST_ID		0	/* Capability ID */
++#define  PCI_CAP_ID_PM		0x01	/* Power Management */
++#define  PCI_CAP_ID_AGP		0x02	/* Accelerated Graphics Port */
++#define  PCI_CAP_ID_VPD		0x03	/* Vital Product Data */
++#define  PCI_CAP_ID_SLOTID	0x04	/* Slot Identification */
++#define  PCI_CAP_ID_MSI		0x05	/* Message Signalled Interrupts */
++#define  PCI_CAP_ID_CHSWP	0x06	/* CompactPCI HotSwap */
++#define PCI_CAP_LIST_NEXT	1	/* Next capability in the list */
++#define PCI_CAP_FLAGS		2	/* Capability defined flags (16 bits) */
++#define PCI_CAP_SIZEOF		4
++
++/* Power Management Registers */
++
++#define  PCI_PM_CAP_VER_MASK	0x0007	/* Version */
++#define  PCI_PM_CAP_PME_CLOCK	0x0008	/* PME clock required */
++#define  PCI_PM_CAP_AUX_POWER	0x0010	/* Auxilliary power support */
++#define  PCI_PM_CAP_DSI		0x0020	/* Device specific initialization */
++#define  PCI_PM_CAP_D1		0x0200	/* D1 power state support */
++#define  PCI_PM_CAP_D2		0x0400	/* D2 power state support */
++#define  PCI_PM_CAP_PME		0x0800	/* PME pin supported */
++#define PCI_PM_CTRL		4	/* PM control and status register */
++#define  PCI_PM_CTRL_STATE_MASK	0x0003	/* Current power state (D0 to D3) */
++#define  PCI_PM_CTRL_PME_ENABLE	0x0100	/* PME pin enable */
++#define  PCI_PM_CTRL_DATA_SEL_MASK	0x1e00	/* Data select (??) */
++#define  PCI_PM_CTRL_DATA_SCALE_MASK	0x6000	/* Data scale (??) */
++#define  PCI_PM_CTRL_PME_STATUS	0x8000	/* PME pin status */
++#define PCI_PM_PPB_EXTENSIONS	6	/* PPB support extensions (??) */
++#define  PCI_PM_PPB_B2_B3	0x40	/* Stop clock when in D3hot (??) */
++#define  PCI_PM_BPCC_ENABLE	0x80	/* Bus power/clock control enable (??) */
++#define PCI_PM_DATA_REGISTER	7	/* (??) */
++#define PCI_PM_SIZEOF		8
++
++/* AGP registers */
++
++#define PCI_AGP_VERSION		2	/* BCD version number */
++#define PCI_AGP_RFU		3	/* Rest of capability flags */
++#define PCI_AGP_STATUS		4	/* Status register */
++#define  PCI_AGP_STATUS_RQ_MASK	0xff000000	/* Maximum number of requests - 1 */
++#define  PCI_AGP_STATUS_SBA	0x0200	/* Sideband addressing supported */
++#define  PCI_AGP_STATUS_64BIT	0x0020	/* 64-bit addressing supported */
++#define  PCI_AGP_STATUS_FW	0x0010	/* FW transfers supported */
++#define  PCI_AGP_STATUS_RATE4	0x0004	/* 4x transfer rate supported */
++#define  PCI_AGP_STATUS_RATE2	0x0002	/* 2x transfer rate supported */
++#define  PCI_AGP_STATUS_RATE1	0x0001	/* 1x transfer rate supported */
++#define PCI_AGP_COMMAND		8	/* Control register */
++#define  PCI_AGP_COMMAND_RQ_MASK 0xff000000  /* Master: Maximum number of requests */
++#define  PCI_AGP_COMMAND_SBA	0x0200	/* Sideband addressing enabled */
++#define  PCI_AGP_COMMAND_AGP	0x0100	/* Allow processing of AGP transactions */
++#define  PCI_AGP_COMMAND_64BIT	0x0020 	/* Allow processing of 64-bit addresses */
++#define  PCI_AGP_COMMAND_FW	0x0010 	/* Force FW transfers */
++#define  PCI_AGP_COMMAND_RATE4	0x0004	/* Use 4x rate */
++#define  PCI_AGP_COMMAND_RATE2	0x0002	/* Use 4x rate */
++#define  PCI_AGP_COMMAND_RATE1	0x0001	/* Use 4x rate */
++#define PCI_AGP_SIZEOF		12
++
++/* Slot Identification */
++
++#define PCI_SID_ESR		2	/* Expansion Slot Register */
++#define  PCI_SID_ESR_NSLOTS	0x1f	/* Number of expansion slots available */
++#define  PCI_SID_ESR_FIC	0x20	/* First In Chassis Flag */
++#define PCI_SID_CHASSIS_NR	3	/* Chassis Number */
++
++/* Message Signalled Interrupts registers */
++
++#define PCI_MSI_FLAGS		2	/* Various flags */
++#define  PCI_MSI_FLAGS_64BIT	0x80	/* 64-bit addresses allowed */
++#define  PCI_MSI_FLAGS_QSIZE	0x70	/* Message queue size configured */
++#define  PCI_MSI_FLAGS_QMASK	0x0e	/* Maximum queue size available */
++#define  PCI_MSI_FLAGS_ENABLE	0x01	/* MSI feature enabled */
++#define PCI_MSI_RFU		3	/* Rest of capability flags */
++#define PCI_MSI_ADDRESS_LO	4	/* Lower 32 bits */
++#define PCI_MSI_ADDRESS_HI	8	/* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
++#define PCI_MSI_DATA_32		8	/* 16 bits of data for 32-bit devices */
++#define PCI_MSI_DATA_64		12	/* 16 bits of data for 64-bit devices */
++
++int pci_find_device(u32 vendor, u32 device);
++int pci_config_write_u8(int fd, int ofs, u8 v);
++int pci_config_write_u16(int fd, int ofs, u16 v);
++int pci_config_write_u32(int fd, int ofs, u32 v);
++int pci_config_read_u8(int fd, int ofs, u8 *v);
++int pci_config_read_u16(int fd, int ofs, u16 *v);
++int pci_config_read_u32(int fd, int ofs, u32 *v);
++u32 pci_read_base_address(u32 vendor, u32 device);
++
++#endif
++
diff --git a/sysutils/sjog/files/patch-src::pci_freebsd.c b/sysutils/sjog/files/patch-src::pci_freebsd.c
new file mode 100644
index 000000000000..227c211b16e5
--- /dev/null
+++ b/sysutils/sjog/files/patch-src::pci_freebsd.c
@@ -0,0 +1,153 @@
+--- src/pci_freebsd.c.orig	Sat Aug 17 20:38:56 2002
++++ src/pci_freebsd.c	Sat Aug 17 20:38:56 2002
+@@ -0,0 +1,150 @@
++/* manipulate PCI devices from user space
++
++   Tridge, July 2000
++
++   FreeBSD modifications for sjog by Jay Kuri jk@oneway.com 08/13/01 
++*/
++/* 
++   Copyright (C) Andrew Tridgell 2000
++   Copyright (C) Takanori Watanabe 2000
++   
++   This program is free software; you can redistribute it and/or modify
++   it under the terms of the GNU General Public License as published by
++   the Free Software Foundation; either version 2 of the License, or
++   (at your option) any later version.
++   
++   This program is distributed in the hope that it will be useful,
++   but WITHOUT ANY WARRANTY; without even the implied warranty of
++   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++   GNU General Public License for more details.
++   
++   You should have received a copy of the GNU General Public License
++   along with this program; if not, write to the Free Software
++   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*/
++#include <sys/types.h>
++#include <sys/pciio.h>
++#include <sys/fcntl.h>
++#include "sonypi.h"
++#define MAX_BUS 8
++
++#define PCI_GETCONF_MATCH_VENDDEV (PCI_GETCONF_MATCH_VENDOR|PCI_GETCONF_MATCH_DEVICE)
++#define MAXHANDLE 32
++
++static struct pci_io pio[MAXHANDLE];
++static u_int32_t handlebmp=0;
++static int pci_fd=-1;
++static int pcifd_internal_init();
++int pcifd_internal_init()
++{
++  return pci_fd=open("/dev/pci",O_RDWR,0);
++}
++/* find a PCI device and return a handle to it */
++int pci_find_device(u32 vendor, u32 device)
++{
++  
++  struct pci_conf pc[4];/*I think only one is enough*/
++  struct pci_conf_io pcfi;
++  struct pci_match_conf pmc={{0,0,0},"",0,0xffff,0xffff,0,
++			       PCI_GETCONF_MATCH_VENDDEV};
++  int handle;
++  if(pci_fd==-1){
++    if(pcifd_internal_init()==-1)
++      return -1;
++  }
++  pmc.pc_vendor=vendor;
++  pmc.pc_device=device;
++  pcfi.pat_buf_len=sizeof(pmc);
++  pcfi.num_patterns=1;
++  pcfi.patterns=&pmc;
++  pcfi.match_buf_len=sizeof(pc);
++  pcfi.num_matches=0;
++  pcfi.matches=pc;
++  pcfi.offset=0;
++  pcfi.generation=0;
++  ioctl(pci_fd,PCIOCGETCONF,&pcfi);
++  if(pcfi.num_matches==0){
++    goto error;
++  }
++  for(handle=0;handle<32;handle++){
++    if(!(handlebmp&(1<<handle))){
++      pio[handle].pi_sel=pc[0].pc_sel;
++      handlebmp|=(1<<handle);
++      return handle;
++    }
++  }
++ error:
++  close(pci_fd);
++  return -1;
++}
++
++
++/* routines to read and write PCI config space */
++#define PCICFGWACCESSOR(bsize) \
++int pci_config_write_u##bsize(int fd, int ofs, u##bsize v)\
++{\
++  int result;\
++  if(fd==-1){\
++    return -1;\
++  }\
++  if(pci_fd==-1){\
++    if(pcifd_internal_init()==-1)\
++       return -1;\
++  }\
++  pio[fd].pi_reg=ofs;\
++  pio[fd].pi_width=bsize/8;\
++  pio[fd].pi_data=v;\
++  result=ioctl(pci_fd,PCIOCWRITE,&pio[fd]);\
++  return result;\
++}
++PCICFGWACCESSOR(8)
++PCICFGWACCESSOR(16)
++PCICFGWACCESSOR(32)
++#undef PCICFGWACCESSOR
++/*Acctually define 
++  pci_config_write_u8();
++  pci_config_write_u16();
++  pci_config_write_u32();
++*/
++#define PCICFGRACCESSOR(bsize) \
++int pci_config_read_u##bsize(int fd, int ofs, u##bsize *v)\
++{\
++  int result;\
++  if(fd==-1){\
++    return -1;\
++  }\
++  if(pci_fd==-1){\
++    if(pcifd_internal_init()==-1)\
++       return -1;\
++  }\
++  pio[fd].pi_reg=ofs;\
++  pio[fd].pi_width=bsize/8;\
++  result=ioctl(pci_fd,PCIOCREAD,&pio[fd]);\
++  *v=pio[fd].pi_data&((bsize==32)? 0xffffffff: (1<<bsize)-1);\
++  return result;\
++}
++/*Acctually define 
++  pci_config_read_u8();
++  pci_config_read_u16();
++  pci_config_read_u32();
++*/
++PCICFGRACCESSOR(8) 
++PCICFGRACCESSOR(16) 
++PCICFGRACCESSOR(32) 
++#undef PCICFGRACCESSOR
++
++/* find a pci base address via /proc/bus/pci/devices. This seems to be
++   needed on some boxes. Why? */
++u_int32_t pci_read_base_address(u32 vendor, u32 device)
++{
++  return 0;/* In FreeBSD???*/
++}
++
++
++
++
++
++
++
++
++
diff --git a/sysutils/sjog/files/patch-src::sjog.c b/sysutils/sjog/files/patch-src::sjog.c
new file mode 100644
index 000000000000..a7bdab473f2e
--- /dev/null
+++ b/sysutils/sjog/files/patch-src::sjog.c
@@ -0,0 +1,14 @@
+--- src/sjog.c.orig	Mon Aug 13 20:52:02 2001
++++ src/sjog.c	Sat Aug 17 20:38:56 2002
+@@ -10,7 +10,11 @@
+ /* -------------------------------------------------------------------------- */
+ 
+ gboolean reverseBrightness = TRUE;
++#ifdef __FreeBSD__
++gboolean useSpic = TRUE;
++#else 
+ gboolean useSpic = FALSE;
++#endif
+ gboolean mousewheelFakeKeys = FALSE;
+ gboolean centerWindow = TRUE;
+ 
diff --git a/sysutils/sjog/files/patch-src::sjog_spic.c b/sysutils/sjog/files/patch-src::sjog_spic.c
new file mode 100644
index 000000000000..5fdd5f301dc5
--- /dev/null
+++ b/sysutils/sjog/files/patch-src::sjog_spic.c
@@ -0,0 +1,45 @@
+--- src/sjog_spic.c.orig	Mon Aug  6 13:38:14 2001
++++ src/sjog_spic.c	Sat Aug 17 20:38:56 2002
+@@ -1,9 +1,17 @@
++/* FreeBSD modifications by Jay Kuri jk@oneway.com 08/13/01 */
++
+ #include "sjog_spic.h"
++#ifdef __FreeBSD__
++#include "sonypi.h"
++#endif
+ 
+ void
+ sjog_spic_init()
+ {
+ 
++#ifdef __FreeBSD__
++   spic_init();
++#else
+    /* open spic device */
+    if ((spic_fd = open(SPIC_DEVICE, O_RDONLY)) < 0)
+    {
+@@ -11,6 +19,7 @@
+               SPIC_DEVICE);
+       exit(1);
+    }
++#endif
+ 
+ }
+ 
+@@ -24,12 +33,16 @@
+    fprintf(stdout, "sjog_spic_read_jog: spic_fd=%d\n", spic_fd);
+ #endif
+ 
++#ifdef __FreeBSD__
++      jog = spic_jogger_turned();
++#else
+    if (read(spic_fd, (gchar *) & jog, sizeof(gint)) < 0)
+    {
+       fprintf(stderr, "%s read error!\n", SPIC_DEVICE);
+       close(spic_fd);
+       exit(1);
+    }
++#endif
+ 
+    sjog_jog_position_changed(jog);
+ 
diff --git a/sysutils/sjog/files/patch-src::sjog_volume.c b/sysutils/sjog/files/patch-src::sjog_volume.c
new file mode 100644
index 000000000000..41bd4dfc9346
--- /dev/null
+++ b/sysutils/sjog/files/patch-src::sjog_volume.c
@@ -0,0 +1,12 @@
+--- src/sjog_volume.c.orig	Sun Aug 12 23:17:33 2001
++++ src/sjog_volume.c	Sat Aug 17 20:38:56 2002
+@@ -1,5 +1,9 @@
+ #include <sys/ioctl.h>
++#ifdef __FreeBSD__
++#include <machine/soundcard.h>
++#else
+ #include <linux/soundcard.h>
++#endif
+ 
+ #include "sjog.h"
+ #include "sjog_volume.h"
diff --git a/sysutils/sjog/files/patch-src::sonypi.c b/sysutils/sjog/files/patch-src::sonypi.c
new file mode 100644
index 000000000000..d8093dac544a
--- /dev/null
+++ b/sysutils/sjog/files/patch-src::sonypi.c
@@ -0,0 +1,434 @@
+--- src/sonypi.c.orig	Sat Aug 17 20:38:56 2002
++++ src/sonypi.c	Sat Aug 17 20:38:56 2002
+@@ -0,0 +1,431 @@
++/* sony programmable I/O control device (SPIC) functions for picturebook 
++
++   Tridge and sfr, July 2000
++
++   FreeBSD modifications by Jay Kuri jk@oneway.com 08/13/01 
++*/
++/* 
++   Copyright (C) Andrew Tridgell 2000
++   
++   This program is free software; you can redistribute it and/or modify
++   it under the terms of the GNU General Public License as published by
++   the Free Software Foundation; either version 2 of the License, or
++   (at your option) any later version.
++   
++   This program is distributed in the hope that it will be useful,
++   but WITHOUT ANY WARRANTY; without even the implied warranty of
++   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++   GNU General Public License for more details.
++   
++   You should have received a copy of the GNU General Public License
++   along with this program; if not, write to the Free Software
++   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*/
++
++
++#include "sonypi.h"
++#include "pci.h"
++
++static int spic_fd;
++static int debug=0;
++#ifdef LINUX
++static void OUTB(u8 v, int port)
++{
++	outb(v, port);
++}
++
++static u8 INB(int port)
++{
++	usleep(10);
++	return inb(port);
++}
++#define OUTW outw
++#else ifdef __FreeBSD__
++#include <machine/cpufunc.h>
++void OUTB(u8 v, unsigned int port)
++{
++	outb(port,v);
++}
++void OUTW(u16 v, unsigned int port)
++{
++	outw(port,v);
++}
++
++static u8 INB(unsigned int port)
++{
++	usleep(10);
++	return inb(port);
++}
++static int deviofd=-1;
++int iopl(int lvl)
++{
++  if(lvl==0){
++    if(deviofd!=-1){
++      close(deviofd);
++      deviofd=-1;
++    }    
++    return 0;
++  }else if(lvl==3){
++    if(deviofd==-1){
++      deviofd=open("/dev/io",0);
++    }
++    return deviofd;
++  }
++  return -1;
++}
++
++#endif
++/* initialise the SPIC - this comes from the AML code in the ACPI bios */
++static void spic_srs(int fd, u16 port1, u16 port2, u8 irq)
++{
++	u8 v;
++	u16 v2;
++
++	pci_config_write_u16(fd, SPI_G10A, port1);
++	pci_config_read_u8(fd, SPI_G10L, &v);
++	v = (v & 0xF0) | (port1 ^ port2);
++	pci_config_write_u8(fd, SPI_G10L, v);
++
++	v2 = inw(SPI_IRQ_PORT);
++	v2 &= ~(0x3 << SPI_IRQ_SHIFT);
++	v2 |= (irq << SPI_IRQ_SHIFT);
++	OUTW(v2, SPI_IRQ_PORT);
++
++	pci_config_read_u8(fd, SPI_G10L, &v);
++	v = (v & 0x1F) | 0xC0;
++	pci_config_write_u8(fd, SPI_G10L, v);
++}
++
++/* disable the SPIC - this comes from the AML code in the ACPI bios */
++static void spic_dis(void)
++{
++	u8 v1;
++	u16 v;
++
++	pci_config_read_u8(spic_fd, SPI_G10L, &v1);
++	pci_config_write_u8(spic_fd, SPI_G10L, v1 & 0x3F);
++
++	v = inw(SPI_IRQ_PORT);
++	v |= (0x3 << SPI_IRQ_SHIFT);
++	OUTW(v, SPI_IRQ_PORT);
++	close(spic_fd);
++}
++
++
++static void spic_settle(void)
++{
++	while (INB(SPIC_PORT2) & 2) usleep(1);
++}
++
++static u8 spic_call1(u8 dev)
++{
++	u8 v1, v2;
++	spic_settle();
++
++	OUTB(dev, SPIC_PORT2);
++	v1 = INB(SPIC_PORT2);
++	v2 = INB(SPIC_PORT1);
++	if (debug)
++		printf("spic call1(%x) -> %x %x\n", dev, v1, v2);
++	return v2;
++}
++
++static u8 spic_call2(u8 dev, u8 fn)
++{
++	u8 v1;
++
++	while (INB(SPIC_PORT2) & 2) ;
++	OUTB(dev, SPIC_PORT2);
++
++	while (INB(SPIC_PORT2) & 2) ;
++	OUTB(fn, SPIC_PORT1);
++
++	v1 = INB(SPIC_PORT1);
++	if (debug)
++		printf("spic call2(%x, %x) -> %x\n", dev, fn, v1);
++	return v1;
++}
++
++static u8 spic_call3(u8 dev, u8 fn, u8 v)
++{
++	u8 v1;
++
++	while (INB(SPIC_PORT2) & 2) ;
++	OUTB(dev, SPIC_PORT2);
++
++	while (INB(SPIC_PORT2) & 2) ;
++	OUTB(fn, SPIC_PORT1);
++
++	while (INB(SPIC_PORT2) & 2) ;
++	OUTB(v, SPIC_PORT1);
++
++	v1 = INB(SPIC_PORT1);
++	if (debug)
++		printf("call3(%x, %x, %x) -> %x\n", dev, fn, v, v1);
++	return v1;
++}
++
++static u8 spic_read(u8 fn)
++{
++	u8 v1, v2;
++	int n = 100;
++	while (n--) {
++		v1 = spic_call2(0x8f, fn);
++		v2 = spic_call2(0x8f, fn);
++		if (v1 == v2 && v1 != 0xff) {
++			return v1;
++		}
++	}
++	return 0xff;
++}
++
++/* set brightness, hue etc */
++static void spic_set(u8 fn, u8 v)
++{
++	int n = 100;
++	while (n--) {
++		if (spic_call3(0x90, fn, v) == 0) break;
++	}
++}
++
++static int spic_camera_ready(void)
++{
++	u8 v = spic_call2(0x8f, SPIC_CAMERA_STATUS);
++	return (v != 0xff && (v & SPIC_CAMERA_STATUS_READY));
++}
++
++/* turn the camera off */
++void spic_camera_off(void)
++{
++	spic_call2(0x91, 0);
++}
++
++/* turn the camera on */
++void spic_camera_on(void)
++{
++	int i;
++
++	while (spic_call2(0x91, 0x1) != 0) usleep(1);
++	spic_call1(0x93);
++
++	if (!spic_camera_ready()) {
++		printf("waiting for camera ready\n");
++		for (i=400;i>0;i--) {
++			if (spic_camera_ready()) break;
++			usleep(100);
++		}
++		if (i == 0) {
++			printf("failed to power on camera\n");
++			return;
++		}
++	}
++
++	spic_set(0x10, 0x5a);
++}
++
++/* return 0 if capture not pressed, return 1 if pressed to partial,
++   return 2 if fully pressed */
++int spic_capture_pressed(void)
++{
++	u8 v1, v2;
++	v1 = inb(SPIC_PORT1);
++	v2 = inb(SPIC_PORT2);
++	if (v2 != 0x60) return 0;
++	if (v1 == SPIC_EVENT_CAPTURE_PARTIAL) return 1;
++	if (v1 == SPIC_EVENT_CAPTURE_FULL) return 2;
++	return 0;
++}
++
++int spic_jogger_pressed(void)
++{
++	u8 v1, v2;
++	v1 = inb(SPIC_PORT1);
++	v2 = inb(SPIC_PORT2);
++	return (v1 == 0x40 && v2 == 0x10);
++}
++
++int spic_jogger_turned(void)
++{
++	u8 v1, v2;
++	v1 = inb(SPIC_PORT1);
++	v2 = inb(SPIC_PORT2);
++	if ((v2 & 0x10) == 0 || v1 == 0) return 0;
++	/* the following clears the evnet bits */
++	spic_call2(0x81, 0xff);
++	return (signed char)v1;
++}
++
++int spic_jogger(void)
++{
++	u8 v1, v2, ov1=0, ov2=1;
++	while (1) {
++		v1 = INB(SPIC_PORT1);
++		v2 = INB(SPIC_PORT2);
++		if (v1 != ov1 || v2 != ov2) {
++			printf("event 0x%02x 0x%02x\n", v1, v2);
++		}
++		ov1 = v1;
++		ov2 = v2;
++	}
++}
++
++void spic_settings(int brightness, int contrast, int hue, int color, int sharpness, int picture, int agc)
++{
++	spic_set(SPIC_CAMERA_BRIGHTNESS, brightness);
++	spic_set(SPIC_CAMERA_CONTRAST, contrast);
++	spic_set(SPIC_CAMERA_HUE, hue);
++	spic_set(SPIC_CAMERA_COLOR, color);
++	spic_set(SPIC_CAMERA_SHARPNESS, sharpness);
++	spic_set(SPIC_CAMERA_PICTURE, picture);
++	spic_set(SPIC_CAMERA_AGC, agc);
++}
++
++void spic_setup_vga(void)
++{
++/* :about to start capture again
 */
++OUTB(0x09, 0x03CE); usleep(10);
++inb(0x03CF); usleep(10); /* -> 00000026 */
++OUTW(0x2609, 0x03CE); usleep(10);
++OUTB(0x0A, 0x03CE); usleep(10);
++inb(0x03CF); usleep(10); /* -> 00000021 */
++OUTW(0x210A, 0x03CE); usleep(10);
++OUTB(0x08, 0x03C4); usleep(10);
++inb(0x03C5); usleep(10); /* -> 00000020 */
++OUTB(0x09, 0x03C4); usleep(10);
++inb(0x03C5); usleep(10); /* -> 000000F3 */
++OUTW(0x2008, 0x03C4); usleep(10);
++OUTW(0xF309, 0x03C4); usleep(10);
++OUTW(0x2609, 0x03CE); usleep(10);
++OUTW(0x210A, 0x03CE); usleep(10);
++OUTB(0x09, 0x03CE); usleep(10);
++inb(0x03CF); usleep(10); /* -> 00000026 */
++OUTW(0x2609, 0x03CE); usleep(10);
++OUTB(0x0A, 0x03CE); usleep(10);
++inb(0x03CF); usleep(10); /* -> 00000021 */
++OUTW(0x210A, 0x03CE); usleep(10);
++OUTB(0x08, 0x03C4); usleep(10);
++inb(0x03C5); usleep(10); /* -> 00000020 */
++OUTB(0x09, 0x03C4); usleep(10);
++inb(0x03C5); usleep(10); /* -> 000000F3 */
++OUTW(0xF109, 0x03C4); usleep(10);
++OUTW(0x2609, 0x03CE); usleep(10);
++OUTW(0x210A, 0x03CE); usleep(10);
++OUTB(0x09, 0x03CE); usleep(10);
++inb(0x03CF); usleep(10); /* -> 00000026 */
++OUTW(0x2609, 0x03CE); usleep(10);
++OUTB(0x0A, 0x03CE); usleep(10);
++inb(0x03CF); usleep(10); /* -> 00000021 */
++OUTW(0x210A, 0x03CE); usleep(10);
++OUTB(0x08, 0x03C4); usleep(10);
++inb(0x03C5); usleep(10); /* -> 00000020 */
++OUTB(0x09, 0x03C4); usleep(10);
++inb(0x03C5); usleep(10); /* -> 0000001F */
++OUTW(0x1D09, 0x03C4); usleep(10);
++OUTW(0x2609, 0x03CE); usleep(10);
++OUTW(0x210A, 0x03CE); usleep(10);
++OUTB(0x08, 0x03C4); usleep(10);
++inb(0x03C5); usleep(10); /* -> 00002621 */
++OUTB(0x09, 0x03C4); usleep(10);
++inb(0x03C5); usleep(10); /* -> 000026E9 */
++OUTB(0x08, 0x03C4); usleep(10);
++inb(0x03C5); usleep(10); /* -> 00002621 */
++OUTB(0x09, 0x03C4); usleep(10);
++inb(0x03C5); usleep(10); /* -> 000026F9 */
++OUTB(0x09, 0x03CE); usleep(10);
++inb(0x03CF); usleep(10); /* -> 00000026 */
++OUTB(0x09, 0x03CE); usleep(10);
++OUTB(0x26, 0x03CF); usleep(10);
++OUTB(0x0A, 0x03CE); usleep(10);
++inb(0x03CF); usleep(10); /* -> 00000021 */
++OUTB(0x0A, 0x03CE); usleep(10);
++OUTB(0x21, 0x03CF); usleep(10);
++OUTB(0x0F, 0x03C4); usleep(10);
++inb(0x03C5); usleep(10); /* -> 00000001 */
++OUTB(0x0F, 0x03C4); usleep(10);
++OUTB(0x01, 0x03C5); usleep(10);
++OUTB(0x0F, 0x03C4); usleep(10);
++inb(0x03C5); usleep(10); /* -> 00000001 */
++OUTB(0x0A, 0x03CE); usleep(10);
++OUTB(0x21, 0x03CF); usleep(10);
++OUTB(0x09, 0x03CE); usleep(10);
++OUTB(0x26, 0x03CF); usleep(10);
++OUTB(0x09, 0x03CE); usleep(10);
++inb(0x03CF); usleep(10); /* -> 00000026 */
++OUTW(0x2609, 0x03CE); usleep(10);
++OUTB(0xBF, 0x03CE); usleep(10);
++inb(0x03CF); usleep(10); /* -> 00000000 */
++OUTB(0xA3, 0x03CE); usleep(10);
++inb(0x03CF); usleep(10); /* -> 0000000C */
++OUTW(0xBF, 0x03CE); usleep(10);
++OUTW(0x0CA3, 0x03CE); usleep(10);
++OUTB(0x09, 0x03CE); usleep(10);
++inb(0x03CF); usleep(10); /* -> 00000026 */
++OUTW(0x2609, 0x03CE); usleep(10);
++OUTB(0x0A, 0x03CE); usleep(10);
++inb(0x03CF); usleep(10); /* -> 00000021 */
++OUTW(0x210A, 0x03CE); usleep(10);
++OUTB(0x08, 0x03C4); usleep(10);
++inb(0x03C5); usleep(10); /* -> 00000021 */
++OUTB(0x09, 0x03C4); usleep(10);
++inb(0x03C5); usleep(10); /* -> 000000F9 */
++OUTW(0x2609, 0x03CE); usleep(10);
++OUTW(0x210A, 0x03CE); usleep(10);
++OUTB(0x08, 0x03C4); usleep(10);
++inb(0x03C5); usleep(10); /* -> 00002621 */
++OUTB(0x09, 0x03C4); usleep(10);
++inb(0x03C5); usleep(10); /* -> 000026F9 */
++}
++
++void spic_show_settings(void)
++{
++	printf("Brightness %d  ", spic_read(SPIC_CAMERA_BRIGHTNESS));
++	printf("Color %d  ", spic_read(SPIC_CAMERA_COLOR));
++	printf("Contrast %d  ", spic_read(SPIC_CAMERA_CONTRAST));
++	printf("Hue %d  ", spic_read(SPIC_CAMERA_HUE));
++	printf("Sharpness %d\n", spic_read(SPIC_CAMERA_SHARPNESS));
++	printf("Picture 0x%02x  ", spic_read(SPIC_CAMERA_PICTURE));
++	printf("AGC 0x%02x  ", spic_read(SPIC_CAMERA_AGC));
++	printf("Direction: %s\n", (spic_read(SPIC_CAMERA_STATUS) & SPIC_DIRECTION_BACKWARDS) ? "back":"front");
++	printf("RomVersion: %d  ", spic_read(SPIC_CAMERA_ROMVERSION));
++	printf("Revision: %d\n", spic_read(SPIC_CAMERA_REVISION));
++}
++
++void spic_init(void)
++{
++	spic_fd = pci_find_device(SPIC_PCI_VENDOR, SPIC_PCI_DEVICE);
++	if (spic_fd == -1) {
++		printf("can't find spic PCI device\n");
++		exit(1);
++	}
++
++	iopl(3);
++	spic_srs(spic_fd, SPIC_PORT1, SPIC_PORT2, 0x3);
++
++	spic_call1(0x82);
++	spic_call2(0x81, 0xff);
++	spic_call1(0x92);
++
++//	printf("spic enabled\n");
++}
++
++void sdelay(u32 usecs)
++{
++	INB(SPIC_PORT1);
++	INB(SPIC_PORT2);
++	usleep(usecs);
++}
++
++void spic_shutdown(int power_off)
++{
++	spic_set(SPIC_CAMERA_PICTURE, SPIC_CAMERA_MUTE_MASK);
++	spic_call2(0x81, 0); /* make sure we don't get any more events */
++	if (power_off) {
++		spic_camera_off();
++		printf("camera off\n");
++	}
++	spic_dis();
++}
++
++
++
++
diff --git a/sysutils/sjog/files/patch-src::sonypi.h b/sysutils/sjog/files/patch-src::sonypi.h
new file mode 100644
index 000000000000..76104f825fed
--- /dev/null
+++ b/sysutils/sjog/files/patch-src::sonypi.h
@@ -0,0 +1,87 @@
+--- src/sonypi.h.orig	Sat Aug 17 20:38:56 2002
++++ src/sonypi.h	Sat Aug 17 20:38:56 2002
+@@ -0,0 +1,84 @@
++#include <stdio.h>
++#include <stdlib.h>
++#include <unistd.h>
++#include <fcntl.h>
++#include <errno.h>
++#include <sys/mman.h>
++#include <dirent.h>
++#include <ctype.h>
++#include <string.h>
++#include <signal.h>
++#include <sys/pciio.h>
++#define O_SYNC O_FSYNC
++#include <sys/stat.h>
++#include <sys/time.h>
++
++typedef unsigned char u8;
++typedef unsigned short u16;
++typedef unsigned u32;
++
++#define PAGE_SIZE 0x1000
++
++#define SONYPI_DEV "/proc/bus/pci/00/07.3"
++
++#define SPIC_PCI_VENDOR 0x8086
++#define SPIC_PCI_DEVICE 0x7113
++
++/* the irq selection is 2 bits in the following port */
++#define SPI_IRQ_PORT 0x8034
++#define SPI_IRQ_SHIFT 22
++
++#define SPI_BASE 0x50
++
++#define SPI_G10A (SPI_BASE+0x14)
++#define SPI_G10L (SPI_BASE+0x16) /* 4 bits at this offset - the port offset of
++				    2nd port from first */
++#define SPIC_PORT1 0x10a0
++#define SPIC_PORT2 0x10a4
++
++#define SPIC_CAMERA_BRIGHTNESS 0
++#define SPIC_CAMERA_CONTRAST 1
++#define SPIC_CAMERA_HUE 2
++#define SPIC_CAMERA_COLOR 3
++#define SPIC_CAMERA_SHARPNESS 4
++
++#define SPIC_CAMERA_PICTURE 5
++#define SPIC_CAMERA_EXPOSURE_MASK 0xC
++#define SPIC_CAMERA_WHITE_BALANCE_MASK 0x3
++#define SPIC_CAMERA_PICTURE_MODE_MASK 0x30
++#define SPIC_CAMERA_MUTE_MASK 0x40
++
++/* the rest don't need a loop until not 0xff */
++#define SPIC_CAMERA_AGC 6
++#define SPIC_CAMERA_AGC_MASK 0x30
++#define SPIC_CAMERA_SHUTTER_MASK 0x7
++
++#define SPIC_CAMERA_SHUTDOWN_REQUEST 7
++#define SPIC_CAMERA_CONTROL 0x10
++
++#define SPIC_CAMERA_STATUS 7
++#define SPIC_CAMERA_STATUS_READY 0x2
++#define SPIC_CAMERA_STATUS_POSITION 0x4
++
++#define SPIC_DIRECTION_BACKWARDS 0x4
++
++#define SPIC_CAMERA_REVISION 8
++#define SPIC_CAMERA_ROMVERSION 9
++
++
++#define SPIC_EVENT_CAPTURE_BUTTON 0x20
++#define SPIC_EVENT_CAPTURE_PARTIAL 0x05
++#define SPIC_EVENT_CAPTURE_FULL 0x07
++
++#define JOGGER_V1 0x1
++#define JOGGER_V2 0x19
++
++#define BRIGHTNESS_V1 0x15
++#define BRIGHTNESS_V2 0x29
++
++#define VOLUME_V1 0x14
++#define VOLUME_V2 0x29
++
++#define MUTE_V1 0x13
++#define MUTE_V2 0x29
++
diff --git a/sysutils/sjog/pkg-comment b/sysutils/sjog/pkg-comment
new file mode 100644
index 000000000000..aacbe685e710
--- /dev/null
+++ b/sysutils/sjog/pkg-comment
@@ -0,0 +1 @@
+Userland daemon for Sony Vaio Jog Dial
diff --git a/sysutils/sjog/pkg-descr b/sysutils/sjog/pkg-descr
new file mode 100644
index 000000000000..aaa5d0766a35
--- /dev/null
+++ b/sysutils/sjog/pkg-descr
@@ -0,0 +1,17 @@
+From the website:
+
+S-Jog is a program that uses the Sony Vaio laptop's Jog Wheel to do
+various things:
+
+    * Launch applications
+    * Adjust screen brightness
+    * Adjust volume
+    * Act like a mousewheel
+
+S-Jog pops up when you click the Jog Wheel then disappears after 3 seconds
+of idle time. The mousewheel feature is turned on when S-Jog is hidden.
+
+WWW: http://sjog.sourceforge.net/
+
+Bruce
+bms@spc.org
diff --git a/sysutils/sjog/pkg-plist b/sysutils/sjog/pkg-plist
new file mode 100644
index 000000000000..a77380a8036d
--- /dev/null
+++ b/sysutils/sjog/pkg-plist
@@ -0,0 +1,7 @@
+bin/sjog
+bin/setbrightness
+etc/sjogrc
+share/sjog/pixmaps/sjog-brightness.xpm
+share/sjog/pixmaps/sjog-volume.xpm
+@dirrm share/sjog/pixmaps
+@dirrm share/sjog