Add support for Intel Atom/Core/Core2 processors

Install tests to DATADIR/{ctests,ftests} instead of PREFIX/{ctests,ftests}

PR:		ports/136757
Submitted by:	Harald Servat <redcrash@gmail.com>
Approved by:	wxs (mentor)

15 files changed, 2129 insertions, 93 deletions

diff --git a/devel/papi/Makefile b/devel/papi/Makefile
index 68d06e5f4c18..820951baa737 100644
--- a/devel/papi/Makefile
+++ b/devel/papi/Makefile
@@ -7,6 +7,7 @@
 
 PORTNAME=	papi
 PORTVERSION=	3.6.2
+PORTREVISION=	1
 CATEGORIES=	devel
 MASTER_SITES=	http://icl.cs.utk.edu/projects/papi/downloads/
 
@@ -261,15 +262,15 @@ do-install:
 	${INSTALL_DATA} ${WRKSRC}/${f} ${PREFIX}/include
 .endfor
 .if defined(WITH_FTESTS)
-	${MKDIR} ${PREFIX}/share/ftests
+	${MKDIR} ${DATADIR}/ftests
 .for f in ${PAPI_FORTRAN_TESTS}
-	${INSTALL_PROGRAM} ${WRKSRC}/ftests/${f} ${PREFIX}/share/ftests
+	${INSTALL_PROGRAM} ${WRKSRC}/ftests/${f} ${DATADIR}/ftests
 .endfor
 .endif
 .if defined(WITH_CTESTS)
-	${MKDIR} ${PREFIX}/share/ctests
+	${MKDIR} ${DATADIR}/ctests
 .for f in ${PAPI_C_TESTS}
-	${INSTALL_PROGRAM} ${WRKSRC}/ctests/${f} ${PREFIX}/share/ctests
+	${INSTALL_PROGRAM} ${WRKSRC}/ctests/${f} ${DATADIR}/ctests
 .endfor
 .endif
 .for f in ${PAPI_LIBS}
diff --git a/devel/papi/files/patch-Makefile.freebsd b/devel/papi/files/patch-Makefile.freebsd
new file mode 100644
index 000000000000..5924576f1608
--- /dev/null
+++ b/devel/papi/files/patch-Makefile.freebsd
@@ -0,0 +1,40 @@
+--- ./Makefile.freebsd.orig	2008-04-26 04:19:38.000000000 -0400
++++ ./Makefile.freebsd	2009-07-15 12:05:10.589724000 -0400
+@@ -8,6 +8,7 @@
+ POST_BUILD  =
+ SPECIAL_REMOVE =
+ 
++#DEBUGFLAGS  = -DDEBUG
+ 
+ CC_R        = $(CC) -pthread
+ CC_SHR      = $(CC) $(SHRFLAGS) -shared -Xlinker "-soname" -Xlinker "libpapi.so" -Xlinker "-rpath" -Xlinker "$(LIBDIR)" -DPIC -fPIC -I. -Ifreebsd
+@@ -16,8 +17,8 @@
+ 
+ CPU	      = 
+ 
+-MISCHDRS = freebsd/map-unknown.h freebsd/map.h freebsd/map-p6.h freebsd/map-p6-m.h freebsd/map-p6-3.h freebsd/map-p6-2.h freebsd/map-p6-c.h freebsd/map-k7.h freebsd/map-k8.h freebsd/map-p4.h
+-MISCSRCS = freebsd/map-unknown.c freebsd/map.c freebsd/map-p6.c freebsd/map-p6-m.c freebsd/map-p6-3.c freebsd/map-p6-2.c freebsd/map-p6-c.c freebsd/map-k7.c freebsd/map-k8.c freebsd/map-p4.c
++MISCHDRS = freebsd/map-unknown.h freebsd/map.h freebsd/map-p6.h freebsd/map-p6-m.h freebsd/map-p6-3.h freebsd/map-p6-2.h freebsd/map-p6-c.h freebsd/map-k7.h freebsd/map-k8.h freebsd/map-p4.h freebsd/map-atom.h freebsd/map-core.h freebsd/map-core2.h freebsd/map-core2-extreme.h
++MISCSRCS = freebsd/map-unknown.c freebsd/map.c freebsd/map-p6.c freebsd/map-p6-m.c freebsd/map-p6-3.c freebsd/map-p6-2.c freebsd/map-p6-c.c freebsd/map-k7.c freebsd/map-k8.c freebsd/map-p4.c freebsd/map-atom.c freebsd/map-core.c freebsd/map-core2.c freebsd/map-core2-extreme.c
+ MISCOBJS = $(MISCSRCS:.c=.o)
+ SHLIBDEPS =
+ 
+@@ -53,6 +54,18 @@
+ freebsd/map-p4.o: freebsd/map-p4.c $(HEADERS)
+ 	$(CC) $(LIBCFLAGS) -c $< -o $@
+ 
++freebsd/map-atom.o: freebsd/map-atom.c $(HEADERS)
++	$(CC) $(LIBCFLAGS) -c $< -o $@
++
++freebsd/map-core.o: freebsd/map-core.c $(HEADERS)
++	$(CC) $(LIBCFLAGS) -c $< -o $@
++
++freebsd/map-core2.o: freebsd/map-core2.c $(HEADERS)
++	$(CC) $(LIBCFLAGS) -c $< -o $@
++
++freebsd/map-core2-extreme.o: freebsd/map-core2-extreme.c $(HEADERS)
++	$(CC) $(LIBCFLAGS) -c $< -o $@
++
+ freebsd.o: freebsd.c $(HEADERS)
+ 	$(CC) $(LIBCFLAGS) -c $< -o $@
+ 
diff --git a/devel/papi/files/patch-freebsd.c b/devel/papi/files/patch-freebsd.c
index 8f7af39891a4..8de6bdd3409d 100644
--- a/devel/papi/files/patch-freebsd.c
+++ b/devel/papi/files/patch-freebsd.c
@@ -1,6 +1,39 @@
---- freebsd.c	2008-04-26 10:19:38.000000000 +0200
-+++ freebsd.new.c	2009-03-21 18:54:19.000000000 +0100
-@@ -174,8 +174,6 @@
+--- ./freebsd.c.orig	2008-04-26 04:19:38.000000000 -0400
++++ ./freebsd.c	2009-07-15 12:05:10.789747000 -0400
+@@ -4,9 +4,9 @@
+ 
+ /* 
+ * File:    freebsd.c
+-* CVS:     $Id: freebsd.c,v 1.1 2008-04-26 08:19:38 servat Exp $
++* CVS:     $Id: freebsd.c,v 1.6 2009/07/09 13:02:25 servat Exp $
+ * Author:  Harald Servat
+-*          harald.servat@gmail.com
++*          redcrash@gmail.com
+ */
+ 
+ #include <sys/types.h>
+@@ -147,6 +147,14 @@
+ 		Context.CPUsubstrate = CPU_K8;
+ 	else if (strcmp(pmc_name_of_cputype(info->pm_cputype), "INTEL_PIV") == 0)
+ 		Context.CPUsubstrate = CPU_P4;
++	else if (strcmp(pmc_name_of_cputype(info->pm_cputype), "INTEL_ATOM") == 0)
++		Context.CPUsubstrate = CPU_ATOM;
++	else if (strcmp(pmc_name_of_cputype(info->pm_cputype), "INTEL_CORE") == 0)
++		Context.CPUsubstrate = CPU_CORE;
++	else if (strcmp(pmc_name_of_cputype(info->pm_cputype), "INTEL_CORE2") == 0)
++		Context.CPUsubstrate = CPU_CORE2;
++	else if (strcmp(pmc_name_of_cputype(info->pm_cputype), "INTEL_CORE2EXTREME") == 0)
++		Context.CPUsubstrate = CPU_CORE2EXTREME;
+ 	else
+ 		/* Unknown processor! */
+ 		Context.CPUsubstrate = CPU_UNKNOWN;
+@@ -168,14 +176,11 @@
+  */
+ int init_mdi(void)
+ {
+-	int result;
+ 	const struct pmc_cpuinfo *info;
+    
  	SHOW_WHERE_I_AM;
  
  	/* Initialize PMC library */
@@ -9,7 +42,7 @@
  	if (pmc_init() < 0)
  		return PAPI_ESYS;
        
-@@ -187,7 +185,7 @@
+@@ -187,7 +192,7 @@
  		/* Get CPU clock rate from HW.CLOCKRATE sysctl value, and
  		   MODEL from HW.MODEL */
  		int mib[5];
diff --git a/devel/papi/files/patch-freebsd.h b/devel/papi/files/patch-freebsd.h
new file mode 100644
index 000000000000..c14185c66e4f
--- /dev/null
+++ b/devel/papi/files/patch-freebsd.h
@@ -0,0 +1,25 @@
+--- ./freebsd.h.orig	2008-04-26 04:19:38.000000000 -0400
++++ ./freebsd.h	2009-07-15 12:05:10.807711000 -0400
+@@ -3,11 +3,11 @@
+ /****************************/
+ /* 
+ * File:    freebsd-libpmc.c
+-* CVS:     $Id: freebsd.h,v 1.1 2008-04-26 08:19:38 servat Exp $
++* CVS:     $Id: freebsd.h,v 1.3 2009/07/09 13:02:25 servat Exp $
+ * Author:  Kevin London
+ *          london@cs.utk.edu
+ * Mods:    Harald Servat
+-*          harald.servat@gmail.com
++*          redcrash@gmail.com
+ */
+ 
+ #ifndef _PAPI_FreeBSD_H
+@@ -51,7 +51,7 @@
+ 	int hwc_domain;      /* HWC domain {user|kernel} */
+ 	unsigned *caps;      /* Capabilities for each counter */
+ 	pmc_id_t *pmcs;      /* PMC identifiers */
+-	long_long *values;   /* Stored values for each counter */
++	long long *values;   /* Stored values for each counter */
+ 	char **counters;     /* Name of each counter (with mode) */
+ } hwd_control_state_t;
+ 
diff --git a/devel/papi/files/patch-freebsd__map-atom.c b/devel/papi/files/patch-freebsd__map-atom.c
new file mode 100644
index 000000000000..a07e65cbb4ef
--- /dev/null
+++ b/devel/papi/files/patch-freebsd__map-atom.c
@@ -0,0 +1,267 @@
+--- ./freebsd/map-atom.c.orig	2009-07-15 12:05:10.607715000 -0400
++++ ./freebsd/map-atom.c	2009-07-15 12:05:10.610728000 -0400
+@@ -0,0 +1,264 @@
++/****************************/
++/* THIS IS OPEN SOURCE CODE */
++/****************************/
++
++/* 
++* File:    map-atom.c
++* CVS:     $Id: map-atom.c,v 1.2 2009/07/09 13:02:25 servat Exp $
++* Author:  Harald Servat
++*          redcrash@gmail.com
++*/
++
++#include SUBSTRATE
++#include "papiStdEventDefs.h"
++#include "map.h"
++
++/****************************************************************************
++ ATOM SUBSTRATE 
++ ATOM SUBSTRATE 
++ ATOM SUBSTRATE
++ ATOM SUBSTRATE
++ ATOM SUBSTRATE
++****************************************************************************/
++
++/*
++        NativeEvent_Value_AtomProcessor must match AtomProcessor_info 
++*/
++
++Native_Event_LabelDescription_t AtomProcessor_info[] =
++{
++	{"BACLEARS", "The number of times the front end is resteered."},
++	{"BOGUS_BR", "The number of byte sequences mistakenly detected as taken branch instructions."},
++	{"BR_BAC_MISSP_EXEC", "The number of branch instructions that were mispredicted when decoded."},
++	{"BR_CALL_MISSP_EXEC", "The number of mispredicted CALL instructions that were executed."},
++	{"BR_CALL_EXEC", "The number of CALL instructions executed."},
++	{"BR_CND_EXEC", "The number of conditional branches executed, but not necessarily retired."},
++	{"BR_CND_MISSP_EXEC", "The number of mispredicted conditional branches executed."},
++	{"BR_IND_CALL_EXEC", "The number of indirect CALL instructions executed."},
++	{"BR_IND_EXEC", "The number of indirect branch instructions executed."},
++	{"BR_IND_MISSP_EXEC", "The number of mispredicted indirect branch instructions executed."},
++	{"BR_INST_DECODED", "The number of branch instructions decoded."},
++	{"BR_INST_EXEC", "The number of branches executed, but not necessarily retired."},
++	{"BR_INST_RETIRED.ANY", "The number of branch instructions retired. This is an architectural performance event."},
++	{"BR_INST_RETIRED.ANY1", "The number of branch instructions retired that were mispredicted."},
++	{"BR_INST_RETIRED.MISPRED", "The number of mispredicted branch instructions retired. This is an architectural performance event."},
++	{"BR_INST_RETIRED.MISPRED_NOT_TAKEN", "The number of not taken branch instructions retired that were mispredicted."},
++	{"BR_INST_RETIRED.MISPRED_TAKEN", "The number taken branch instructions retired that were mispredicted."},
++	{"BR_INST_RETIRED.PRED_NOT_TAKEN", "The number of not taken branch instructions retired that were correctly predicted."},
++	{"BR_INST_RETIRED.PRED_TAKEN", "The number of taken branch instructions retired that were correctly predicted."},
++	{"BR_INST_RETIRED.TAKEN", "The number of taken branch instructions retired."},
++	{"BR_MISSP_EXEC", "The number of mispredicted branch instructions that were executed."},
++	{"BR_RET_MISSP_EXEC", "The number of mispredicted RET instructions executed."},
++	{"BR_RET_BAC_MISSP_EXEC", "The number of RET instructions executed that were mispredicted at decode time."},
++	{"BR_RET_EXEC", "The number of RET instructions executed."},
++	{"BR_TKN_BUBBLE_1", "The number of branch predicted taken with bubble 1."},
++	{"BR_TKN_BUBBLE_2", "The number of branch predicted taken with bubble 2."},
++	{"BUSQ_EMPTY", "The number of cycles during which the core did not have any pending transactions in the bus queue."},
++	{"BUS_BNR_DRV", "The number of Bus Not Ready signals asserted on the bus.  This event is thread-independent."},
++	{"BUS_DATA_RCV", "The number of bus cycles during which the processor is receiving data.  This event is thread-independent."},
++	{"BUS_DRDY_CLOCKS", "The number of bus cycles during which the Data Ready signal is asserted on the bus.  This event is thread-independent."},
++	{"BUS_HIT_DRV", "The number of bus cycles during which the processor drives the HIT# pin.  This event is thread-independent."},
++	{"BUS_HITM_DRV", "The number of bus cycles during which the processor drives the HITM# pin.  This event is thread-independent."},
++	{"BUS_IO_WAIT", "The number of core cycles during which I/O requests wait in the bus queue."},
++	{"BUS_LOCK_CLOCKS", "The number of bus cycles during which the LOCK signal was asserted on the bus.  This event is thread independent."},
++	{"BUS_REQUEST_OUTSTANDING", "The number of pending full cache line read transactions on the bus occuring in each cycle.  This event is thread independent."},
++	{"BUS_TRANS_P", "The number of partial bus transactions."},
++	{"BUS_TRANS_IFETCH", "The number of instruction fetch full cache line bus transactions."},
++	{"BUS_TRANS_INVAL", "The number of invalidate bus transactions."},
++	{"BUS_TRANS_PWR", "The number of partial write bus transactions."},
++	{"BUS_TRANS_DEF", "The number of deferred bus transactions."},
++	{"BUS_TRANS_BURST", "The number of burst transactions."},
++	{"BUS_TRANS_MEM", "The number of memory bus transactions."},
++	{"BUS_TRANS_ANY", "The number of bus transactions of any kind."},
++	{"BUS_TRANS_BRD", "The number of burst read transactions."},
++	{"BUS_TRANS_IO", "The number of completed I/O bus transaactions due to IN and OUT instructions."},
++	{"BUS_TRANS_RFO", "The number of Read For Ownership bus transactions."},
++	{"BUS_TRANS_WB", "The number explicit writeback bus transactions due to dirty line evictions."},
++	{"CMP_SNOOP", "The number of times the L1 data cache is snooped by the other core in the same processor."},
++	{"CPU_CLK_UNHALTED.BUS", "The number of bus cycles when the core is not in the halt state. This is an architectural performance event."},
++	{"CPU_CLK_UNHALTED.CORE_P", "The number of core cycles while the core is not in a halt state. This is an architectural performance event."},
++	{"CPU_CLK_UNHALTED.NO_OTHER", "The number of bus cycles during which the core remains unhalted and the other core is halted."},
++	{"CYCLES_DIV_BUSY", "The number of cycles the divider is busy."},
++	{"CYCLES_INT_MASKED.CYCLES_INT_MASKED", "The number of cycles during which interrupts are disabled."},
++	{"CYCLES_INT_MASKED.CYCLES_INT_PENDING_AND_MASKED", "The number of cycles during which there were pending interrupts while interrupts were disabled."},
++	{"CYCLES_L1I_MEM_STALLED", "The number of cycles for which an instruction fetch stalls."},
++	{"DATA_TLB_MISSES.DTLB_MISS", "The number of memory access that missed the Data TLB"},
++	{"DATA_TLB_MISSES.DTLB_MISS_LD", "The number of loads that missed the Data TLB."},
++	{"DATA_TLB_MISSES.DTLB_MISS_ST", "The number of stores that missed the Data TLB."},
++	{"DATA_TLB_MISSES.UTLB_MISS_LD", "The number of loads that missed the UTLB."},
++	{"DELAYED_BYPASS.FP", "The number of floating point operations that used data immediately after the data was generated by a non floating point execution unit."},
++	{"DELAYED_BYPASS.LOAD", "The number of delayed bypass penalty cycles that a load operation incurred."},
++	{"DELAYED_BYPASS.SIMD", "The number of times SIMD operations use data immediately after data, was generated by a non-SIMD execution unit."},
++	{"DIV", "The number of divide operations executed.  This event is only available on PMC1."},
++	{"DIV.AR", "The number of divide operations retired."},
++	{"DIV.S", "The number of divide operations executed."},
++	{"DTLB_MISSES.ANY", "The number of Data TLB misses, including misses that result from speculative accesses."},
++	{"DTLB_MISSES.L0_MISS_LD", "The number of level 0 DTLB misses due to load operations."},
++	{"DTLB_MISSES.MISS_LD", "The number of Data TLB misses due to load operations."},
++	{"DTLB_MISSES.MISS_ST", "The number of Data TLB misses due to store operations."},
++	{"EIST_TRANS", "The number of Enhanced Intel SpeedStep Technology transitions."},
++	{"ESP.ADDITIONS", "The number of automatic additions to the esp register."},
++	{"ESP.SYNCH", "The number of times the esp register was explicitly used in an address expression after it is implicitly used by a PUSH or POP instruction."},
++	{"EXT_SNOOP", "The number of snoop responses to bus transactions."},
++	{"FP_ASSIST", "The number of floating point operations executed that needed a microcode assist, including speculatively executed instructions."},
++	{"FP_ASSIST.AR", "The number of floating point operations retired that needed a microcode assist."},
++	{"FP_COMP_OPS_EXE", "The number of floating point computational micro-ops executed.  The event is available only on PMC0."},
++	{"FP_MMX_TRANS_TO_FP", "The number of transitions from MMX instructions to floating point instructions."},
++	{"FP_MMX_TRANS_TO_MMX", "The number of transitions from floating point instructions to MMX instructions."},
++	{"HW_INT_RCV", "The number of hardware interrupts recieved."},
++	{"ICACHE.ACCESSES", "The number of instruction fetches."},
++	{"ICACHE.MISSES", "The number of instruction fetches that miss the instruction cache."},
++	{"IDLE_DURING_DIV", "The number of cycles the divider is busy and no other execution unit or load operation was in progress.  This event is available only on PMC0."},
++	{"ILD_STALL", "The number of cycles the instruction length decoder stalled due to a length changing prefix."},
++	{"INST_QUEUE.FULL", "The number of cycles during which the instruction queue is full."},
++	{"INST_RETIRED.ANY_P", "The number of instructions retired. This is an architectural performance event."},
++	{"INST_RETIRED.LOADS", "The number of instructions retired that contained a load operation."},
++	{"INST_RETIRED.OTHER", "The number of instructions retired that did not contain a load or a store operation."},
++	{"INST_RETIRED.STORES", "The number of instructions retired that contained a store operation."},
++	{"ITLB.FLUSH", "The number of ITLB flushes."},
++	{"ITLB.LARGE_MISS", "The number of instruction fetches from large pages that miss the ITLB."},
++	{"ITLB.MISSES", "The number of instruction fetches from both large and small pages that miss the ITLB."},
++	{"ITLB.SMALL_MISS", "The number of instruction fetches from small pages that miss the ITLB."},
++	{"ITLB_MISS_RETIRED", "The number of retired instructions that missed the ITLB when they were fetched."},
++	{"L1D_ALL_REF", "The number of references to L1 data cache counting loads and stores of to all memory types."},
++	{"L1D_ALL_CACHE_REF", "The number of data reads and writes to cacheable memory."},
++	{"L1D_CACHE_LOCK", "The number of locked reads from cacheable memory."},
++	{"L1D_CACHE_LOCK_DURATION", "The number of cycles during which any cache line is locked by any locking instruction."},
++	{"L1D_CACHE.LD", "The number of data reads from cacheable memory."},
++	{"L1D_CACHE.ST", "The number of data writes to cacheable memory."},
++	{"L1D_M_EVICT", "The number of modified cache lines evicted from L1 data cache."},
++	{"L1D_M_REPL", "The number of modified lines allocated in L1 data cache."},
++	{"L1D_PEND_MISS", "The total number of outstanding L1 data cache misses at any clock."},
++	{"L1D_PREFETCH.REQUESTS", "The number of times L1 data cache requested to prefetch a data cache line."},
++	{"L1D_REPL", "The number of lines brought into L1 data cache."},
++	{"L1D_SPLIT.LOADS", "The number of load operations that span two cache lines."},
++	{"L1D_SPLIT.STORES", "The number of store operations that span two cache lines."},
++	{"L1I_MISSES", "The number of instruction fetch unit misses."},
++	{"L1I_READS", "The number of instruction fetches."},
++	{"L2_ADS", "The number of cycles that the L2 address bus is in use."},
++	{"L2_DBUS_BUSY_RD", "The number of core cycles during which the L2 data bus is busy transferring data to the core."},
++	{"L2_IFETCH", "The number of instruction cache line requests from the instruction fetch unit."},
++	{"L2_LD", "The number of L2 cache read requests from L1 cache and L2 prefetchers."},
++	{"L2_LINES_IN", "The number of cache lines allocated in L2 cache."},
++	{"L2_LINES_OUT", "The number of L2 cache lines evicted."},
++	{"L2_LOCK", "The number of locked accesses to cache lines that miss L1 data cache."},
++	{"L2_M_LINES_IN", "The number of L2 cache line modifications."},
++	{"L2_M_LINES_OUT", "The number of modified lines evicted from L2 cache."},
++	{"L2_NO_REQ", "The number of cycles during which no L2 cache requests were pending from a core."},
++	{"L2_REJECT_BUSQ", "The number of L2 cache requests that were rejected."},
++	{"L2_RQSTS", "The number of completed L2 cache requests."},
++	{"L2_RQSTS.SELF.DEMAND.I_STATE", "The number of completed L2 cache demand requests from this core that missed the L2 cache. This is an architectural performance event."},
++	{"L2_RQSTS.SELF.DEMAND.MESI", "The number of completed L2 cache demand requests from this core."},
++	{"L2_ST", "The number of store operations that miss the L1 cache and request data from the L2 cache."},
++	{"LOAD_BLOCK.L1D", "The number of loads blocked by the L1 data cache."},
++	{"LOAD_BLOCK.OVERLAP_STORE", "The number of loads that partially overlap an earlier store or are aliased with a previous store."},
++	{"LOAD_BLOCK.STA", "The number of loads blocked by preceding stores whose address is yet to be calculated."},
++	{"LOAD_BLOCK.STD", "The number of loads blocked by preceding stores to the same address whose data value is not known."},
++	{"LOAD_BLOCK.UNTIL_RETIRE", "The numer of load operations that were blocked until retirement."},
++	{"LOAD_HIT_PRE", "The number of load operations that conflicted with an prefetch to the same cache line."},
++	{"MACHINE_CLEARS.SMC", "The number of times a program writes to a code section."},
++	{"MACHINE_NUKES.MEM_ORDER", "The number of times the execution pipeline was restarted due to a memory ordering conflict or memory disambiguation misprediction."},
++	{"MACRO_INSTS.ALL_DECODED", "The number of instructions decoded."},
++	{"MACRO_INSTS.CISC_DECODED", "The number of complex instructions decoded."},
++	{"MEMORY_DISAMBIGUATION.RESET", "The number of cycles during which memory disambiguation misprediction occurs."},
++	{"MEMORY_DISAMBIGUATION.SUCCESS", "The number of load operations that were successfully disambiguated."},
++	{"MEM_LOAD_RETIRED.DTLB_MISS", "The number of retired load operations that missed the DTLB."},
++	{"MEM_LOAD_RETIRED.L2_MISS", "The number of retired load operations that miss L2 cache."},
++	{"MEM_LOAD_RETIRED.L2_HIT", "The number of retired load operations that hit L2 cache."},
++	{"MEM_LOAD_RETIRED.L2_LINE_MISS", "The number of load operations that missed L2 cache and that caused a bus request."},
++	{"MUL", "The number of multiply operations executed.  This event is only available on PMC1."},
++	{"MUL.AR", "The number of multiply operations retired."},
++	{"MUL.S", "The number of multiply operations executed."},
++	{"PAGE_WALKS.WALKS", "The number of page walks executed due to an ITLB or DTLB miss."},
++	{"PAGE_WALKS.CYCLES", "The number of cycles spent in a page walk caused by an ITLB or DTLB miss."},
++	{"PREF_RQSTS_DN", "The number of downward prefetches issued from the Data Prefetch Logic unit to L2 cache."},
++	{"PREF_RQSTS_UP", "The number of upward prefetches issued from the Data Prefetch Logic unit to L2 cache."},
++	{"PREFETCH.PREFETCHNTA", "The number of PREFETCHNTA instructions executed."},
++	{"PREFETCH.PREFETCHT0", "The number of PREFETCHT0 instructions executed."},
++	{"PREFETCH.SW_L2", "The number of PREFETCHT1 and PREFETCHT2 instructions executed."},
++	{"RAT_STALLS.ANY", "The number of stall cycles due to any of RAT_STALLS.FLAGS RAT_STALLS.FPSW, RAT_STALLS.PARTIAL and RAT_STALLS.ROB_READ_PORT."},
++	{"RAT_STALLS.FLAGS", "The number of cycles execution stalled due to a flag register induced stall."},
++	{"RAT_STALLS.FPSW", "The number of times the floating point status word was written."},
++	{"RAT_STALLS.PARTIAL_CYCLES", "The number of cycles of added instruction execution latency due to the use of a register that was partially written by previous instructions."},
++	{"RAT_STALLS.ROB_READ_PORT", "The number of cycles when ROB read port stalls occurred."},
++	{"RESOURCE_STALLS.ANY", "The number of cycles during which any resource related stall occurred."},
++	{"RESOURCE_STALLS.BR_MISS_CLEAR", "The number of cycles stalled due to branch misprediction."},
++	{"RESOURCE_STALLS.FPCW", "The number of cycles stalled due to writing the floating point control word."},
++	{"RESOURCE_STALLS.LD_ST", "The number of cycles during which the number of loads and stores in the pipeline exceeded their limits."},
++	{"RESOURCE_STALLS.ROB_FULL", "The number of cycles when the reorder buffer was full."},
++	{"RESOURCE_STALLS.RS_FULL", "The number of cycles during which the RS was full."},
++	{"RS_UOPS_DISPATCHED", "The number of micro-ops dispatched for execution."},
++	{"RS_UOPS_DISPATCHED.PORT0", "The number of cycles micro-ops were dispatched for execution on port 0."},
++	{"RS_UOPS_DISPATCHED.PORT1", "The number of cycles micro-ops were dispatched for execution on port 1."},
++	{"RS_UOPS_DISPATCHED.PORT2", "The number of cycles micro-ops were dispatched for execution on port 2."},
++	{"RS_UOPS_DISPATCHED.PORT3", "The number of cycles micro-ops were dispatched for execution on port 3."},
++	{"RS_UOPS_DISPATCHED.PORT4", "The number of cycles micro-ops were dispatched for execution on port 4."},
++	{"RS_UOPS_DISPATCHED.PORT5", "The number of cycles micro-ops were dispatched for execution on port 5."},
++	{"SB_DRAIN_CYCLES", "The number of cycles while the store buffer is draining."},
++	{"SEGMENT_REG_LOADS.ANY", "The number of segment register loads."},
++	{"SEG_REG_RENAMES.ANY", "The number of times the any segment register was renamed."},
++	{"SEG_REG_RENAMES.DS", "The number of times the ds register is renamed."},
++	{"SEG_REG_RENAMES.ES", "The number of times the es register is renamed."},
++	{"SEG_REG_RENAMES.FS", "The number of times the fs register is renamed."},
++	{"SEG_REG_RENAMES.GS", "The number of times the gs register is renamed."},
++	{"SEG_RENAME_STALLS.ANY", "The number of stalls due to lack of resource to rename any segment register."},
++	{"SEG_RENAME_STALLS.DS", "The number of stalls due to lack of renaming resources for the ds register."},
++	{"SEG_RENAME_STALLS.ES", "The number of stalls due to lack of renaming resources for the es register."},
++	{"SEG_RENAME_STALLS.FS", "The number of stalls due to lack of renaming resources for the fs register."},
++	{"SEG_RENAME_STALLS.GS", "The number of stalls due to lack of renaming resources for the gs register."},
++	{"SIMD_ASSIST", "The number SIMD assists invoked."},
++	{"SIMD_COMP_INST_RETIRED.PACKED_DOUBLE", "Then number of computational SSE2 packed double precision instructions retired."},
++	{"SIMD_COMP_INST_RETIRED.PACKED_SINGLE", "Then number of computational SSE2 packed single precision instructions retired."},
++	{"SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE", "Then number of computational SSE2 scalar double precision instructions retired."},
++	{"SIMD_COMP_INST_RETIRED.SCALAR_SINGLE", "Then number of computational SSE2 scalar single precision instructions retired."},
++	{"SIMD_INSTR_RETIRED", "The number of retired SIMD instructions that use MMX registers."},
++	{"SIMD_INST_RETIRED.ANY", "The number of streaming SIMD instructions retired."},
++	{"SIMD_INST_RETIRED.PACKED_DOUBLE", "The number of SSE2 packed double precision instructions retired."},
++	{"SIMD_INST_RETIRED.PACKED_SINGLE", "The number of SSE packed single precision instructions retired."},
++	{"SIMD_INST_RETIRED.SCALAR_DOUBLE", "The number of SSE2 scalar double precision instructions retired."},
++	{"SIMD_INST_RETIRED.SCALAR_SINGLE", "The number of SSE scalar single precision instructions retired."},
++	{"SIMD_INST_RETIRED.VECTOR", "The number of SSE2 vector instructions retired."},
++	{"SIMD_SAT_INSTR_RETIRED", "The number of saturated arithmetic SIMD instructions retired."},
++	{"SIMD_SAT_UOP_EXEC.AR", "The number of SIMD saturated arithmetic micro-ops retired."},
++	{"SIMD_SAT_UOP_EXEC.S", "The number of SIMD saturated arithmetic micro-ops executed."},
++	{"SIMD_UOPS_EXEC.AR", "The number of SIMD micro-ops retired."},
++	{"SIMD_UOPS_EXEC.S", "The number of SIMD micro-ops executed."},
++	{"SIMD_UOP_TYPE_EXEC.ARITHMETIC.AR", "The number of SIMD packed arithmetic micro-ops executed."},
++	{"SIMD_UOP_TYPE_EXEC.ARITHMETIC.S", "The number of SIMD packed arithmetic micro-ops executed."},
++	{"SIMD_UOP_TYPE_EXEC.LOGICAL.AR", "The number of SIMD packed logical microops executed."},
++	{"SIMD_UOP_TYPE_EXEC.LOGICAL.S", "The number of SIMD packed logical microops executed."},
++	{"SIMD_UOP_TYPE_EXEC.MUL.AR", "The number of SIMD packed multiply microops retired."},
++	{"SIMD_UOP_TYPE_EXEC.MUL.S", "The number of SIMD packed multiply microops executed."},
++	{"SIMD_UOP_TYPE_EXEC.PACK.AR", "The number of SIMD pack micro-ops retired."},
++	{"SIMD_UOP_TYPE_EXEC.PACK.S", "The number of SIMD pack micro-ops executed."},
++	{"SIMD_UOP_TYPE_EXEC.SHIFT.AR", "The number of SIMD packed shift micro-ops retired."},
++	{"SIMD_UOP_TYPE_EXEC.SHIFT.S", "The number of SIMD packed shift micro-ops executed."},
++	{"SIMD_UOP_TYPE_EXEC.UNPACK.AR", "The number of SIMD unpack micro-ops executed."},
++	{"SIMD_UOP_TYPE_EXEC.UNPACK.S", "The number of SIMD unpack micro-ops executed."},
++	{"SNOOP_STALL_DRV", "The number of times the bus stalled for snoops.  This event is thread-independent."},
++	{"SSE_PRE_EXEC.L2", "The number of PREFETCHT1 instructions executed."},
++	{"SSE_PRE_EXEC.STORES", "The number of times SSE non-temporal store instructions were executed."},
++	{"SSE_PRE_MISS.L1", "The number of times the PREFETCHT0 instruction executed and missed all cache levels."},
++	{"SSE_PRE_MISS.L2", "The number of times the PREFETCHT1 instruction executed and missed all cache levels."},
++	{"SSE_PRE_MISS.NTA", "The number of times the PREFETCHNTA instruction executed and missed all cache levels."},
++	{"STORE_BLOCK.ORDER", "The number of cycles while a store was waiting for another store to be globally observed."},
++	{"STORE_BLOCK.SNOOP", "The number of cycles while a store was blocked due to a conflict with an internal or external snoop."},
++	{"STORE_FORWARDS.GOOD", "The number of times stored data was forwarded directly to a load."},
++	{"THERMAL_TRIP", "The number of thermal trips."},
++	{"UOPS_RETIRED.LD_IND_BR", "The number of micro-ops retired that fused a load with another operation."},
++	{"UOPS_RETIRED.STD_STA", "The number of store address calculations that fused into one micro-op."},
++	{"UOPS_RETIRED.MACRO_FUSION", "The number of times retired instruction pairs were fused into one micro-op."},
++	{"UOPS_RETIRED.FUSED", "The number of fused micro-ops retired."},
++	{"UOPS_RETIRED.NON_FUSED", "The number of non-fused micro-ops retired."},
++	{"UOPS_RETIRED.ANY", "The number of micro-ops retired."},
++	{"X87_COMP_OPS_EXE.ANY.AR", "The number of x87 floating-point computational micro-ops retired."},
++	{"X87_COMP_OPS_EXE.ANY.S", "The number of x87 floating-point computational micro-ops executed."},
++	{"X87_OPS_RETIRED.ANY", "The number of floating point computational instructions retired."},
++	{"X87_OPS_RETIRED.FXCH", "The number of FXCH instructions retired."},
++	{ NULL, NULL }
++};
++
++/* PAPI PRESETS */
++hwi_search_t AtomProcessor_map[] = {
++	{0, {0, {PAPI_NULL}, {0,}}}
++};
diff --git a/devel/papi/files/patch-freebsd__map-atom.h b/devel/papi/files/patch-freebsd__map-atom.h
new file mode 100644
index 000000000000..6ded02e24b08
--- /dev/null
+++ b/devel/papi/files/patch-freebsd__map-atom.h
@@ -0,0 +1,253 @@
+--- ./freebsd/map-atom.h.orig	2009-07-15 12:05:10.626716000 -0400
++++ ./freebsd/map-atom.h	2009-07-15 12:05:10.636718000 -0400
+@@ -0,0 +1,250 @@
++/****************************/
++/* THIS IS OPEN SOURCE CODE */
++/****************************/
++
++/* 
++* File:    map-atom.h
++* CVS:     $Id: map-atom.h,v 1.2 2009/07/09 13:02:26 servat Exp $
++* Author:  Harald Servat
++*          redcrash@gmail.com
++*/
++
++#ifndef FreeBSD_MAP_ATOM
++#define FreeBSD_MAP_ATOM
++
++enum NativeEvent_Value_AtomProcessor {
++	PNE_ATOM_BACLEARS = PAPI_NATIVE_MASK,
++	PNE_ATOM_BOGUS_BR,
++	PNE_ATOM_BR_BAC_MISSP_EXEC,
++	PNE_ATOM_BR_CALL_MISSP_EXEC,
++	PNE_ATOM_BR_CALL_EXEC,
++	PNE_ATOM_BR_CND_EXEC,
++	PNE_ATOM_BR_CND_MISSP_EXEC,
++	PNE_ATOM_BR_IND_CALL_EXEC,
++	PNE_ATOM_BR_IND_EXEC,
++	PNE_ATOM_BR_IND_MISSP_EXEC,
++	PNE_ATOM_BR_INST_DECODED,
++	PNE_ATOM_BR_INST_EXEC,
++	PNE_ATOM_BR_INST_RETIRED_ANY,
++	PNE_ATOM_BR_INST_RETIRED_ANY1,
++	PNE_ATOM_BR_INST_RETIRED_MISPRED,
++	PNE_ATOM_BR_INST_RETIRED_MISPRED_NOT_TAKEN,
++	PNE_ATOM_BR_INST_RETIRED_MISPRED_TAKEN,
++	PNE_ATOM_BR_INST_RETIRED_PRED_NOT_TAKEN,
++	PNE_ATOM_BR_INST_RETIRED_PRED_TAKEN,
++	PNE_ATOM_BR_INST_RETIRED_TAKEN,
++	PNE_ATOM_BR_MISSP_EXEC,
++	PNE_ATOM_BR_RET_MISSP_EXEC,
++	PNE_ATOM_BR_RET_BAC_MISSP_EXEC,
++	PNE_ATOM_BR_RET_EXEC,
++	PNE_ATOM_BR_TKN_BUBBLE_1,
++	PNE_ATOM_BR_TKN_BUBBLE_2,
++	PNE_ATOM_BUSQ_EMPTY,
++	PNE_ATOM_BUS_BNR_DRV,
++	PNE_ATOM_BUS_DATA_RCV,
++	PNE_ATOM_BUS_DRDY_CLOCKS,
++	PNE_ATOM_BUS_HIT_DRV,
++	PNE_ATOM_BUS_HITM_DRV,
++	PNE_ATOM_BUS_IO_WAIT,
++	PNE_ATOM_BUS_LOCK_CLOCKS,
++	PNE_ATOM_BUS_REQUEST_OUTSTANDING,
++	PNE_ATOM_BUS_TRANS_P,
++	PNE_ATOM_BUS_TRANS_IFETCH,
++	PNE_ATOM_BUS_TRANS_INVAL,
++	PNE_ATOM_BUS_TRANS_PWR,
++	PNE_ATOM_BUS_TRANS_DEF,
++	PNE_ATOM_BUS_TRANS_BURST,
++	PNE_ATOM_BUS_TRANS_MEM,
++	PNE_ATOM_BUS_TRANS_ANY,
++	PNE_ATOM_BUS_TRANS_BRD,
++	PNE_ATOM_BUS_TRANS_IO,
++	PNE_ATOM_BUS_TRANS_RFO,
++	PNE_ATOM_BUS_TRANS_WB,
++	PNE_ATOM_CMP_SNOOP,
++	PNE_ATOM_CPU_CLK_UNHALTED_BUS,
++	PNE_ATOM_CPU_CLK_UNHALTED_CORE_P,
++	PNE_ATOM_CPU_CLK_UNHALTED_NO_OTHER,
++	PNE_ATOM_CYCLES_DIV_BUSY,
++	PNE_ATOM_CYCLES_INT_MASKED_CYCLES_INT_MASKED,
++	PNE_ATOM_CYCLES_INT_MASKED_CYCLES_INT_PENDING_AND_MASKED,
++	PNE_ATOM_CYCLES_L1I_MEM_STALLED,
++	PNE_ATOM_DATA_TLB_MISSES_DTLB_MISS,
++	PNE_ATOM_DATA_TLB_MISSES_DTLB_MISS_LD,
++	PNE_ATOM_DATA_TLB_MISSES_DTLB_MISS_ST,
++	PNE_ATOM_DATA_TLB_MISSES_UTLB_MISS_LD,
++	PNE_ATOM_DELAYED_BYPASS_FP,
++	PNE_ATOM_DELAYED_BYPASS_LOAD,
++	PNE_ATOM_DELAYED_BYPASS_SIMD,
++	PNE_ATOM_DIV,
++	PNE_ATOM_DIV_AR,
++	PNE_ATOM_DIV_S,
++	PNE_ATOM_DTLB_MISSES_ANY,
++	PNE_ATOM_DTLB_MISSES_L0_MISS_LD,
++	PNE_ATOM_DTLB_MISSES_MISS_LD,
++	PNE_ATOM_DTLB_MISSES_MISS_ST,
++	PNE_ATOM_EIST_TRANS,
++	PNE_ATOM_ESP_ADDITIONS,
++	PNE_ATOM_ESP_SYNCH,
++	PNE_ATOM_EXT_SNOOP,
++	PNE_ATOM_FP_ASSIST,
++	PNE_ATOM_FP_ASSIST_AR,
++	PNE_ATOM_FP_COMP_OPS_EXE,
++	PNE_ATOM_FP_MMX_TRANS_TO_FP,
++	PNE_ATOM_FP_MMX_TRANS_TO_MMX,
++	PNE_ATOM_HW_INT_RCV,
++	PNE_ATOM_ICACHE_ACCESSES,
++	PNE_ATOM_ICACHE_MISSES,
++	PNE_ATOM_IDLE_DURING_DIV,
++	PNE_ATOM_ILD_STALL,
++	PNE_ATOM_INST_QUEUE_FULL,
++	PNE_ATOM_INST_RETIRED_ANY_P,
++	PNE_ATOM_INST_RETIRED_LOADS,
++	PNE_ATOM_INST_RETIRED_OTHER,
++	PNE_ATOM_INST_RETIRED_STORES,
++	PNE_ATOM_ITLB_FLUSH,
++	PNE_ATOM_ITLB_LARGE_MISS,
++	PNE_ATOM_ITLB_MISSES,
++	PNE_ATOM_ITLB_SMALL_MISS,
++	PNE_ATOM_ITLB_MISS_RETIRED,
++	PNE_ATOM_L1D_ALL_REF,
++	PNE_ATOM_L1D_ALL_CACHE_REF,
++	PNE_ATOM_L1D_CACHE_LOCK,
++	PNE_ATOM_L1D_CACHE_LOCK_DURATION,
++	PNE_ATOM_L1D_CACHE_LD,
++	PNE_ATOM_L1D_CACHE_ST,
++	PNE_ATOM_L1D_M_EVICT,
++	PNE_ATOM_L1D_M_REPL,
++	PNE_ATOM_L1D_PEND_MISS,
++	PNE_ATOM_L1D_PREFETCH_REQUESTS,
++	PNE_ATOM_L1D_REPL,
++	PNE_ATOM_L1D_SPLIT_LOADS,
++	PNE_ATOM_L1D_SPLIT_STORES,
++	PNE_ATOM_L1I_MISSES,
++	PNE_ATOM_L1I_READS,
++	PNE_ATOM_L2_ADS,
++	PNE_ATOM_L2_DBUS_BUSY_RD,
++	PNE_ATOM_L2_IFETCH,
++	PNE_ATOM_L2_LD,
++	PNE_ATOM_L2_LINES_IN,
++	PNE_ATOM_L2_LINES_OUT,
++	PNE_ATOM_L2_LOCK,
++	PNE_ATOM_L2_M_LINES_IN,
++	PNE_ATOM_L2_M_LINES_OUT,
++	PNE_ATOM_L2_NO_REQ,
++	PNE_ATOM_L2_REJECT_BUSQ,
++	PNE_ATOM_L2_RQSTS,
++	PNE_ATOM_L2_RQSTS_SELF_DEMAND_I_STATE,
++	PNE_ATOM_L2_RQSTS_SELF_DEMAND_MESI,
++	PNE_ATOM_L2_ST,
++	PNE_ATOM_LOAD_BLOCK_L1D,
++	PNE_ATOM_LOAD_BLOCK_OVERLAP_STORE,
++	PNE_ATOM_LOAD_BLOCK_STA,
++	PNE_ATOM_LOAD_BLOCK_STD,
++	PNE_ATOM_LOAD_BLOCK_UNTIL_RETIRE,
++	PNE_ATOM_LOAD_HIT_PRE,
++	PNE_ATOM_MACHINE_CLEARS_SMC,
++	PNE_ATOM_MACHINE_NUKES_MEM_ORDER,
++	PNE_ATOM_MACRO_INSTS_ALL_DECODED,
++	PNE_ATOM_MACRO_INSTS_CISC_DECODED,
++	PNE_ATOM_MEMORY_DISAMBIGUATION_RESET,
++	PNE_ATOM_MEMORY_DISAMBIGUATION_SUCCESS,
++	PNE_ATOM_MEM_LOAD_RETIRED_DTLB_MISS,
++	PNE_ATOM_MEM_LOAD_RETIRED_L2_MISS,
++	PNE_ATOM_MEM_LOAD_RETIRED_L2_HIT,
++	PNE_ATOM_MEM_LOAD_RETIRED_L2_LINE_MISS,
++	PNE_ATOM_MUL,
++	PNE_ATOM_MUL_AR,
++	PNE_ATOM_MUL_S,
++	PNE_ATOM_PAGE_WALKS_WALKS,
++	PNE_ATOM_PAGE_WALKS_CYCLES,
++	PNE_ATOM_PREF_RQSTS_DN,
++	PNE_ATOM_PREF_RQSTS_UP,
++	PNE_ATOM_PREFETCH_PREFETCHNTA,
++	PNE_ATOM_PREFETCH_PREFETCHT0,
++	PNE_ATOM_PREFETCH_SW_L2,
++	PNE_ATOM_RAT_STALLS_ANY,
++	PNE_ATOM_RAT_STALLS_FLAGS,
++	PNE_ATOM_RAT_STALLS_FPSW,
++	PNE_ATOM_RAT_STALLS_PARTIAL_CYCLES,
++	PNE_ATOM_RAT_STALLS_ROB_READ_PORT,
++	PNE_ATOM_RESOURCE_STALLS_ANY,
++	PNE_ATOM_RESOURCE_STALLS_BR_MISS_CLEAR,
++	PNE_ATOM_RESOURCE_STALLS_FPCW,
++	PNE_ATOM_RESOURCE_STALLS_LD_ST,
++	PNE_ATOM_RESOURCE_STALLS_ROB_FULL,
++	PNE_ATOM_RESOURCE_STALLS_RS_FULL,
++	PNE_ATOM_RS_UOPS_DISPATCHED,
++	PNE_ATOM_RS_UOPS_DISPATCHED_PORT0,
++	PNE_ATOM_RS_UOPS_DISPATCHED_PORT1,
++	PNE_ATOM_RS_UOPS_DISPATCHED_PORT2,
++	PNE_ATOM_RS_UOPS_DISPATCHED_PORT3,
++	PNE_ATOM_RS_UOPS_DISPATCHED_PORT4,
++	PNE_ATOM_RS_UOPS_DISPATCHED_PORT5,
++	PNE_ATOM_SB_DRAIN_CYCLES,
++	PNE_ATOM_SEGMENT_REG_LOADS_ANY,
++	PNE_ATOM_SEG_REG_RENAMES_ANY,
++	PNE_ATOM_SEG_REG_RENAMES_DS,
++	PNE_ATOM_SEG_REG_RENAMES_ES,
++	PNE_ATOM_SEG_REG_RENAMES_FS,
++	PNE_ATOM_SEG_REG_RENAMES_GS,
++	PNE_ATOM_SEG_RENAME_STALLS_ANY,
++	PNE_ATOM_SEG_RENAME_STALLS_DS,
++	PNE_ATOM_SEG_RENAME_STALLS_ES,
++	PNE_ATOM_SEG_RENAME_STALLS_FS,
++	PNE_ATOM_SEG_RENAME_STALLS_GS,
++	PNE_ATOM_SIMD_ASSIST,
++	PNE_ATOM_SIMD_COMP_INST_RETIRED_PACKED_DOUBLE,
++	PNE_ATOM_SIMD_COMP_INST_RETIRED_PACKED_SINGLE,
++	PNE_ATOM_SIMD_COMP_INST_RETIRED_SCALAR_DOUBLE,
++	PNE_ATOM_SIMD_COMP_INST_RETIRED_SCALAR_SINGLE,
++	PNE_ATOM_SIMD_INSTR_RETIRED,
++	PNE_ATOM_SIMD_INST_RETIRED_ANY,
++	PNE_ATOM_SIMD_INST_RETIRED_PACKED_DOUBLE,
++	PNE_ATOM_SIMD_INST_RETIRED_PACKED_SINGLE,
++	PNE_ATOM_SIMD_INST_RETIRED_SCALAR_DOUBLE,
++	PNE_ATOM_SIMD_INST_RETIRED_SCALAR_SINGLE,
++	PNE_ATOM_SIMD_INST_RETIRED_VECTOR,
++	PNE_ATOM_SIMD_SAT_INSTR_RETIRED,
++	PNE_ATOM_SIMD_SAT_UOP_EXEC_AR,
++	PNE_ATOM_SIMD_SAT_UOP_EXEC_S,
++	PNE_ATOM_SIMD_UOPS_EXEC_AR,
++	PNE_ATOM_SIMD_UOPS_EXEC_S,
++	PNE_ATOM_SIMD_UOP_TYPE_EXEC_ARITHMETIC_AR,
++	PNE_ATOM_SIMD_UOP_TYPE_EXEC_ARITHMETIC_S,
++	PNE_ATOM_SIMD_UOP_TYPE_EXEC_LOGICAL_AR,
++	PNE_ATOM_SIMD_UOP_TYPE_EXEC_LOGICAL_S,
++	PNE_ATOM_SIMD_UOP_TYPE_EXEC_MUL_AR,
++	PNE_ATOM_SIMD_UOP_TYPE_EXEC_MUL_S,
++	PNE_ATOM_SIMD_UOP_TYPE_EXEC_PACK_AR,
++	PNE_ATOM_SIMD_UOP_TYPE_EXEC_PACK_S,
++	PNE_ATOM_SIMD_UOP_TYPE_EXEC_SHIFT_AR,
++	PNE_ATOM_SIMD_UOP_TYPE_EXEC_SHIFT_S,
++	PNE_ATOM_SIMD_UOP_TYPE_EXEC_UNPACK_AR,
++	PNE_ATOM_SIMD_UOP_TYPE_EXEC_UNPACK_S,
++	PNE_ATOM_SNOOP_STALL_DRV,
++	PNE_ATOM_SSE_PRE_EXEC_L2,
++	PNE_ATOM_SSE_PRE_EXEC_STORES,
++	PNE_ATOM_SSE_PRE_MISS_L1,
++	PNE_ATOM_SSE_PRE_MISS_L2,
++	PNE_ATOM_SSE_PRE_MISS_NTA,
++	PNE_ATOM_STORE_BLOCK_ORDER,
++	PNE_ATOM_STORE_BLOCK_SNOOP,
++	PNE_ATOM_STORE_FORWARDS_GOOD,
++	PNE_ATOM_THERMAL_TRIP,
++	PNE_ATOM_UOPS_RETIRED_LD_IND_BR,
++	PNE_ATOM_UOPS_RETIRED_STD_STA,
++	PNE_ATOM_UOPS_RETIRED_MACRO_FUSION,
++	PNE_ATOM_UOPS_RETIRED_FUSED,
++	PNE_ATOM_UOPS_RETIRED_NON_FUSED,
++	PNE_ATOM_UOPS_RETIRED_ANY,
++	PNE_ATOM_X87_COMP_OPS_EXE_ANY_AR,
++	PNE_ATOM_X87_COMP_OPS_EXE_ANY_S,
++	PNE_ATOM_X87_OPS_RETIRED_ANY,
++	PNE_ATOM_X87_OPS_RETIRED_FXCH,
++	PNE_ATOM_NATNAME_GUARD
++};
++
++extern Native_Event_LabelDescription_t AtomProcessor_info[];
++extern hwi_search_t AtomProcessor_map[];
++
++#endif
diff --git a/devel/papi/files/patch-freebsd__map-core.c b/devel/papi/files/patch-freebsd__map-core.c
new file mode 100644
index 000000000000..f0ac4a072f98
--- /dev/null
+++ b/devel/papi/files/patch-freebsd__map-core.c
@@ -0,0 +1,171 @@
+--- ./freebsd/map-core.c.orig	2009-07-15 12:05:10.649730000 -0400
++++ ./freebsd/map-core.c	2009-07-15 12:05:10.652723000 -0400
+@@ -0,0 +1,168 @@
++/****************************/
++/* THIS IS OPEN SOURCE CODE */
++/****************************/
++
++/* 
++* File:    map-core.c
++* CVS:     $Id: map-core.c,v 1.2 2009/07/09 13:02:26 servat Exp $
++* Author:  Harald Servat
++*          redcrash@gmail.com
++*/
++
++#include SUBSTRATE
++#include "papiStdEventDefs.h"
++#include "map.h"
++
++/****************************************************************************
++ CORE SUBSTRATE 
++ CORE SUBSTRATE 
++ CORE SUBSTRATE
++ CORE SUBSTRATE
++ CORE SUBSTRATE
++****************************************************************************/
++
++/*
++        NativeEvent_Value_CoreProcessor must match CoreProcessor_info 
++*/
++
++Native_Event_LabelDescription_t CoreProcessor_info[] =
++{
++	{"BAClears", "The number of BAClear conditions asserted."},
++	{"BTB_Misses", "The number of branches for which the branch table buffer did not produce a prediction."},
++	{"Br_BAC_Missp_Exec", "The number of branch instructions executed that were mispredicted at the front end."},
++	{"Br_Bogus", "The number of bogus branches."},
++	{"Br_Call_Exec", "The number of CALL instructions executed."},
++	{"Br_Call_Missp_Exec", "The number of CALL instructions executed that were mispredicted."},
++	{"Br_Cnd_Exec", "The number of conditional branch instructions executed."},
++	{"Br_Cnd_Missp_Exec", "The number of conditional branch instructions executed that were mispredicted."},
++	{"Br_Ind_Call_Exec", "The number of indirect CALL instructions executed."},
++	{"Br_Ind_Exec", "The number of indirect branches executed."},
++	{"Br_Ind_Missp_Exec", "The number of indirect branch instructions executed that were mispredicted."},
++	{"Br_Inst_Exec", "The number of branch instructions executed including speculative branches."},
++	{"Br_Instr_Decoded", "The number of branch instructions decoded."},
++	{"Br_Instr_Ret", "The number of branch instructions retired. This is an architectural performance event."},
++	{"Br_MisPred_Ret", "The number of mispredicted branch instructions retired. This is an architectural performance event."},
++	{"Br_MisPred_Taken_Ret", "The number of taken and mispredicted branches retired."},
++	{"Br_Missp_Exec", "The number of branch instructions executed and mispredicted at execution including branches that were not predicted."},
++	{"Br_Ret_BAC_Missp_Exec", "The number of return branch instructions that were mispredicted at the front end."},
++	{"Br_Ret_Exec", "The number of return branch instructions executed."},
++	{"Br_Ret_Missp_Exec", "The number of return branch instructions executed that were mispredicted."},
++	{"Br_Taken_Ret", "The number of taken branches retired."},
++	{"Bus_BNR_Clocks", "was asserted."},
++	{"Bus_DRDY_Clocks", "The number of external bus cycles while DRDY was asserted."},
++	{"Bus_Data_Rcv", "The number of cycles during which the processor is busy receiving data."},
++	{"Bus_Locks_Clocks", "The number of external bus cycles while the bus lock signal was asserted."},
++	{"Bus_Not_In_Use", "The number of cycles when there is no transaction from the core."},
++	{"Bus_Req_Outstanding", "The weighted cycles of cacheable bus data read requests from the data cache unit or hardware prefetcher."},
++	{"Bus_Snoop_Stall", "The number bus cycles while a bus snoop is stalled."},
++	{"Bus_Snoops", "The number of snoop responses to bus transactions."},
++	{"Bus_Trans_Any", "The number of completed bus transactions."},
++	{"Bus_Trans_Brd", "The number of read bus transactions."},
++	{"Bus_Trans_Burst", "The number of completed burst transactions.  Retried transactions may be counted more than once."},
++	{"Bus_Trans_Def", "The number of completed deferred transactions."},
++	{"Bus_Trans_IO", "The number of completed I/O transactions counting both reads and writes."},
++	{"Bus_Trans_Ifetch", "Completed instruction fetch transactions."},
++	{"Bus_Trans_Inval", "The number completed invalidate transactions."},
++	{"Bus_Trans_Mem", "The number of completed memory transactions."},
++	{"Bus_Trans_P", "The number of completed partial transactions."},
++	{"Bus_Trans_Pwr", "The number of completed partial write transactions."},
++	{"Bus_Trans_RFO", "The number of completed read-for-ownership transactions."},
++	{"Bus_Trans_WB", "The number of completed writeback transactions from the data cache unit, excluding L2 writebacks."},
++	{"Cycles_Div_Busy", "The number of cycles the divider is busy.  The event is only available on PMC0."},
++	{"Cycles_Int_Masked", "The number of cycles while interrupts were disabled."},
++	{"Cycles_Int_Pending_Masked", "The number of cycles while interrupts were disabled and interrupts were pending."},
++	{"DCU_Snoop_To_Share", "The number of data cache unit snoops to L1 cache lines in the shared state."},
++	{"DCache_Cache_Lock", "The number of cacheable locked read operations to invalid state."},
++	{"DCache_Cache_LD", "The number of cacheable L1 data read operations."},
++	{"DCache_Cache_ST", "The number cacheable L1 data write operations."},
++	{"DCache_M_Evict", "The number of M state data cache lines that were evicted."},
++	{"DCache_M_Repl", "The number of M state data cache lines that were allocated."},
++	{"DCache_Pend_Miss", "The weighted cycles an L1 miss was outstanding."},
++	{"DCache_Repl", "The number of data cache line replacements."},
++	{"Data_Mem_Cache_Ref", "The number of cacheable read and write operations to L1 data cache."},
++	{"Data_Mem_Ref", "The number of L1 data reads and writes, both cacheable and uncacheable."},
++	{"Dbus_Busy", "The number of core cycles during which the data bus was busy."},
++	{"Dbus_Busy_Rd", "The nunber of cycles during which the data bus was busy transferring data to a core."},
++	{"Div", "The number of divide operations including speculative operations for integer and floating point divides. This event can only be counted on PMC1."},
++	{"Dtlb_Miss", "The number of data references that missed the TLB."},
++	{"ESP_Uops", "The number of ESP folding instructions decoded."},
++	{"EST_Trans", "Count the number of Intel Enhanced SpeedStep transitions."},
++	{"FP_Assist", "The number of floating point operations that required microcode assists.  The event is only available on PMC1."},
++	{"FP_Comp_Instr_Ret", "The number of X87 floating point compute instructions retired.  The event is only available on PMC0."},
++	{"FP_Comps_Op_Exe", "The number of floating point computational instructions executed."},
++	{"FP_MMX_Trans", "The number of transitions from X87 to MMX."},
++	{"Fused_Ld_Uops_Ret", "The number of fused load uops retired."},
++	{"Fused_St_Uops_Ret", "The number of fused store uops retired."},
++	{"Fused_Uops_Ret", "The number of fused uops retired."},
++	{"HW_Int_Rx", "The number of hardware interrupts received."},
++	{"ICache_Misses", "The number of instruction fetch misses in the instruction cache and streaming buffers."},
++	{"ICache_Reads", "The number of instruction fetches from the the instruction cache and streaming buffers counting both cacheable and uncacheable fetches."},
++	{"IFU_Mem_Stall", "The number of cycles the instruction fetch unit was stalled while waiting for data from memory."},
++	{"ILD_Stall", "The number of instruction length decoder stalls."},
++	{"ITLB_Misses", "The number of instruction TLB misses."},
++	{"Instr_Decoded", "The number of instructions decoded."},
++	{"Instr_Ret", "The number of instructions retired. This is an architectural performance event."},
++	{"L1_Pref_Req", "The number of L1 prefetch request due to data cache misses."},
++	{"L2_ADS", "The number of L2 address strobes."},
++	{"L2_IFetch", "The number of instruction fetches by the instruction fetch unit from L2 cache including speculative fetches."},
++	{"L2_LD", "The number of L2 cache reads."},
++	{"L2_Lines_In", "The number of L2 cache lines allocated."},
++	{"L2_Lines_Out", "The number of L2 cache lines evicted."},
++	{"L2_M_Lines_In", "The number of L2 M state cache lines allocated."},
++	{"L2_M_Lines_Out", "The number of L2 M state cache lines evicted."},
++	{"L2_No_Request_Cycles", "The number of cycles there was no request to access L2 cache."},
++	{"L2_Reject_Cycles", "The number of cycles the L2 cache was busy and rejecting new requests."},
++	{"L2_Rqsts", "The number of L2 cache requests."},
++	{"L2_ST", "The number of L2 cache writes including speculative writes."},
++	{"LD_Blocks", "The number of load operations delayed due to store buffer blocks."},
++	{"LLC_Misses", "The number of cache misses for references to the last level cache, excluding misses due to hardware prefetches. This is an architectural performance event."},
++	{"LLC_Reference", "The number of references to the last level cache, excluding those due to hardware prefetches. This is an architectural performance event."},
++	{"MMX_Assist", "The number of EMMX instructions executed."},
++	{"MMX_FP_Trans", "The number of transitions from MMX to X87."},
++	{"MMX_Instr_Exec", "The number of MMX instructions executed excluding MOVQ and MOVD stores."},
++	{"MMX_Instr_Ret", "The number of MMX instructions retired."},
++	{"Misalign_Mem_Ref", "The number of misaligned data memory references, counting loads and stores."},
++	{"Mul", "The number of multiply operations include speculative floating point and integer multiplies. This event is available on PMC1 only."},
++	{"NonHlt_Ref_Cycles", "The number of non-halted bus cycles. This is an architectural performance event."},
++	{"Pref_Rqsts_Dn", "The number of hardware prefetch requests issued in backward streams."},
++	{"Pref_Rqsts_Up", "The number of hardware prefetch requests issued in forward streams."},
++	{"Resource_Stall", "The number of cycles where there is a resource related stall."},
++	{"SD_Drains", "The number of cycles while draining store buffers."},
++	{"SIMD_FP_DP_P_Ret", "The number of SSE/SSE2 packed double precision instructions retired."},
++	{"SIMD_FP_DP_P_Comp_Ret", "The number of SSE/SSE2 packed double precision compute instructions retired."},
++	{"SIMD_FP_DP_S_Ret", "The number of SSE/SSE2 scalar double precision instructions retired."},
++	{"SIMD_FP_DP_S_Comp_Ret", "The number of SSE/SSE2 scalar double precision compute instructions retired."},
++	{"SIMD_FP_SP_P_Comp_Ret", "The number of SSE/SSE2 packed single precision compute instructions retired."},
++	{"SIMD_FP_SP_Ret", "The number of SSE/SSE2 scalar single precision instructions retired, both packed and scalar."},
++	{"SIMD_FP_SP_S_Ret", "The number of SSE/SSE2 scalar single precision instructions retired."},
++	{"SIMD_FP_SP_S_Comp_Ret", "The number of SSE/SSE2 single precision compute instructions retired."},
++	{"SIMD_Int_128_Ret", "The number of SSE2 128-bit integer instructions retired."},
++	{"SIMD_Int_Pari_Exec", "The number of SIMD integer packed arithmetic instructions executed."},
++	{"SIMD_Int_Pck_Exec", "The number of SIMD integer pack operations instructions executed."},
++	{"SIMD_Int_Plog_Exec", "The number of SIMD integer packed logical instructions executed."},
++	{"SIMD_Int_Pmul_Exec", "The number of SIMD integer packed multiply instructions executed."},
++	{"SIMD_Int_Psft_Exec", "The number of SIMD integer packed shift instructions executed."},
++	{"SIMD_Int_Sat_Exec", "The number of SIMD integer saturating instructions executed."},
++	{"SIMD_Int_Upck_Exec", "The number of SIMD integer unpack instructions executed."},
++	{"SMC_Detected", "The number of times self-modifying code was detected."},
++	{"SSE_NTStores_Miss", "The number of times an SSE streaming store instruction missed all caches."},
++	{"SSE_NTStores_Ret", "The number of SSE streaming store instructions executed."},
++	{"SSE_PrefNta_Miss", "The number of times PREFETCHNTA missed all caches."},
++	{"SSE_PrefNta_Ret", "The number of PREFETCHNTA instructions retired."},
++	{"SSE_PrefT1_Miss", "The number of times PREFETCHT1 missed all caches."},
++	{"SSE_PrefT1_Ret", "The number of PREFETCHT1 instructions retired."},
++	{"SSE_PrefT2_Miss", "The number of times PREFETCHNT2 missed all caches."},
++	{"SSE_PrefT2_Ret", "The number of PREFETCHT2 instructions retired."},
++	{"Seg_Reg_Loads", "The number of segment register loads."},
++	{"Serial_Execution_Cycles", "The number of non-halted bus cycles of this code while the other core was halted."},
++	{"Thermal_Trip", "The duration in a thermal trip based on the current core clock."},
++	{"Unfusion", "The number of unfusion events."},
++	{"Unhalted_Core_Cycles", "The number of core clock cycles when the clock signal on a specific core is not halted. This is an architectural performance event."},
++	{"Uops_Ret", "The number of micro-ops retired."},
++	{ NULL, NULL }
++};
++
++/* PAPI PRESETS */
++hwi_search_t CoreProcessor_map[] = {
++	{0, {0, {PAPI_NULL}, {0,}}}
++};
diff --git a/devel/papi/files/patch-freebsd__map-core.h b/devel/papi/files/patch-freebsd__map-core.h
new file mode 100644
index 000000000000..2fe65a710ed5
--- /dev/null
+++ b/devel/papi/files/patch-freebsd__map-core.h
@@ -0,0 +1,158 @@
+--- ./freebsd/map-core.h.orig	2009-07-15 12:05:10.665729000 -0400
++++ ./freebsd/map-core.h	2009-07-15 12:05:10.668717000 -0400
+@@ -0,0 +1,155 @@
++/****************************/
++/* THIS IS OPEN SOURCE CODE */
++/****************************/
++
++/* 
++* File:    map-core.h
++* CVS:     $Id: map-core.h,v 1.2 2009/07/09 13:02:26 servat Exp $
++* Author:  Harald Servat
++*          redcrash@gmail.com
++*/
++
++#ifndef FreeBSD_MAP_CORE
++#define FreeBSD_MAP_CORE
++
++enum NativeEvent_Value_CoreProcessor {
++	PNE_CORE_BACLEARS,
++	PNE_CORE_BTB_MISSES,
++	PNE_CORE_BR_BAC_MISSP_EXEC,
++	PNE_CORE_BR_BOGUS,
++	PNE_CORE_BR_CALL_EXEC,
++	PNE_CORE_BR_CALL_MISSP_EXEC,
++	PNE_CORE_BR_CND_EXEC,
++	PNE_CORE_BR_CND_MISSP_EXEC,
++	PNE_CORE_BR_IND_CALL_EXEC,
++	PNE_CORE_BR_IND_EXEC,
++	PNE_CORE_BR_IND_MISSP_EXEC,
++	PNE_CORE_BR_INST_EXEC,
++	PNE_CORE_BR_INSTR_DECODED,
++	PNE_CORE_BR_INSTR_RET,
++	PNE_CORE_BR_MISPRED_RET,
++	PNE_CORE_BR_MISPRED_TAKEN_RET,
++	PNE_CORE_BR_MISSP_EXEC,
++	PNE_CORE_BR_RET_BAC_MISSP_EXEC,
++	PNE_CORE_BR_RET_EXEC,
++	PNE_CORE_BR_RET_MISSP_EXEC,
++	PNE_CORE_BR_TAKEN_RET,
++	PNE_CORE_BUS_BNR_CLOCKS,
++	PNE_CORE_BUS_DRDY_CLOCKS,
++	PNE_CORE_BUS_DATA_RCV,
++	PNE_CORE_BUS_LOCKS_CLOCKS,
++	PNE_CORE_BUS_NOT_IN_USE,
++	PNE_CORE_BUS_REQ_OUTSTANDING,
++	PNE_CORE_BUS_SNOOP_STALL,
++	PNE_CORE_BUS_SNOOPS,
++	PNE_CORE_BUS_TRANS_ANY,
++	PNE_CORE_BUS_TRANS_BRD,
++	PNE_CORE_BUS_TRANS_BURST,
++	PNE_CORE_BUS_TRANS_DEF,
++	PNE_CORE_BUS_TRANS_IO,
++	PNE_CORE_BUS_TRANS_IFETCH,
++	PNE_CORE_BUS_TRANS_INVAL,
++	PNE_CORE_BUS_TRANS_MEM,
++	PNE_CORE_BUS_TRANS_P,
++	PNE_CORE_BUS_TRANS_PWR,
++	PNE_CORE_BUS_TRANS_RFO,
++	PNE_CORE_BUS_TRANS_WB,
++	PNE_CORE_CYCLES_DIV_BUSY,
++	PNE_CORE_CYCLES_INT_MASKED,
++	PNE_CORE_CYCLES_INT_PENDING_MASKED,
++	PNE_CORE_DCU_SNOOP_TO_SHARE,
++	PNE_CORE_DCACHE_CACHE_LOCK,
++	PNE_CORE_DCACHE_CACHE_LD,
++	PNE_CORE_DCACHE_CACHE_ST,
++	PNE_CORE_DCACHE_M_EVICT,
++	PNE_CORE_DCACHE_M_REPL,
++	PNE_CORE_DCACHE_PEND_MISS,
++	PNE_CORE_DCACHE_REPL,
++	PNE_CORE_DATA_MEM_CACHE_REF,
++	PNE_CORE_DATA_MEM_REF,
++	PNE_CORE_DBUS_BUSY,
++	PNE_CORE_DBUS_BUSY_RD,
++	PNE_CORE_DIV,
++	PNE_CORE_DTLB_MISS,
++	PNE_CORE_ESP_UOPS,
++	PNE_CORE_EST_TRANS,
++	PNE_CORE_FP_ASSIST,
++	PNE_CORE_FP_COMP_INSTR_RET,
++	PNE_CORE_FP_COMPS_OP_EXE,
++	PNE_CORE_FP_MMX_TRANS,
++	PNE_CORE_FUSED_LD_UOPS_RET,
++	PNE_CORE_FUSED_ST_UOPS_RET,
++	PNE_CORE_FUSED_UOPS_RET,
++	PNE_CORE_HW_INT_RX,
++	PNE_CORE_ICACHE_MISSES,
++	PNE_CORE_ICACHE_READS,
++	PNE_CORE_IFU_MEM_STALL,
++	PNE_CORE_ILD_STALL,
++	PNE_CORE_ITLB_MISSES,
++	PNE_CORE_INSTR_DECODED,
++	PNE_CORE_INSTR_RET,
++	PNE_CORE_L1_PREF_REQ,
++	PNE_CORE_L2_ADS,
++	PNE_CORE_L2_IFETCH,
++	PNE_CORE_L2_LD,
++	PNE_CORE_L2_LINES_IN,
++	PNE_CORE_L2_LINES_OUT,
++	PNE_CORE_L2_M_LINES_IN,
++	PNE_CORE_L2_M_LINES_OUT,
++	PNE_CORE_L2_NO_REQUEST_CYCLES,
++	PNE_CORE_L2_REJECT_CYCLES,
++	PNE_CORE_L2_RQSTS,
++	PNE_CORE_L2_ST,
++	PNE_CORE_LD_BLOCKS,
++	PNE_CORE_LLC_MISSES,
++	PNE_CORE_LLC_REFERENCE,
++	PNE_CORE_MMX_ASSIST,
++	PNE_CORE_MMX_FP_TRANS,
++	PNE_CORE_MMX_INSTR_EXEC,
++	PNE_CORE_MMX_INSTR_RET,
++	PNE_CORE_MISALIGN_MEM_REF,
++	PNE_CORE_MUL,
++	PNE_CORE_NONHLT_REF_CYCLES,
++	PNE_CORE_PREF_RQSTS_DN,
++	PNE_CORE_PREF_RQSTS_UP,
++	PNE_CORE_RESOURCE_STALL,
++	PNE_CORE_SD_DRAINS,
++	PNE_CORE_SIMD_FP_DP_P_RET,
++	PNE_CORE_SIMD_FP_DP_P_COMP_RET,
++	PNE_CORE_SIMD_FP_DP_S_RET,
++	PNE_CORE_SIMD_FP_DP_S_COMP_RET,
++	PNE_CORE_SIMD_FP_SP_P_COMP_RET,
++	PNE_CORE_SIMD_FP_SP_RET,
++	PNE_CORE_SIMD_FP_SP_S_RET,
++	PNE_CORE_SIMD_FP_SP_S_COMP_RET,
++	PNE_CORE_SIMD_INT_128_RET,
++	PNE_CORE_SIMD_INT_PARI_EXEC,
++	PNE_CORE_SIMD_INT_PCK_EXEC,
++	PNE_CORE_SIMD_INT_PLOG_EXEC,
++	PNE_CORE_SIMD_INT_PMUL_EXEC,
++	PNE_CORE_SIMD_INT_PSFT_EXEC,
++	PNE_CORE_SIMD_INT_SAT_EXEC,
++	PNE_CORE_SIMD_INT_UPCK_EXEC,
++	PNE_CORE_SMC_DETECTED,
++	PNE_CORE_SSE_NTSTORES_MISS,
++	PNE_CORE_SSE_NTSTORES_RET,
++	PNE_CORE_SSE_PREFNTA_MISS,
++	PNE_CORE_SSE_PREFNTA_RET,
++	PNE_CORE_SSE_PREFT1_MISS,
++	PNE_CORE_SSE_PREFT1_RET,
++	PNE_CORE_SSE_PREFT2_MISS,
++	PNE_CORE_SSE_PREFT2_RET,
++	PNE_CORE_SEG_REG_LOADS,
++	PNE_CORE_SERIAL_EXECUTION_CYCLES,
++	PNE_CORE_THERMAL_TRIP,
++	PNE_CORE_UNFUSION,
++	PNE_CORE_UNHALTED_CORE_CYCLES,
++	PNE_CORE_UOPS_RET,
++	PNE_CORE_NATNAME_GUARD
++};
++
++extern Native_Event_LabelDescription_t CoreProcessor_info[];
++extern hwi_search_t CoreProcessor_map[];
++
++#endif
++
diff --git a/devel/papi/files/patch-freebsd__map-core2-extreme.c b/devel/papi/files/patch-freebsd__map-core2-extreme.c
new file mode 100644
index 000000000000..174ee470bac1
--- /dev/null
+++ b/devel/papi/files/patch-freebsd__map-core2-extreme.c
@@ -0,0 +1,279 @@
+--- ./freebsd/map-core2-extreme.c.orig	2009-07-15 12:05:10.681724000 -0400
++++ ./freebsd/map-core2-extreme.c	2009-07-15 12:05:10.684723000 -0400
+@@ -0,0 +1,276 @@
++/****************************/
++/* THIS IS OPEN SOURCE CODE */
++/****************************/
++
++/* 
++* File:    map-core2-extreme.c
++* CVS:     $Id: map-core2-extreme.c,v 1.3 2009/07/09 13:02:26 servat Exp $
++* Author:  George Neville-Neil
++*          gnn@freebsd.org
++*          Harald Servat
++*          redcrash@gmail.com
++*/
++
++#include SUBSTRATE
++#include "papiStdEventDefs.h"
++#include "map.h"
++
++
++/****************************************************************************
++ CORE2_EXTREME SUBSTRATE 
++ CORE2_EXTREME SUBSTRATE 
++ CORE2_EXTREME SUBSTRATE
++ CORE2_EXTREME SUBSTRATE
++ CORE2_EXTREME SUBSTRATE
++****************************************************************************/
++
++/*
++	NativeEvent_Value_Core2ExtremeProcessor must match Core2ExtremeProcessor_info 
++*/
++
++Native_Event_LabelDescription_t Core2ExtremeProcessor_info[] =
++{
++	{"BACLEARS", "The number of times the front end is resteered."},
++	{"BOGUS_BR", "The number of byte sequences mistakenly detected as taken branch instructions."},
++	{"BR_BAC_MISSP_EXEC", "The number of branch instructions that were mispredicted when decoded."},
++	{"BR_CALL_MISSP_EXEC", "The number of mispredicted CALL instructions that were executed."},
++	{"BR_CALL_EXEC", "The number of CALL instructions executed."},
++	{"BR_CND_EXEC", "The number of conditional branches executed, but not necessarily retired."},
++	{"BR_CND_MISSP_EXEC", "The number of mispredicted conditional branches executed."},
++	{"BR_IND_CALL_EXEC", "The number of indirect CALL instructions executed."},
++	{"BR_IND_EXEC", "The number of indirect branch instructions executed."},
++	{"BR_IND_MISSP_EXEC", "The number of mispredicted indirect branch instructions executed."},
++	{"BR_INST_DECODED", "The number of branch instructions decoded."},
++	{"BR_INST_EXEC", "The number of branches executed, but not necessarily retired."},
++	{"BR_INST_RETIRED.ANY", "The number of branch instructions retired.  This is an architectural performance event."},
++	{"BR_INST_RETIRED.MISPRED", "The number of mispredicted branch instructions retired.  This is an architectural performance event."},
++	{"BR_INST_RETIRED.MISPRED_NOT_TAKEN", "The number of not taken branch instructions retired that were mispredicted."},
++	{"BR_INST_RETIRED.MISPRED_TAKEN", "The number taken branch instructions retired that were mispredicted."},
++	{"BR_INST_RETIRED.PRED_NOT_TAKEN", "The number of not taken branch instructions retired that were correctly predicted."},
++	{"BR_INST_RETIRED.PRED_TAKEN", "The number of taken branch instructions retired that were correctly predicted."},
++	{"BR_INST_RETIRED.TAKEN", "The number of taken branch instructions retired."},
++	{"BR_MISSP_EXEC", "The number of mispredicted branch instructions that were executed."},
++	{"BR_RET_MISSP_EXEC", "The number of mispredicted RET instructions executed."},
++	{"BR_RET_BAC_MISSP_EXEC", "The number of RET instructions executed that were mispredicted at decode time."},
++	{"BR_RET_EXEC", "The number of RET instructions executed."},
++	{"BR_TKN_BUBBLE_1", "The number of branch predicted taken with bubble 1."},
++	{"BR_TKN_BUBBLE_2", "The number of branch predicted taken with bubble 2."},
++	{"BUSQ_EMPTY", "The number of cycles during which the core did not have any pending transactions in the bus queue."},
++	{"BUS_BNR_DRV", "Number of Bus Not Ready signals asserted on the bus."},
++	{"BUS_DATA_RCV", "Number of bus cycles during which the processor is receiving data."},
++	{"BUS_DRDY_CLOCKS", "The number of bus cycles during which the Data Ready signal is asserted on the bus."},
++	{"BUS_HIT_DRV", "The number of bus cycles during which the processor drives the HIT# pin."},
++	{"BUS_HITM_DRV", "The number of bus cycles during which the processor drives the HITM# pin."},
++	{"BUS_IO_WAIT", "The number of core cycles during which I/O requests wait in the bus queue."},
++	{"BUS_LOCK_CLOCKS", "The number of bus cycles during which the LOCK signal was asserted on the bus."},
++	{"BUS_REQUEST_OUTSTANDING", "The number of pending full cache line read transactions on the bus occuring in each cycle."},
++	{"BUS_TRANS_ANY", "The number of bus transactions of any kind."},
++	{"BUS_TRANS_BRD", "The number of burst read transactions."},
++	{"BUS_TRANS_BURST", "The number of burst transactions."},
++	{"BUS_TRANS_DEF", "The number of deferred bus transactions."},
++	{"BUS_TRANS_IFETCH", "The number of instruction fetch full cache line bus transactions."},
++	{"BUS_TRANS_INVAL", "The number of invalidate bus transactions."},
++	{"BUS_TRANS_IO", "The number of completed I/O bus transaactions due to IN and OUT instructions."},
++	{"BUS_TRANS_MEM", "The number of memory bus transactions."},
++	{"BUS_TRANS_P", "The number of partial bus transactions."},
++	{"BUS_TRANS_PWR", "The number of partial write bus transactions."},
++	{"BUS_TRANS_RFO", "The number of Read For Ownership bus transactions."},
++	{"BUS_TRANS_WB", "The number of explicit writeback bus transactions due to dirty line evictions."},
++	{"CMP_SNOOP", "The number of times the L1 data cache is snooped by the other core in the same processor."},
++	{"CPU_CLK_UNHALTED.BUS", "The number of bus cycles when the core is not in the halt state. This is an architectural performance event."},
++	{"CPU_CLK_UNHALTED.CORE_P", "The number of core cycles while the core is not in a halt state.  This is an architectural performance event."},
++	{"CPU_CLK_UNHALTED.NO_OTHER", "The number of bus cycles during which the core remains unhalted and the other core is halted."},
++	{"CYCLES_DIV_BUSY", "The number of cycles the divider is busy.  This event is only available on PMC0."},
++	{"CYCLES_INT_MASKED", "The number of cycles during which interrupts are disabled."},
++	{"CYCLES_INT_PENDING_AND_MASKED", "The number of cycles during which there were pending interrupts while interrupts were disabled."},
++	{"CYCLES_L1I_MEM_STALLED", "The number of cycles for which an instruction fetch stalls."},
++	{"DELAYED_BYPASS.FP", "The number of floating point operations that used data immediately after the data was generated by a non floating point execution unit."},
++	{"DELAYED_BYPASS.LOAD", "The number of delayed bypass penalty cycles that a load operation incurred."},
++	{"DELAYED_BYPASS.SIMD", "The number of times SIMD operations use data immediately after data, was generated by a non-SIMD execution unit."},
++	{"DIV", "The number of divide operations executed."},
++	{"DTLB_MISSES.ANY", "The number of Data TLB misses, including misses that result from speculative accesses."},
++	{"DTLB_MISSES.L0_MISS_LD", "The number of level 0 DTLB misses due to load operations."},
++	{"DTLB_MISSES.MISS_LD", "The number of Data TLB misses due to load operations."},
++	{"DTLB_MISSES.MISS_ST", "The number of Data TLB misses due to store operations."},
++	{"EIST_TRANS", "The number of Enhanced Intel SpeedStep Technology transitions."},
++	{"ESP.ADDITIONS", "The number of automatic additions to the esp register."},
++	{"ESP.SYNCH", "The number of times the esp register was explicitly used in an address expression after it is implicitly used by a PUSH or POP instruction."},
++	{"EXT_SNOOP", "The number of snoop responses to bus transactions."},
++	{"FP_ASSIST", "The number of floating point operations executed that needed a microcode assist."},
++	{"FP_COMP_OPS_EXE", "The number of floating point computational micro-ops executed.  The event is available only on PMC0."},
++	{"FP_MMX_TRANS_TO_FP", "The number of transitions from MMX instructions to floating point instructions."},
++	{"FP_MMX_TRANS_TO_MMX", "The number of transitions from floating point instructions to MMX instructions."},
++	{"HW_INT_RCV", "The number of hardware interrupts recieved."},
++	{"IDLE_DURING_DIV", "The number of cycles the divider is busy and no other execution unit or load operation was in progress.  This event is available only on PMC0."},
++	{"ILD_STALL", "The number of cycles the instruction length decoder stalled due to a length changing prefix."},
++	{"INST_QUEUE.FULL", "The number of cycles during which the instruction queue is full."},
++	{"INST_RETIRED.ANY_P", "The number of instructions retired.  This is an architectural performance event."},
++	{"INST_RETIRED.LOADS", "The number of instructions retired that contained a load operation."},
++	{"INST_RETIRED.OTHER", "The number of instructions retired that did not contain a load or a store operation."},
++	{"INST_RETIRED.STORES", "The number of instructions retired that contained a store operation."},
++	{"INST_RETIRED.VM_H", "The number of instructions retired while in VMX root operation."},
++	{"ITLB.FLUSH", "The number of ITLB flushes."},
++	{"ITLB.LARGE_MISS", "The number of instruction fetches from large pages that miss the ITLB."},
++	{"ITLB.MISSES", "The number of instruction fetches from both large and small pages that miss the ITLB."},
++	{"ITLB.SMALL_MISS", "The number of instruction fetches from small pages that miss the ITLB."},
++	{"ITLB_MISS_RETIRED", "The number of retired instructions that missed the ITLB when they were fetched."},
++	{"L1D_ALL_CACHE_REF", "The number of data reads and writes to cacheable memory."},
++	{"L1D_ALL_REF", "The number of references to L1 data cache counting loads and stores of to all memory types."},
++	{"L1D_CACHE_LD", "Number of data reads from cacheable memory excluding locked reads."},
++	{"L1D_CACHE_LOCK", "Number of locked reads from cacheable memory."},
++	{"L1D_CACHE_LOCK_DURATION", "The number of cycles during which any cache line is locked by any locking instruction."},
++	{"L1D_CACHE_ST", "The number of data writes to cacheable memory excluding locked writes."},
++	{"L1D_M_EVICT", "The number of modified cache lines evicted from L1 data cache."},
++	{"L1D_M_REPL", "The number of modified lines allocated in L1 data cache."},
++	{"L1D_PEND_MISS", "The total number of outstanding L1 data cache misses at any clock."},
++	{"L1D_PREFETCH.REQUESTS", "The number of times L1 data cache requested to prefetch a data cache line."},
++	{"L1D_REPL", "The number of lines brought into L1 data cache."},
++	{"L1D_SPLIT.LOADS", "The number of load operations that span two cache lines."},
++	{"L1D_SPLIT.STORES", "The number of store operations that span two cache lines."},
++	{"L1I_MISSES", "The number of instruction fetch unit misses."},
++	{"L1I_READS", "The number of instruction fetches."},
++	{"L2_ADS", "The number of cycles that the L2 address bus is in use."},
++	{"L2_DBUS_BUSY_RD", "The number of cycles during which the L2 data bus is busy transferring data to the core."},
++	{"L2_IFETCH", "The number of instruction cache line requests from the instruction fetch unit."},
++	{"L2_LD", "The number of L2 cache read requests from L1 cache and L2 prefetchers."},
++	{"L2_LINES_IN", "The number of cache lines allocated in L2 cache."},
++	{"L2_LINES_OUT", "The number of L2 cache lines evicted."},
++	{"L2_LOCK", "The number of locked accesses to cache lines that miss L1 data cache."},
++	{"L2_M_LINES_IN", "The number of L2 cache line modifications."},
++	{"L2_M_LINES_OUT", "The number of modified lines evicted from L2 cache."},
++	{"L2_NO_REQ", "Number of cycles during which no L2 cache requests were pending from a core."},
++	{"L2_REJECT_BUSQ", "Number of L2 cache requests that were rejected."},
++	{"L2_RQSTS", "The number of completed L2 cache requests."},
++	{"L2_RQSTS.SELF.DEMAND.I_STATE", "The number of completed L2 cache demand requests from this core that missed the L2 cache.  This is an architectural performance event."},
++	{"L2_RQSTS.SELF.DEMAND.MESI", "The number of completed L2 cache demand requests from this core.  This is an architectural performance event."},
++	{"L2_ST", "The number of store operations that miss the L1 cache and request data from the L2 cache."},
++	{"LOAD_BLOCK.L1D", "The number of loads blocked by the L1 data cache."},
++	{"LOAD_BLOCK.OVERLAP_STORE", "The number of loads that partially overlap an earlier store or are aliased with a previous store."},
++	{"LOAD_BLOCK.STA", "The number of loads blocked by preceding stores whose address is yet to be calculated."},
++	{"LOAD_BLOCK.STD", "The number of loads blocked by preceding stores to the same address whose data value is not known."},
++	{"LOAD_BLOCK.UNTIL_RETIRE", "The numer of load operations that were blocked until retirement."},
++	{"LOAD_HIT_PRE", "The number of load operations that conflicted with an prefetch to the same cache line."},
++	{"MACHINE_NUKES.MEM_ORDER", "The number of times the execution pipeline was restarted due to a memory ordering conflict or memory disambiguation misprediction."},
++	{"MACHINE_NUKES.SMC", "The number of times a program writes to a code section."},
++	{"MACRO_INSTS.CISC_DECODED", "The number of complex instructions decoded."},
++	{"MACRO_INSTS.DECODED", "The number of instructions decoded."},
++	{"MEMORY_DISAMBIGUATION.RESET", "The number of cycles during which memory disambiguation misprediction occurs."},
++	{"MEMORY_DISAMBIGUATION.SUCCESS", "The number of load operations that were successfully disambiguated."},
++	{"MEM_LOAD_RETIRED.DTLB_MISS", "The number of retired loads that missed the DTLB."},
++	{"MEM_LOAD_RETIRED.L1D_LINE_MISS", "The number of retired load operations that missed L1 data cache and that sent a request to L2 cache. This event is only available on PMC0."},
++	{"MEM_LOAD_RETIRED.L1D_MISS", "The number of retired load operations that missed L1 data cache.  This event is only available on PMC0."},
++	{"MEM_LOAD_RETIRED.L2_LINE_MISS", "The number of load operations that missed L2 cache and that caused a bus request."},
++	{"MEM_LOAD_RETIRED.L2_MISS", "The number of load operations that missed L2 cache."},
++	{"MUL","The number of multiply operations executed (only available on PMC1.)"},
++	{"PAGE_WALKS.COUNT", "The number of page walks executed due to an ITLB or DTLB miss."},
++	{"PAGE_WALKS.CYCLES", "The number of cycles spent in a page walk caused by an ITLB or DTLB miss."},
++	{"PREF_RQSTS_DN", "The number of downward prefetches issued from the Data Prefetch Logic unit to L2 cache."},
++	{"PREF_RQSTS_UP", "The number of upward prefetches issued from the Data Prefetch Logic unit to L2 cache."},
++	{"RAT_STALLS.ANY", "The number of stall cycles due to any of RAT_STALLS.FLAGS RAT_STALLS.FPSW, RAT_STALLS.PARTIAL and RAT_STALLS.ROB_READ_PORT."},
++	{"RAT_STALLS.FLAGS", "The number of cycles execution stalled due to a flag register induced stall."},
++	{"RAT_STALLS.FPSW", "The number of times the floating point status word was written."},
++	{"RAT_STALLS.OTHER_SERIALIZATION_STALLS", "The number of stalls due to other RAT resource serialization not counted by umask 0FH."},
++	{"RAT_STALLS.PARTIAL_CYCLES", "The number of cycles of added instruction execution latency due to the use of a register that was partially written by previous instructions."},
++	{"RAT_STALLS.ROB_READ_PORT", "The number of cycles when ROB read port stalls occurred."},
++	{"RESOURCE_STALLS.ANY", "The number of cycles during which any resource related stall occurred."},
++	{"RESOURCE_STALLS.BR_MISS_CLEAR", "The number of cycles stalled due to branch misprediction."},
++	{"RESOURCE_STALLS.FPCW", "The number of cycles stalled due to writing the floating point control word."},
++	{"RESOURCE_STALLS.LD_ST", "The number of cycles during which the number of loads and stores in the pipeline exceeded their limits."},
++	{"RESOURCE_STALLS.ROB_FULL", "The number of cycles when the reorder buffer was full."},
++	{"RESOURCE_STALLS.RS_FULL", "The number of cycles during which the RS was full."},
++	{"RS_UOPS_DISPATCHED", "The number of micro-ops dispatched for execution."},
++	{"RS_UOPS_DISPATCHED.PORT0", "The number of cycles micro-ops were dispatched for execution on port 0."},
++	{"RS_UOPS_DISPATCHED.PORT1", "The number of cycles micro-ops were dispatched for execution on port 1."},
++	{"RS_UOPS_DISPATCHED.PORT2", "The number of cycles micro-ops were dispatched for execution on port 2."},
++	{"RS_UOPS_DISPATCHED.PORT3", "The number of cycles micro-ops were dispatched for execution on port 3."},
++	{"RS_UOPS_DISPATCHED.PORT4", "The number of cycles micro-ops were dispatched for execution on port 4."},
++	{"RS_UOPS_DISPATCHED.PORT5", "The number of cycles micro-ops were dispatched for execution on port 5."},
++	{"SB_DRAIN_CYCLES", "The number of cycles while the store buffer is draining."},
++	{"SEGMENT_REG_LOADS", "The number of segment register loads."},
++	{"SEG_REG_RENAMES.ANY", "The number of times the any segment register was renamed."},
++	{"SEG_REG_RENAMES.DS", "The number of times the ds register is renamed."},
++	{"SEG_REG_RENAMES.ES", "The number of times the es register is renamed."},
++	{"SEG_REG_RENAMES.FS", "The number of times the fs register is renamed."},
++	{"SEG_REG_RENAMES.GS", "The number of times the gs register is renamed."},
++	{"SEG_RENAME_STALLS.ANY", "The number of stalls due to lack of resource to rename any segment register."},
++	{"SEG_RENAME_STALLS.DS", "The number of stalls due to lack of renaming resources for the ds register."},
++	{"SEG_RENAME_STALLS.ES", "The number of stalls due to lack of renaming resources for the es register."},
++	{"SEG_RENAME_STALLS.FS", "The number of stalls due to lack of renaming resources for the fs register."},
++	{"SEG_RENAME_STALLS.GS", "The number of stalls due to lack of renaming resources for the gs register."},
++	{"SIMD_ASSIST", "The number SIMD assists invoked."},
++	{"SIMD_COMP_INST_RETIRED.PACKED_DOUBLE", "Then number of computational SSE2 packed double precision instructions retired."},
++	{"SIMD_COMP_INST_RETIRED.PACKED_SINGLE", "Then number of computational SSE2 packed single precision instructions retired."},
++	{"SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE", "Then number of computational SSE2 scalar double precision instructions retired."},
++	{"SIMD_COMP_INST_RETIRED.SCALAR_SINGLE", "Then number of computational SSE2 scalar single precision instructions retired."},
++	{"SIMD_INSTR_RETIRED", "The number of retired SIMD instructions that use MMX registers."},
++	{"SIMD_INST_RETIRED.ANY", "The number of streaming SIMD instructions retired."},
++	{"SIMD_INST_RETIRED.PACKED_DOUBLE", "The number of SSE2 packed double precision instructions retired."},
++	{"SIMD_INST_RETIRED.PACKED_SINGLE", "The number of SSE packed single precision instructions retired."},
++	{"SIMD_INST_RETIRED.SCALAR_DOUBLE", "The number of SSE2 scalar double precision instructions retired."},
++	{"SIMD_INST_RETIRED.SCALAR_SINGLE", "The number of SSE scalar single precision instructions retired."},
++	{"SIMD_INST_RETIRED.VECTOR", "The number of SSE2 vector instructions retired."},
++	{"SIMD_SAT_INSTR_RETIRED", "The number of saturated arithmetic SIMD instructions retired."},
++	{"SIMD_SAT_UOP_EXEC", "The number of SIMD saturated arithmetic micro-ops executed."},
++	{"SIMD_UOPS_EXEC", "The number of SIMD micro-ops executed."},
++	{"SIMD_UOP_TYPE_EXEC.ARITHMETIC", "The number of SIMD packed arithmetic micro-ops executed."},
++	{"SIMD_UOP_TYPE_EXEC.LOGICAL", "The number of SIMD packed logical micro-ops executed."},
++	{"SIMD_UOP_TYPE_EXEC.MUL", "The number of SIMD packed multiply micro-ops executed."},
++	{"SIMD_UOP_TYPE_EXEC.PACK", "The number of SIMD pack micro-ops executed."},
++	{"SIMD_UOP_TYPE_EXEC.SHIFT", "The number of SIMD packed shift micro-ops executed."},
++	{"SIMD_UOP_TYPE_EXEC.UNPACK", "The number of SIMD unpack micro-ops executed."},
++	{"SNOOP_STALL_DRV", "The number of times the bus stalled for snoops."},
++	{"SSE_PRE_EXEC.L1", "The number of PREFETCHT0 instructions executed."},
++	{"SSE_PRE_EXEC.L2", "The number of PREFETCHT1 instructions executed."},
++	{"SSE_PRE_EXEC.NTA", "The number of PREFETCHNTA instructions executed."},
++	{"SSE_PRE_EXEC.STORES", "The number of times SSE non-temporal store instructions were executed."},
++	{"SSE_PRE_MISS.L1", "The number of times the PREFETCHT0 instruction executed and missed all cache levels."},
++	{"SSE_PRE_MISS.L2", "The number of times the PREFETCHT1 instruction executed and missed all cache levels."},
++	{"SSE_PRE_MISS.NTA", "The number of times the PREFETCHNTA instruction executed and missed all cache levels."},
++	{"STORE_BLOCK.ORDER", "The number of cycles while a store was waiting for another store to be globally observed."},
++	{"STORE_BLOCK.SNOOP", "The number of cycles while a store was blocked due to a conflict with an internal or external snoop."},
++	{"THERMAL_TRIP", "The number of thermal trips."},
++	{"UOPS_RETIRED.ANY", "The number of micro-ops retired."},
++	{"UOPS_RETIRED.FUSED", "The number of fused micro-ops retired."},
++	{"UOPS_RETIRED.LD_IND_BR", "The number of micro-ops retired that fused a load with another operation."},
++	{"UOPS_RETIRED.MACRO_FUSION", "The number of times retired instruction pairs were fused into one micro-op."},
++	{"UOPS_RETIRED.NON_FUSED", "he number of non-fused micro-ops retired."},
++	{"UOPS_RETIRED.STD_STA", "The number of store address calculations that fused into one micro-op."},
++	{"X87_OPS_RETIRED.ANY", "The number of floating point computational instructions retired."},
++	{"X87_OPS_RETIRED.FXCH", "The number of FXCH instructions retired."},
++	{ NULL, NULL } 
++};
++
++/* PAPI PRESETS */
++hwi_search_t Core2ExtremeProcessor_map[] = {
++	{PAPI_BR_INS, {0, {PNE_CORE2EXTREME_BR_INST_RETIRED_ANY, PAPI_NULL}, {0,}}},
++	{PAPI_RES_STL, {0, {PNE_CORE2EXTREME_RESOURCE_STALLS_ANY, PAPI_NULL}, {0,}}},
++	{PAPI_TOT_CYC, {0, {PNE_CORE2EXTREME_CPU_CLK_UNHALTED_BUS, PAPI_NULL}, {0,}}},
++	{PAPI_TOT_INS, {0, {PNE_CORE2EXTREME_INST_RETIRED_ANY_P, PAPI_NULL}, {0,}}},
++	{PAPI_HW_INT, {0, {PNE_CORE2EXTREME_HW_INT_RCV, PAPI_NULL}, {0,}}},
++	{PAPI_BR_TKN, {0, {PNE_CORE2EXTREME_BR_INST_RETIRED_TAKEN, PAPI_NULL}, {0,}}},
++	{PAPI_BR_MSP, {0, {PNE_CORE2EXTREME_BR_MISSP_EXEC, PAPI_NULL}, {0,}}},
++	{PAPI_TLB_DM, {0, {PNE_CORE2EXTREME_DTLB_MISSES_ANY, PAPI_NULL}, {0,}}},
++	{PAPI_TLB_IM, {0, {PNE_CORE2EXTREME_ITLB_MISSES, PAPI_NULL}, {0,}}},
++#if HWPMC_NUM_COUNTERS >= 2
++	{PAPI_TLB_TL, {DERIVED_ADD, {PNE_CORE2EXTREME_DTLB_MISSES_ANY, PNE_CORE2EXTREME_ITLB_MISSES, PAPI_NULL},{0,}}},
++#endif
++	{PAPI_L1_DCA, {0, {PNE_CORE2EXTREME_L1D_ALL_REF, PAPI_NULL}, {0,}}},
++	{PAPI_L1_ICA, {0, {PNE_CORE2EXTREME_L1I_READS, PAPI_NULL}, {0,}}},
++#if HWPMC_NUM_COUNTERS >= 2
++	{PAPI_L1_TCA, {DERIVED_ADD, {PNE_CORE2EXTREME_L1D_ALL_REF, PNE_CORE2EXTREME_L1I_READS, PAPI_NULL}, {0,}}},
++#endif
++	/* PAPI_L2_ICH seems not to work
++	{PAPI_L2_ICH, {0, {PNE_CORE2EXTREME_L2_IFETCH, PAPI_NULL}, {0,}}},
++	*/
++	{PAPI_L2_DCH, {0, {PNE_CORE2EXTREME_L2_LD, PAPI_NULL}, {0,}}},
++	{PAPI_FP_INS, {0, {PNE_CORE2EXTREME_X87_OPS_RETIRED_ANY, PAPI_NULL}, {0,}}},
++	{PAPI_L1_DCM, {0, {PNE_CORE2EXTREME_MEM_LOAD_RETIRED_L1D_MISS, PAPI_NULL}, {0,}}},
++	{PAPI_L1_ICM, {0, {PNE_CORE2EXTREME_L1I_MISSES, PAPI_NULL}, {0,}}},
++#if HWPMC_NUM_COUNTERS >= 2
++	{PAPI_L1_TCM, {DERIVED_ADD, {PNE_CORE2EXTREME_MEM_LOAD_RETIRED_L1D_MISS, PNE_CORE2EXTREME_L1I_MISSES, PAPI_NULL}, {0,}}},
++#endif
++	{PAPI_L2_DCM, {0, {PNE_CORE2EXTREME_MEM_LOAD_RETIRED_L2_MISS, PAPI_NULL}, {0,}}},
++	{0, {0, {PAPI_NULL}, {0,}}}
++};
++
++
diff --git a/devel/papi/files/patch-freebsd__map-core2-extreme.h b/devel/papi/files/patch-freebsd__map-core2-extreme.h
new file mode 100644
index 000000000000..1496a3c29b07
--- /dev/null
+++ b/devel/papi/files/patch-freebsd__map-core2-extreme.h
@@ -0,0 +1,232 @@
+--- ./freebsd/map-core2-extreme.h.orig	2009-07-15 12:05:10.699715000 -0400
++++ ./freebsd/map-core2-extreme.h	2009-07-15 12:05:10.701743000 -0400
+@@ -0,0 +1,229 @@
++/****************************/
++/* THIS IS OPEN SOURCE CODE */
++/****************************/
++
++/* 
++* File:    map-core2.h
++* CVS:     $Id: map-core2-extreme.h,v 1.2 2009/07/09 13:02:26 servat Exp $
++* Author:  George Neville-Neil
++*          gnn@freebsd.org
++*/
++
++#ifndef FreeBSD_MAP_CORE2EXTREME_EXTREME
++#define FreeBSD_MAP_CORE2EXTREME_EXTREME
++
++enum NativeEvent_Value_Core2ExtremeProcessor {
++	PNE_CORE2EXTREME_BACLEARS = PAPI_NATIVE_MASK ,
++	PNE_CORE2EXTREME_BOGUS_BR,
++	PNE_CORE2EXTREME_BR_BAC_MISSP_EXEC,
++	PNE_CORE2EXTREME_BR_CALL_MISSP_EXEC,
++	PNE_CORE2EXTREME_BR_CALL_EXEC,
++	PNE_CORE2EXTREME_BR_CND_EXEC,
++	PNE_CORE2EXTREME_BR_CND_MISSP_EXEC,
++	PNE_CORE2EXTREME_BR_IND_CALL_EXEC,
++	PNE_CORE2EXTREME_BR_IND_EXEC,
++	PNE_CORE2EXTREME_BR_IND_MISSP_EXEC,
++	PNE_CORE2EXTREME_BR_INST_DECODED,
++	PNE_CORE2EXTREME_BR_INST_EXEC,
++	PNE_CORE2EXTREME_BR_INST_RETIRED_ANY,
++	PNE_CORE2EXTREME_BR_INST_RETIRED_MISPRED,
++	PNE_CORE2EXTREME_BR_INST_RETIRED_MISPRED_NOT_TAKEN,
++	PNE_CORE2EXTREME_BR_INST_RETIRED_MISPRED_TAKEN,
++	PNE_CORE2EXTREME_BR_INST_RETIRED_PRED_NOT_TAKEN,
++	PNE_CORE2EXTREME_BR_INST_RETIRED_PRED_TAKEN,
++	PNE_CORE2EXTREME_BR_INST_RETIRED_TAKEN,
++	PNE_CORE2EXTREME_BR_MISSP_EXEC,
++	PNE_CORE2EXTREME_BR_RET_MISSP_EXEC,
++	PNE_CORE2EXTREME_BR_RET_BAC_MISSP_EXEC,
++	PNE_CORE2EXTREME_BR_RET_EXEC,
++	PNE_CORE2EXTREME_BR_TKN_BUBBLE_1,
++	PNE_CORE2EXTREME_BR_TKN_BUBBLE_2,
++	PNE_CORE2EXTREME_BUSQ_EMPTY,
++	PNE_CORE2EXTREME_BUS_BNR_DRV,
++	PNE_CORE2EXTREME_BUS_DATA_RCV,
++	PNE_CORE2EXTREME_BUS_DRDY_CLOCKS,
++	PNE_CORE2EXTREME_BUS_HIT_DRV,
++	PNE_CORE2EXTREME_BUS_HITM_DRV,
++	PNE_CORE2EXTREME_BUS_IO_WAIT,
++	PNE_CORE2EXTREME_BUS_LOCK_CLOCKS,
++	PNE_CORE2EXTREME_BUS_REQUEST_OUTSTANDING,
++	PNE_CORE2EXTREME_BUS_TRANS_ANY,
++	PNE_CORE2EXTREME_BUS_TRANS_BRD,
++	PNE_CORE2EXTREME_BUS_TRANS_BURST,
++	PNE_CORE2EXTREME_BUS_TRANS_DEF,
++	PNE_CORE2EXTREME_BUS_TRANS_IFETCH,
++	PNE_CORE2EXTREME_BUS_TRANS_INVAL,
++	PNE_CORE2EXTREME_BUS_TRANS_IO,
++	PNE_CORE2EXTREME_BUS_TRANS_MEM,
++	PNE_CORE2EXTREME_BUS_TRANS_P,
++	PNE_CORE2EXTREME_BUS_TRANS_PWR,
++	PNE_CORE2EXTREME_BUS_TRANS_RFO,
++	PNE_CORE2EXTREME_BUS_TRANS_WB,
++	PNE_CORE2EXTREME_CMP_SNOOP,
++	PNE_CORE2EXTREME_CPU_CLK_UNHALTED_BUS,
++	PNE_CORE2EXTREME_CPU_CLK_UNHALTED_CORE_P,
++	PNE_CORE2EXTREME_CPU_CLK_UNHALTED_NO_OTHER,
++	PNE_CORE2EXTREME_CYCLES_DIV_BUSY,
++	PNE_CORE2EXTREME_CYCLES_INT_MASKED,
++	PNE_CORE2EXTREME_CYCLES_INT_PENDING_AND_MASKED,
++	PNE_CORE2EXTREME_CYCLES_L1I_MEM_STALLED,
++	PNE_CORE2EXTREME_DELAYED_BYPASS_FP,
++	PNE_CORE2EXTREME_DELAYED_BYPASS_LOAD,
++	PNE_CORE2EXTREME_DELAYED_BYPASS_SIMD,
++	PNE_CORE2EXTREME_DIV,
++	PNE_CORE2EXTREME_DTLB_MISSES_ANY,
++	PNE_CORE2EXTREME_DTLB_MISSES_L0_MISS_LD,
++	PNE_CORE2EXTREME_DTLB_MISSES_MISS_LD,
++	PNE_CORE2EXTREME_DTLB_MISSES_MISS_ST,
++	PNE_CORE2EXTREME_EIST_TRANS,
++	PNE_CORE2EXTREME_ESP_ADDITIONS,
++	PNE_CORE2EXTREME_ESP_SYNCH,
++	PNE_CORE2EXTREME_EXT_SNOOP,
++	PNE_CORE2EXTREME_FP_ASSIST,
++	PNE_CORE2EXTREME_FP_COMP_OPS_EXE,
++	PNE_CORE2EXTREME_FP_MMX_TRANS_TO_FP,
++	PNE_CORE2EXTREME_FP_MMX_TRANS_TO_MMX,
++	PNE_CORE2EXTREME_HW_INT_RCV,
++	PNE_CORE2EXTREME_IDLE_DURING_DIV,
++	PNE_CORE2EXTREME_ILD_STALL,
++	PNE_CORE2EXTREME_INST_QUEUE_FULL,
++	PNE_CORE2EXTREME_INST_RETIRED_ANY_P,
++	PNE_CORE2EXTREME_INST_RETIRED_LOADS,
++	PNE_CORE2EXTREME_INST_RETIRED_OTHER,
++	PNE_CORE2EXTREME_INST_RETIRED_STORES,
++	PNE_CORE2EXTREME_INST_RETIRED_VM_H,
++	PNE_CORE2EXTREME_ITLB_FLUSH,
++	PNE_CORE2EXTREME_ITLB_LARGE_MISS,
++	PNE_CORE2EXTREME_ITLB_MISSES,
++	PNE_CORE2EXTREME_ITLB_SMALL_MISS,
++	PNE_CORE2EXTREME_ITLB_MISS_RETIRED,
++	PNE_CORE2EXTREME_L1D_ALL_CACHE_REF,
++	PNE_CORE2EXTREME_L1D_ALL_REF,
++	PNE_CORE2EXTREME_L1D_CACHE_LD,
++	PNE_CORE2EXTREME_L1D_CACHE_LOCK,
++	PNE_CORE2EXTREME_L1D_CACHE_LOCK_DURATION,
++	PNE_CORE2EXTREME_L1D_CACHE_ST,
++	PNE_CORE2EXTREME_L1D_M_EVICT,
++	PNE_CORE2EXTREME_L1D_M_REPL,
++	PNE_CORE2EXTREME_L1D_PEND_MISS,
++	PNE_CORE2EXTREME_L1D_PREFETCH_REQUESTS,
++	PNE_CORE2EXTREME_L1D_REPL,
++	PNE_CORE2EXTREME_L1D_SPLIT_LOADS,
++	PNE_CORE2EXTREME_L1D_SPLIT_STORES,
++	PNE_CORE2EXTREME_L1I_MISSES,
++	PNE_CORE2EXTREME_L1I_READS,
++	PNE_CORE2EXTREME_L2_ADS,
++	PNE_CORE2EXTREME_L2_DBUS_BUSY_RD,
++	PNE_CORE2EXTREME_L2_IFETCH,
++	PNE_CORE2EXTREME_L2_LD,
++	PNE_CORE2EXTREME_L2_LINES_IN,
++	PNE_CORE2EXTREME_L2_LINES_OUT,
++	PNE_CORE2EXTREME_L2_LOCK,
++	PNE_CORE2EXTREME_L2_M_LINES_IN,
++	PNE_CORE2EXTREME_L2_M_LINES_OUT,
++	PNE_CORE2EXTREME_L2_NO_REQ,
++	PNE_CORE2EXTREME_L2_REJECT_BUSQ,
++	PNE_CORE2EXTREME_L2_RQSTS,
++	PNE_CORE2EXTREME_L2_RQSTS_SELF_DEMAND_I_STATE,
++	PNE_CORE2EXTREME_L2_RQSTS_SELF_DEMAND_MESI,
++	PNE_CORE2EXTREME_L2_ST,
++	PNE_CORE2EXTREME_LOAD_BLOCK_L1D,
++	PNE_CORE2EXTREME_LOAD_BLOCK_OVERLAP_STORE,
++	PNE_CORE2EXTREME_LOAD_BLOCK_STA,
++	PNE_CORE2EXTREME_LOAD_BLOCK_STD,
++	PNE_CORE2EXTREME_LOAD_BLOCK_UNTIL_RETIRE,
++	PNE_CORE2EXTREME_LOAD_HIT_PRE,
++	PNE_CORE2EXTREME_MACHINE_NUKES_MEM_ORDER,
++	PNE_CORE2EXTREME_MACHINE_NUKES_SMC,
++	PNE_CORE2EXTREME_MACRO_INSTS_CISC_DECODED,
++	PNE_CORE2EXTREME_MACRO_INSTS_DECODED,
++	PNE_CORE2EXTREME_MEMORY_DISAMBIGUATION_RESET,
++	PNE_CORE2EXTREME_MEMORY_DISAMBIGUATION_SUCCESS,
++	PNE_CORE2EXTREME_MEM_LOAD_RETIRED_DTLB_MISS,
++	PNE_CORE2EXTREME_MEM_LOAD_RETIRED_L1D_LINE_MISS,
++	PNE_CORE2EXTREME_MEM_LOAD_RETIRED_L1D_MISS,
++	PNE_CORE2EXTREME_MEM_LOAD_RETIRED_L2_LINE_MISS,
++	PNE_CORE2EXTREME_MEM_LOAD_RETIRED_L2_MISS,
++	PNE_CORE2EXTREME_MUL,
++	PNE_CORE2EXTREME_PAGE_WALKS_COUNT,
++	PNE_CORE2EXTREME_PAGE_WALKS_CYCLES,
++	PNE_CORE2EXTREME_PREF_RQSTS_DN,
++	PNE_CORE2EXTREME_PREF_RQSTS_UP,
++	PNE_CORE2EXTREME_RAT_STALLS_ANY,
++	PNE_CORE2EXTREME_RAT_STALLS_FLAGS,
++	PNE_CORE2EXTREME_RAT_STALLS_FPSW,
++	PNE_CORE2EXTREME_RAT_STALLS_OTHER_SERIALIZATION_STALLS,
++	PNE_CORE2EXTREME_RAT_STALLS_PARTIAL_CYCLES,
++	PNE_CORE2EXTREME_RAT_STALLS_ROB_READ_PORT,
++	PNE_CORE2EXTREME_RESOURCE_STALLS_ANY,
++	PNE_CORE2EXTREME_RESOURCE_STALLS_BR_MISS_CLEAR,
++	PNE_CORE2EXTREME_RESOURCE_STALLS_FPCW,
++	PNE_CORE2EXTREME_RESOURCE_STALLS_LD_ST,
++	PNE_CORE2EXTREME_RESOURCE_STALLS_ROB_FULL,
++	PNE_CORE2EXTREME_RESOURCE_STALLS_RS_FULL,
++	PNE_CORE2EXTREME_RS_UOPS_DISPATCHED,
++	PNE_CORE2EXTREME_RS_UOPS_DISPATCHED_PORT0,
++	PNE_CORE2EXTREME_RS_UOPS_DISPATCHED_PORT1,
++	PNE_CORE2EXTREME_RS_UOPS_DISPATCHED_PORT2,
++	PNE_CORE2EXTREME_RS_UOPS_DISPATCHED_PORT3,
++	PNE_CORE2EXTREME_RS_UOPS_DISPATCHED_PORT4,
++	PNE_CORE2EXTREME_RS_UOPS_DISPATCHED_PORT5,
++	PNE_CORE2EXTREME_SB_DRAIN_CYCLES,
++	PNE_CORE2EXTREME_SEGMENT_REG_LOADS,
++	PNE_CORE2EXTREME_SEG_REG_RENAMES_ANY,
++	PNE_CORE2EXTREME_SEG_REG_RENAMES_DS,
++	PNE_CORE2EXTREME_SEG_REG_RENAMES_ES,
++	PNE_CORE2EXTREME_SEG_REG_RENAMES_FS,
++	PNE_CORE2EXTREME_SEG_REG_RENAMES_GS,
++	PNE_CORE2EXTREME_SEG_RENAME_STALLS_ANY,
++	PNE_CORE2EXTREME_SEG_RENAME_STALLS_DS,
++	PNE_CORE2EXTREME_SEG_RENAME_STALLS_ES,
++	PNE_CORE2EXTREME_SEG_RENAME_STALLS_FS,
++	PNE_CORE2EXTREME_SEG_RENAME_STALLS_GS,
++	PNE_CORE2EXTREME_SIMD_ASSIST,
++	PNE_CORE2EXTREME_SIMD_COMP_INST_RETIRED_PACKED_DOUBLE,
++	PNE_CORE2EXTREME_SIMD_COMP_INST_RETIRED_PACKED_SINGLE,
++	PNE_CORE2EXTREME_SIMD_COMP_INST_RETIRED_SCALAR_DOUBLE,
++	PNE_CORE2EXTREME_SIMD_COMP_INST_RETIRED_SCALAR_SINGLE,
++	PNE_CORE2EXTREME_SIMD_INSTR_RETIRED,
++	PNE_CORE2EXTREME_SIMD_INST_RETIRED_ANY,
++	PNE_CORE2EXTREME_SIMD_INST_RETIRED_PACKED_DOUBLE,
++	PNE_CORE2EXTREME_SIMD_INST_RETIRED_PACKED_SINGLE,
++	PNE_CORE2EXTREME_SIMD_INST_RETIRED_SCALAR_DOUBLE,
++	PNE_CORE2EXTREME_SIMD_INST_RETIRED_SCALAR_SINGLE,
++	PNE_CORE2EXTREME_SIMD_INST_RETIRED_VECTOR,
++	PNE_CORE2EXTREME_SIMD_SAT_INSTR_RETIRED,
++	PNE_CORE2EXTREME_SIMD_SAT_UOP_EXEC,
++	PNE_CORE2EXTREME_SIMD_UOPS_EXEC,
++	PNE_CORE2EXTREME_SIMD_UOP_TYPE_EXEC_ARITHMETIC,
++	PNE_CORE2EXTREME_SIMD_UOP_TYPE_EXEC_LOGICAL,
++	PNE_CORE2EXTREME_SIMD_UOP_TYPE_EXEC_MUL,
++	PNE_CORE2EXTREME_SIMD_UOP_TYPE_EXEC_PACK,
++	PNE_CORE2EXTREME_SIMD_UOP_TYPE_EXEC_SHIFT,
++	PNE_CORE2EXTREME_SIMD_UOP_TYPE_EXEC_UNPACK,
++	PNE_CORE2EXTREME_SNOOP_STALL_DRV,
++	PNE_CORE2EXTREME_SSE_PRE_EXEC_L1,
++	PNE_CORE2EXTREME_SSE_PRE_EXEC_L2,
++	PNE_CORE2EXTREME_SSE_PRE_EXEC_NTA,
++	PNE_CORE2EXTREME_SSE_PRE_EXEC_STORES,
++	PNE_CORE2EXTREME_SSE_PRE_MISS_L1,
++	PNE_CORE2EXTREME_SSE_PRE_MISS_L2,
++	PNE_CORE2EXTREME_SSE_PRE_MISS_NTA,
++	PNE_CORE2EXTREME_STORE_BLOCK_ORDER,
++	PNE_CORE2EXTREME_STORE_BLOCK_SNOOP,
++	PNE_CORE2EXTREME_THERMAL_TRIP,
++	PNE_CORE2EXTREME_UOPS_RETIRED_ANY,
++	PNE_CORE2EXTREME_UOPS_RETIRED_FUSED,
++	PNE_CORE2EXTREME_UOPS_RETIRED_LD_IND_BR,
++	PNE_CORE2EXTREME_UOPS_RETIRED_MACRO_FUSION,
++	PNE_CORE2EXTREME_UOPS_RETIRED_NON_FUSED,
++	PNE_CORE2EXTREME_UOPS_RETIRED_STD_STA,
++	PNE_CORE2EXTREME_X87_OPS_RETIRED_ANY,
++	PNE_CORE2EXTREME_X87_OPS_RETIRED_FXCH,
++	PNE_CORE2EXTREME_NATNAME_GUARD
++};
++
++extern Native_Event_LabelDescription_t Core2ExtremeProcessor_info[];
++extern hwi_search_t Core2ExtremeProcessor_map[];
++
++#endif
diff --git a/devel/papi/files/patch-freebsd__map-core2.c b/devel/papi/files/patch-freebsd__map-core2.c
new file mode 100644
index 000000000000..1fc9921585d1
--- /dev/null
+++ b/devel/papi/files/patch-freebsd__map-core2.c
@@ -0,0 +1,277 @@
+--- ./freebsd/map-core2.c.orig	2009-07-15 12:05:10.717723000 -0400
++++ ./freebsd/map-core2.c	2009-07-15 12:05:10.720726000 -0400
+@@ -0,0 +1,274 @@
++/****************************/
++/* THIS IS OPEN SOURCE CODE */
++/****************************/
++
++/* 
++* File:    map-core2.c
++* CVS:     $Id: map-core2.c,v 1.3 2009/07/09 13:02:26 servat Exp $
++* Author:  George Neville-Neil
++*          gnn@freebsd.org
++*          Harald Servat
++*          redcrash@gmail.com
++*/
++
++#include SUBSTRATE
++#include "papiStdEventDefs.h"
++#include "map.h"
++
++
++/****************************************************************************
++ CORE2 SUBSTRATE 
++ CORE2 SUBSTRATE 
++ CORE2 SUBSTRATE
++ CORE2 SUBSTRATE
++ CORE2 SUBSTRATE
++****************************************************************************/
++
++/*
++	NativeEvent_Value_Core2Processor must match Core2Processor_info 
++*/
++
++Native_Event_LabelDescription_t Core2Processor_info[] =
++{
++	{"BACLEARS", "The number of times the front end is resteered."},
++	{"BOGUS_BR", "The number of byte sequences mistakenly detected as taken branch instructions."},
++	{"BR_BAC_MISSP_EXEC", "The number of branch instructions that were mispredicted when decoded."},
++	{"BR_CALL_MISSP_EXEC", "The number of mispredicted CALL instructions that were executed."},
++	{"BR_CALL_EXEC", "The number of CALL instructions executed."},
++	{"BR_CND_EXEC", "The number of conditional branches executed, but not necessarily retired."},
++	{"BR_CND_MISSP_EXEC", "The number of mispredicted conditional branches executed."},
++	{"BR_IND_CALL_EXEC", "The number of indirect CALL instructions executed."},
++	{"BR_IND_EXEC", "The number of indirect branch instructions executed."},
++	{"BR_IND_MISSP_EXEC", "The number of mispredicted indirect branch instructions executed."},
++	{"BR_INST_DECODED", "The number of branch instructions decoded."},
++	{"BR_INST_EXEC", "The number of branches executed, but not necessarily retired."},
++	{"BR_INST_RETIRED.ANY", "The number of branch instructions retired.  This is an architectural performance event."},
++	{"BR_INST_RETIRED.MISPRED", "The number of mispredicted branch instructions retired.  This is an architectural performance event."},
++	{"BR_INST_RETIRED.MISPRED_NOT_TAKEN", "The number of not taken branch instructions retired that were mispredicted."},
++	{"BR_INST_RETIRED.MISPRED_TAKEN", "The number taken branch instructions retired that were mispredicted."},
++	{"BR_INST_RETIRED.PRED_NOT_TAKEN", "The number of not taken branch instructions retired that were correctly predicted."},
++	{"BR_INST_RETIRED.PRED_TAKEN", "The number of taken branch instructions retired that were correctly predicted."},
++	{"BR_INST_RETIRED.TAKEN", "The number of taken branch instructions retired."},
++	{"BR_MISSP_EXEC", "The number of mispredicted branch instructions that were executed."},
++	{"BR_RET_MISSP_EXEC", "The number of mispredicted RET instructions executed."},
++	{"BR_RET_BAC_MISSP_EXEC", "The number of RET instructions executed that were mispredicted at decode time."},
++	{"BR_RET_EXEC", "The number of RET instructions executed."},
++	{"BR_TKN_BUBBLE_1", "The number of branch predicted taken with bubble 1."},
++	{"BR_TKN_BUBBLE_2", "The number of branch predicted taken with bubble 2."},
++	{"BUSQ_EMPTY", "The number of cycles during which the core did not have any pending transactions in the bus queue."},
++	{"BUS_BNR_DRV", "Number of Bus Not Ready signals asserted on the bus."},
++	{"BUS_DATA_RCV", "Number of bus cycles during which the processor is receiving data."},
++	{"BUS_DRDY_CLOCKS", "The number of bus cycles during which the Data Ready signal is asserted on the bus."},
++	{"BUS_HIT_DRV", "The number of bus cycles during which the processor drives the HIT# pin."},
++	{"BUS_HITM_DRV", "The number of bus cycles during which the processor drives the HITM# pin."},
++	{"BUS_IO_WAIT", "The number of core cycles during which I/O requests wait in the bus queue."},
++	{"BUS_LOCK_CLOCKS", "The number of bus cycles during which the LOCK signal was asserted on the bus."},
++	{"BUS_REQUEST_OUTSTANDING", "The number of pending full cache line read transactions on the bus occuring in each cycle."},
++	{"BUS_TRANS_ANY", "The number of bus transactions of any kind."},
++	{"BUS_TRANS_BRD", "The number of burst read transactions."},
++	{"BUS_TRANS_BURST", "The number of burst transactions."},
++	{"BUS_TRANS_DEF", "The number of deferred bus transactions."},
++	{"BUS_TRANS_IFETCH", "The number of instruction fetch full cache line bus transactions."},
++	{"BUS_TRANS_INVAL", "The number of invalidate bus transactions."},
++	{"BUS_TRANS_IO", "The number of completed I/O bus transaactions due to IN and OUT instructions."},
++	{"BUS_TRANS_MEM", "The number of memory bus transactions."},
++	{"BUS_TRANS_P", "The number of partial bus transactions."},
++	{"BUS_TRANS_PWR", "The number of partial write bus transactions."},
++	{"BUS_TRANS_RFO", "The number of Read For Ownership bus transactions."},
++	{"BUS_TRANS_WB", "The number of explicit writeback bus transactions due to dirty line evictions."},
++	{"CMP_SNOOP", "The number of times the L1 data cache is snooped by the other core in the same processor."},
++	{"CPU_CLK_UNHALTED.BUS", "The number of bus cycles when the core is not in the halt state. This is an architectural performance event."},
++	{"CPU_CLK_UNHALTED.CORE_P", "The number of core cycles while the core is not in a halt state.  This is an architectural performance event."},
++	{"CPU_CLK_UNHALTED.NO_OTHER", "The number of bus cycles during which the core remains unhalted and the other core is halted."},
++	{"CYCLES_DIV_BUSY", "The number of cycles the divider is busy.  This event is only available on PMC0."},
++	{"CYCLES_INT_MASKED", "The number of cycles during which interrupts are disabled."},
++	{"CYCLES_INT_PENDING_AND_MASKED", "The number of cycles during which there were pending interrupts while interrupts were disabled."},
++	{"CYCLES_L1I_MEM_STALLED", "The number of cycles for which an instruction fetch stalls."},
++	{"DELAYED_BYPASS.FP", "The number of floating point operations that used data immediately after the data was generated by a non floating point execution unit."},
++	{"DELAYED_BYPASS.LOAD", "The number of delayed bypass penalty cycles that a load operation incurred."},
++	{"DELAYED_BYPASS.SIMD", "The number of times SIMD operations use data immediately after data, was generated by a non-SIMD execution unit."},
++	{"DIV", "The number of divide operations executed."},
++	{"DTLB_MISSES.ANY", "The number of Data TLB misses, including misses that result from speculative accesses."},
++	{"DTLB_MISSES.L0_MISS_LD", "The number of level 0 DTLB misses due to load operations."},
++	{"DTLB_MISSES.MISS_LD", "The number of Data TLB misses due to load operations."},
++	{"DTLB_MISSES.MISS_ST", "The number of Data TLB misses due to store operations."},
++	{"EIST_TRANS", "The number of Enhanced Intel SpeedStep Technology transitions."},
++	{"ESP.ADDITIONS", "The number of automatic additions to the esp register."},
++	{"ESP.SYNCH", "The number of times the esp register was explicitly used in an address expression after it is implicitly used by a PUSH or POP instruction."},
++	{"EXT_SNOOP", "The number of snoop responses to bus transactions."},
++	{"FP_ASSIST", "The number of floating point operations executed that needed a microcode assist."},
++	{"FP_COMP_OPS_EXE", "The number of floating point computational micro-ops executed.  The event is available only on PMC0."},
++	{"FP_MMX_TRANS_TO_FP", "The number of transitions from MMX instructions to floating point instructions."},
++	{"FP_MMX_TRANS_TO_MMX", "The number of transitions from floating point instructions to MMX instructions."},
++	{"HW_INT_RCV", "The number of hardware interrupts recieved."},
++	{"IDLE_DURING_DIV", "The number of cycles the divider is busy and no other execution unit or load operation was in progress.  This event is available only on PMC0."},
++	{"ILD_STALL", "The number of cycles the instruction length decoder stalled due to a length changing prefix."},
++	{"INST_QUEUE.FULL", "The number of cycles during which the instruction queue is full."},
++	{"INST_RETIRED.ANY_P", "The number of instructions retired.  This is an architectural performance event."},
++	{"INST_RETIRED.LOADS", "The number of instructions retired that contained a load operation."},
++	{"INST_RETIRED.OTHER", "The number of instructions retired that did not contain a load or a store operation."},
++	{"INST_RETIRED.STORES", "The number of instructions retired that contained a store operation."},
++	{"ITLB.FLUSH", "The number of ITLB flushes."},
++	{"ITLB.LARGE_MISS", "The number of instruction fetches from large pages that miss the ITLB."},
++	{"ITLB.MISSES", "The number of instruction fetches from both large and small pages that miss the ITLB."},
++	{"ITLB.SMALL_MISS", "The number of instruction fetches from small pages that miss the ITLB."},
++	{"ITLB_MISS_RETIRED", "The number of retired instructions that missed the ITLB when they were fetched."},
++	{"L1D_ALL_CACHE_REF", "The number of data reads and writes to cacheable memory."},
++	{"L1D_ALL_REF", "The number of references to L1 data cache counting loads and stores of to all memory types."},
++	{"L1D_CACHE_LD", "Number of data reads from cacheable memory excluding locked reads."},
++	{"L1D_CACHE_LOCK", "Number of locked reads from cacheable memory."},
++	{"L1D_CACHE_LOCK_DURATION", "The number of cycles during which any cache line is locked by any locking instruction."},
++	{"L1D_CACHE_ST", "The number of data writes to cacheable memory excluding locked writes."},
++	{"L1D_M_EVICT", "The number of modified cache lines evicted from L1 data cache."},
++	{"L1D_M_REPL", "The number of modified lines allocated in L1 data cache."},
++	{"L1D_PEND_MISS", "The total number of outstanding L1 data cache misses at any clock."},
++	{"L1D_PREFETCH.REQUESTS", "The number of times L1 data cache requested to prefetch a data cache line."},
++	{"L1D_REPL", "The number of lines brought into L1 data cache."},
++	{"L1D_SPLIT.LOADS", "The number of load operations that span two cache lines."},
++	{"L1D_SPLIT.STORES", "The number of store operations that span two cache lines."},
++	{"L1I_MISSES", "The number of instruction fetch unit misses."},
++	{"L1I_READS", "The number of instruction fetches."},
++	{"L2_ADS", "The number of cycles that the L2 address bus is in use."},
++	{"L2_DBUS_BUSY_RD", "The number of cycles during which the L2 data bus is busy transferring data to the core."},
++	{"L2_IFETCH", "The number of instruction cache line requests from the instruction fetch unit."},
++	{"L2_LD", "The number of L2 cache read requests from L1 cache and L2 prefetchers."},
++	{"L2_LINES_IN", "The number of cache lines allocated in L2 cache."},
++	{"L2_LINES_OUT", "The number of L2 cache lines evicted."},
++	{"L2_LOCK", "The number of locked accesses to cache lines that miss L1 data cache."},
++	{"L2_M_LINES_IN", "The number of L2 cache line modifications."},
++	{"L2_M_LINES_OUT", "The number of modified lines evicted from L2 cache."},
++	{"L2_NO_REQ", "Number of cycles during which no L2 cache requests were pending from a core."},
++	{"L2_REJECT_BUSQ", "Number of L2 cache requests that were rejected."},
++	{"L2_RQSTS", "The number of completed L2 cache requests."},
++	{"L2_RQSTS.SELF.DEMAND.I_STATE", "The number of completed L2 cache demand requests from this core that missed the L2 cache.  This is an architectural performance event."},
++	{"L2_RQSTS.SELF.DEMAND.MESI", "The number of completed L2 cache demand requests from this core.  This is an architectural performance event."},
++	{"L2_ST", "The number of store operations that miss the L1 cache and request data from the L2 cache."},
++	{"LOAD_BLOCK.L1D", "The number of loads blocked by the L1 data cache."},
++	{"LOAD_BLOCK.OVERLAP_STORE", "The number of loads that partially overlap an earlier store or are aliased with a previous store."},
++	{"LOAD_BLOCK.STA", "The number of loads blocked by preceding stores whose address is yet to be calculated."},
++	{"LOAD_BLOCK.STD", "The number of loads blocked by preceding stores to the same address whose data value is not known."},
++	{"LOAD_BLOCK.UNTIL_RETIRE", "The numer of load operations that were blocked until retirement."},
++	{"LOAD_HIT_PRE", "The number of load operations that conflicted with an prefetch to the same cache line."},
++	{"MACHINE_NUKES.MEM_ORDER", "The number of times the execution pipeline was restarted due to a memory ordering conflict or memory disambiguation misprediction."},
++	{"MACHINE_NUKES.SMC", "The number of times a program writes to a code section."},
++	{"MACRO_INSTS.CISC_DECODED", "The number of complex instructions decoded."},
++	{"MACRO_INSTS.DECODED", "The number of instructions decoded."},
++	{"MEMORY_DISAMBIGUATION.RESET", "The number of cycles during which memory disambiguation misprediction occurs."},
++	{"MEMORY_DISAMBIGUATION.SUCCESS", "The number of load operations that were successfully disambiguated."},
++	{"MEM_LOAD_RETIRED.DTLB_MISS", "The number of retired loads that missed the DTLB."},
++	{"MEM_LOAD_RETIRED.L1D_LINE_MISS", "The number of retired load operations that missed L1 data cache and that sent a request to L2 cache. This event is only available on PMC0."},
++	{"MEM_LOAD_RETIRED.L1D_MISS", "The number of retired load operations that missed L1 data cache.  This event is only available on PMC0."},
++	{"MEM_LOAD_RETIRED.L2_LINE_MISS", "The number of load operations that missed L2 cache and that caused a bus request."},
++	{"MEM_LOAD_RETIRED.L2_MISS", "The number of load operations that missed L2 cache."},
++	{"MUL","The number of multiply operations executed (only available on PMC1.)"},
++	{"PAGE_WALKS.COUNT", "The number of page walks executed due to an ITLB or DTLB miss."},
++	{"PAGE_WALKS.CYCLES", "The number of cycles spent in a page walk caused by an ITLB or DTLB miss."},
++	{"PREF_RQSTS_DN", "The number of downward prefetches issued from the Data Prefetch Logic unit to L2 cache."},
++	{"PREF_RQSTS_UP", "The number of upward prefetches issued from the Data Prefetch Logic unit to L2 cache."},
++	{"RAT_STALLS.ANY", "The number of stall cycles due to any of RAT_STALLS.FLAGS RAT_STALLS.FPSW, RAT_STALLS.PARTIAL and RAT_STALLS.ROB_READ_PORT."},
++	{"RAT_STALLS.FLAGS", "The number of cycles execution stalled due to a flag register induced stall."},
++	{"RAT_STALLS.FPSW", "The number of times the floating point status word was written."},
++	{"RAT_STALLS.PARTIAL_CYCLES", "The number of cycles of added instruction execution latency due to the use of a register that was partially written by previous instructions."},
++	{"RAT_STALLS.ROB_READ_PORT", "The number of cycles when ROB read port stalls occurred."},
++	{"RESOURCE_STALLS.ANY", "The number of cycles during which any resource related stall occurred."},
++	{"RESOURCE_STALLS.BR_MISS_CLEAR", "The number of cycles stalled due to branch misprediction."},
++	{"RESOURCE_STALLS.FPCW", "The number of cycles stalled due to writing the floating point control word."},
++	{"RESOURCE_STALLS.LD_ST", "The number of cycles during which the number of loads and stores in the pipeline exceeded their limits."},
++	{"RESOURCE_STALLS.ROB_FULL", "The number of cycles when the reorder buffer was full."},
++	{"RESOURCE_STALLS.RS_FULL", "The number of cycles during which the RS was full."},
++	{"RS_UOPS_DISPATCHED", "The number of micro-ops dispatched for execution."},
++	{"RS_UOPS_DISPATCHED.PORT0", "The number of cycles micro-ops were dispatched for execution on port 0."},
++	{"RS_UOPS_DISPATCHED.PORT1", "The number of cycles micro-ops were dispatched for execution on port 1."},
++	{"RS_UOPS_DISPATCHED.PORT2", "The number of cycles micro-ops were dispatched for execution on port 2."},
++	{"RS_UOPS_DISPATCHED.PORT3", "The number of cycles micro-ops were dispatched for execution on port 3."},
++	{"RS_UOPS_DISPATCHED.PORT4", "The number of cycles micro-ops were dispatched for execution on port 4."},
++	{"RS_UOPS_DISPATCHED.PORT5", "The number of cycles micro-ops were dispatched for execution on port 5."},
++	{"SB_DRAIN_CYCLES", "The number of cycles while the store buffer is draining."},
++	{"SEGMENT_REG_LOADS", "The number of segment register loads."},
++	{"SEG_REG_RENAMES.ANY", "The number of times the any segment register was renamed."},
++	{"SEG_REG_RENAMES.DS", "The number of times the ds register is renamed."},
++	{"SEG_REG_RENAMES.ES", "The number of times the es register is renamed."},
++	{"SEG_REG_RENAMES.FS", "The number of times the fs register is renamed."},
++	{"SEG_REG_RENAMES.GS", "The number of times the gs register is renamed."},
++	{"SEG_RENAME_STALLS.ANY", "The number of stalls due to lack of resource to rename any segment register."},
++	{"SEG_RENAME_STALLS.DS", "The number of stalls due to lack of renaming resources for the ds register."},
++	{"SEG_RENAME_STALLS.ES", "The number of stalls due to lack of renaming resources for the es register."},
++	{"SEG_RENAME_STALLS.FS", "The number of stalls due to lack of renaming resources for the fs register."},
++	{"SEG_RENAME_STALLS.GS", "The number of stalls due to lack of renaming resources for the gs register."},
++	{"SIMD_ASSIST", "The number SIMD assists invoked."},
++	{"SIMD_COMP_INST_RETIRED.PACKED_DOUBLE", "Then number of computational SSE2 packed double precision instructions retired."},
++	{"SIMD_COMP_INST_RETIRED.PACKED_SINGLE", "Then number of computational SSE2 packed single precision instructions retired."},
++	{"SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE", "Then number of computational SSE2 scalar double precision instructions retired."},
++	{"SIMD_COMP_INST_RETIRED.SCALAR_SINGLE", "Then number of computational SSE2 scalar single precision instructions retired."},
++	{"SIMD_INSTR_RETIRED", "The number of retired SIMD instructions that use MMX registers."},
++	{"SIMD_INST_RETIRED.ANY", "The number of streaming SIMD instructions retired."},
++	{"SIMD_INST_RETIRED.PACKED_DOUBLE", "The number of SSE2 packed double precision instructions retired."},
++	{"SIMD_INST_RETIRED.PACKED_SINGLE", "The number of SSE packed single precision instructions retired."},
++	{"SIMD_INST_RETIRED.SCALAR_DOUBLE", "The number of SSE2 scalar double precision instructions retired."},
++	{"SIMD_INST_RETIRED.SCALAR_SINGLE", "The number of SSE scalar single precision instructions retired."},
++	{"SIMD_INST_RETIRED.VECTOR", "The number of SSE2 vector instructions retired."},
++	{"SIMD_SAT_INSTR_RETIRED", "The number of saturated arithmetic SIMD instructions retired."},
++	{"SIMD_SAT_UOP_EXEC", "The number of SIMD saturated arithmetic micro-ops executed."},
++	{"SIMD_UOPS_EXEC", "The number of SIMD micro-ops executed."},
++	{"SIMD_UOP_TYPE_EXEC.ARITHMETIC", "The number of SIMD packed arithmetic micro-ops executed."},
++	{"SIMD_UOP_TYPE_EXEC.LOGICAL", "The number of SIMD packed logical micro-ops executed."},
++	{"SIMD_UOP_TYPE_EXEC.MUL", "The number of SIMD packed multiply micro-ops executed."},
++	{"SIMD_UOP_TYPE_EXEC.PACK", "The number of SIMD pack micro-ops executed."},
++	{"SIMD_UOP_TYPE_EXEC.SHIFT", "The number of SIMD packed shift micro-ops executed."},
++	{"SIMD_UOP_TYPE_EXEC.UNPACK", "The number of SIMD unpack micro-ops executed."},
++	{"SNOOP_STALL_DRV", "The number of times the bus stalled for snoops."},
++	{"SSE_PRE_EXEC.L1", "The number of PREFETCHT0 instructions executed."},
++	{"SSE_PRE_EXEC.L2", "The number of PREFETCHT1 instructions executed."},
++	{"SSE_PRE_EXEC.NTA", "The number of PREFETCHNTA instructions executed."},
++	{"SSE_PRE_EXEC.STORES", "The number of times SSE non-temporal store instructions were executed."},
++	{"SSE_PRE_MISS.L1", "The number of times the PREFETCHT0 instruction executed and missed all cache levels."},
++	{"SSE_PRE_MISS.L2", "The number of times the PREFETCHT1 instruction executed and missed all cache levels."},
++	{"SSE_PRE_MISS.NTA", "The number of times the PREFETCHNTA instruction executed and missed all cache levels."},
++	{"STORE_BLOCK.ORDER", "The number of cycles while a store was waiting for another store to be globally observed."},
++	{"STORE_BLOCK.SNOOP", "The number of cycles while a store was blocked due to a conflict with an internal or external snoop."},
++	{"THERMAL_TRIP", "The number of thermal trips."},
++	{"UOPS_RETIRED.ANY", "The number of micro-ops retired."},
++	{"UOPS_RETIRED.FUSED", "The number of fused micro-ops retired."},
++	{"UOPS_RETIRED.LD_IND_BR", "The number of micro-ops retired that fused a load with another operation."},
++	{"UOPS_RETIRED.MACRO_FUSION", "The number of times retired instruction pairs were fused into one micro-op."},
++	{"UOPS_RETIRED.NON_FUSED", "he number of non-fused micro-ops retired."},
++	{"UOPS_RETIRED.STD_STA", "The number of store address calculations that fused into one micro-op."},
++	{"X87_OPS_RETIRED.ANY", "The number of floating point computational instructions retired."},
++	{"X87_OPS_RETIRED.FXCH", "The number of FXCH instructions retired."},
++	{ NULL, NULL } 
++};
++
++/* PAPI PRESETS */
++hwi_search_t Core2Processor_map[] = {
++	{PAPI_BR_INS, {0, {PNE_CORE2_BR_INST_RETIRED_ANY, PAPI_NULL}, {0,}}},
++	{PAPI_RES_STL, {0, {PNE_CORE2_RESOURCE_STALLS_ANY, PAPI_NULL}, {0,}}},
++	{PAPI_TOT_CYC, {0, {PNE_CORE2_CPU_CLK_UNHALTED_BUS, PAPI_NULL}, {0,}}},
++	{PAPI_TOT_INS, {0, {PNE_CORE2_INST_RETIRED_ANY_P, PAPI_NULL}, {0,}}},
++	{PAPI_HW_INT, {0, {PNE_CORE2_HW_INT_RCV, PAPI_NULL}, {0,}}},
++	{PAPI_BR_TKN, {0, {PNE_CORE2_BR_INST_RETIRED_TAKEN, PAPI_NULL}, {0,}}},
++	{PAPI_BR_MSP, {0, {PNE_CORE2_BR_MISSP_EXEC, PAPI_NULL}, {0,}}},
++	{PAPI_TLB_DM, {0, {PNE_CORE2_DTLB_MISSES_ANY, PAPI_NULL}, {0,}}},
++	{PAPI_TLB_IM, {0, {PNE_CORE2_ITLB_MISSES, PAPI_NULL}, {0,}}},
++#if HWPMC_NUM_COUNTERS >= 2
++	{PAPI_TLB_TL, {DERIVED_ADD, {PNE_CORE2_DTLB_MISSES_ANY, PNE_CORE2_ITLB_MISSES, PAPI_NULL},{0,}}},
++#endif
++	{PAPI_L1_DCA, {0, {PNE_CORE2_L1D_ALL_REF, PAPI_NULL}, {0,}}},
++	{PAPI_L1_ICA, {0, {PNE_CORE2_L1I_READS, PAPI_NULL}, {0,}}},
++#if HWPMC_NUM_COUNTERS >= 2
++	{PAPI_L1_TCA, {DERIVED_ADD, {PNE_CORE2_L1D_ALL_REF, PNE_CORE2_L1I_READS, PAPI_NULL}, {0,}}},
++#endif
++	/* PAPI_L2_ICH seems not to work
++	{PAPI_L2_ICH, {0, {PNE_CORE2_L2_IFETCH, PAPI_NULL}, {0,}}},
++	*/
++	{PAPI_L2_DCH, {0, {PNE_CORE2_L2_LD, PAPI_NULL}, {0,}}},
++	{PAPI_FP_INS, {0, {PNE_CORE2_X87_OPS_RETIRED_ANY, PAPI_NULL}, {0,}}},
++	{PAPI_L1_DCM, {0, {PNE_CORE2_MEM_LOAD_RETIRED_L1D_MISS, PAPI_NULL}, {0,}}},
++	{PAPI_L1_ICM, {0, {PNE_CORE2_L1I_MISSES, PAPI_NULL}, {0,}}},
++#if HWPMC_NUM_COUNTERS >= 2
++	{PAPI_L1_TCM, {DERIVED_ADD, {PNE_CORE2_MEM_LOAD_RETIRED_L1D_MISS, PNE_CORE2_L1I_MISSES, PAPI_NULL}, {0,}}},
++#endif
++	{PAPI_L2_DCM, {0, {PNE_CORE2_MEM_LOAD_RETIRED_L2_MISS, PAPI_NULL}, {0,}}},
++	{0, {0, {PAPI_NULL}, {0,}}}
++};
++
++
diff --git a/devel/papi/files/patch-freebsd__map-core2.h b/devel/papi/files/patch-freebsd__map-core2.h
new file mode 100644
index 000000000000..3443406621df
--- /dev/null
+++ b/devel/papi/files/patch-freebsd__map-core2.h
@@ -0,0 +1,230 @@
+--- ./freebsd/map-core2.h.orig	2009-07-15 12:05:10.733724000 -0400
++++ ./freebsd/map-core2.h	2009-07-15 12:05:10.736720000 -0400
+@@ -0,0 +1,227 @@
++/****************************/
++/* THIS IS OPEN SOURCE CODE */
++/****************************/
++
++/* 
++* File:    map-core2.h
++* CVS:     $Id: map-core2.h,v 1.2 2009/07/09 13:02:26 servat Exp $
++* Author:  George Neville-Neil
++*          gnn@freebsd.org
++*/
++
++#ifndef FreeBSD_MAP_CORE2
++#define FreeBSD_MAP_CORE2
++
++enum NativeEvent_Value_Core2Processor {
++	PNE_CORE2_BACLEARS = PAPI_NATIVE_MASK ,
++	PNE_CORE2_BOGUS_BR,
++	PNE_CORE2_BR_BAC_MISSP_EXEC,
++	PNE_CORE2_BR_CALL_MISSP_EXEC,
++	PNE_CORE2_BR_CALL_EXEC,
++	PNE_CORE2_BR_CND_EXEC,
++	PNE_CORE2_BR_CND_MISSP_EXEC,
++	PNE_CORE2_BR_IND_CALL_EXEC,
++	PNE_CORE2_BR_IND_EXEC,
++	PNE_CORE2_BR_IND_MISSP_EXEC,
++	PNE_CORE2_BR_INST_DECODED,
++	PNE_CORE2_BR_INST_EXEC,
++	PNE_CORE2_BR_INST_RETIRED_ANY,
++	PNE_CORE2_BR_INST_RETIRED_MISPRED,
++	PNE_CORE2_BR_INST_RETIRED_MISPRED_NOT_TAKEN,
++	PNE_CORE2_BR_INST_RETIRED_MISPRED_TAKEN,
++	PNE_CORE2_BR_INST_RETIRED_PRED_NOT_TAKEN,
++	PNE_CORE2_BR_INST_RETIRED_PRED_TAKEN,
++	PNE_CORE2_BR_INST_RETIRED_TAKEN,
++	PNE_CORE2_BR_MISSP_EXEC,
++	PNE_CORE2_BR_RET_MISSP_EXEC,
++	PNE_CORE2_BR_RET_BAC_MISSP_EXEC,
++	PNE_CORE2_BR_RET_EXEC,
++	PNE_CORE2_BR_TKN_BUBBLE_1,
++	PNE_CORE2_BR_TKN_BUBBLE_2,
++	PNE_CORE2_BUSQ_EMPTY,
++	PNE_CORE2_BUS_BNR_DRV,
++	PNE_CORE2_BUS_DATA_RCV,
++	PNE_CORE2_BUS_DRDY_CLOCKS,
++	PNE_CORE2_BUS_HIT_DRV,
++	PNE_CORE2_BUS_HITM_DRV,
++	PNE_CORE2_BUS_IO_WAIT,
++	PNE_CORE2_BUS_LOCK_CLOCKS,
++	PNE_CORE2_BUS_REQUEST_OUTSTANDING,
++	PNE_CORE2_BUS_TRANS_ANY,
++	PNE_CORE2_BUS_TRANS_BRD,
++	PNE_CORE2_BUS_TRANS_BURST,
++	PNE_CORE2_BUS_TRANS_DEF,
++	PNE_CORE2_BUS_TRANS_IFETCH,
++	PNE_CORE2_BUS_TRANS_INVAL,
++	PNE_CORE2_BUS_TRANS_IO,
++	PNE_CORE2_BUS_TRANS_MEM,
++	PNE_CORE2_BUS_TRANS_P,
++	PNE_CORE2_BUS_TRANS_PWR,
++	PNE_CORE2_BUS_TRANS_RFO,
++	PNE_CORE2_BUS_TRANS_WB,
++	PNE_CORE2_CMP_SNOOP,
++	PNE_CORE2_CPU_CLK_UNHALTED_BUS,
++	PNE_CORE2_CPU_CLK_UNHALTED_CORE_P,
++	PNE_CORE2_CPU_CLK_UNHALTED_NO_OTHER,
++	PNE_CORE2_CYCLES_DIV_BUSY,
++	PNE_CORE2_CYCLES_INT_MASKED,
++	PNE_CORE2_CYCLES_INT_PENDING_AND_MASKED,
++	PNE_CORE2_CYCLES_L1I_MEM_STALLED,
++	PNE_CORE2_DELAYED_BYPASS_FP,
++	PNE_CORE2_DELAYED_BYPASS_LOAD,
++	PNE_CORE2_DELAYED_BYPASS_SIMD,
++	PNE_CORE2_DIV,
++	PNE_CORE2_DTLB_MISSES_ANY,
++	PNE_CORE2_DTLB_MISSES_L0_MISS_LD,
++	PNE_CORE2_DTLB_MISSES_MISS_LD,
++	PNE_CORE2_DTLB_MISSES_MISS_ST,
++	PNE_CORE2_EIST_TRANS,
++	PNE_CORE2_ESP_ADDITIONS,
++	PNE_CORE2_ESP_SYNCH,
++	PNE_CORE2_EXT_SNOOP,
++	PNE_CORE2_FP_ASSIST,
++	PNE_CORE2_FP_COMP_OPS_EXE,
++	PNE_CORE2_FP_MMX_TRANS_TO_FP,
++	PNE_CORE2_FP_MMX_TRANS_TO_MMX,
++	PNE_CORE2_HW_INT_RCV,
++	PNE_CORE2_IDLE_DURING_DIV,
++	PNE_CORE2_ILD_STALL,
++	PNE_CORE2_INST_QUEUE_FULL,
++	PNE_CORE2_INST_RETIRED_ANY_P,
++	PNE_CORE2_INST_RETIRED_LOADS,
++	PNE_CORE2_INST_RETIRED_OTHER,
++	PNE_CORE2_INST_RETIRED_STORES,
++	PNE_CORE2_ITLB_FLUSH,
++	PNE_CORE2_ITLB_LARGE_MISS,
++	PNE_CORE2_ITLB_MISSES,
++	PNE_CORE2_ITLB_SMALL_MISS,
++	PNE_CORE2_ITLB_MISS_RETIRED,
++	PNE_CORE2_L1D_ALL_CACHE_REF,
++	PNE_CORE2_L1D_ALL_REF,
++	PNE_CORE2_L1D_CACHE_LD,
++	PNE_CORE2_L1D_CACHE_LOCK,
++	PNE_CORE2_L1D_CACHE_LOCK_DURATION,
++	PNE_CORE2_L1D_CACHE_ST,
++	PNE_CORE2_L1D_M_EVICT,
++	PNE_CORE2_L1D_M_REPL,
++	PNE_CORE2_L1D_PEND_MISS,
++	PNE_CORE2_L1D_PREFETCH_REQUESTS,
++	PNE_CORE2_L1D_REPL,
++	PNE_CORE2_L1D_SPLIT_LOADS,
++	PNE_CORE2_L1D_SPLIT_STORES,
++	PNE_CORE2_L1I_MISSES,
++	PNE_CORE2_L1I_READS,
++	PNE_CORE2_L2_ADS,
++	PNE_CORE2_L2_DBUS_BUSY_RD,
++	PNE_CORE2_L2_IFETCH,
++	PNE_CORE2_L2_LD,
++	PNE_CORE2_L2_LINES_IN,
++	PNE_CORE2_L2_LINES_OUT,
++	PNE_CORE2_L2_LOCK,
++	PNE_CORE2_L2_M_LINES_IN,
++	PNE_CORE2_L2_M_LINES_OUT,
++	PNE_CORE2_L2_NO_REQ,
++	PNE_CORE2_L2_REJECT_BUSQ,
++	PNE_CORE2_L2_RQSTS,
++	PNE_CORE2_L2_RQSTS_SELF_DEMAND_I_STATE,
++	PNE_CORE2_L2_RQSTS_SELF_DEMAND_MESI,
++	PNE_CORE2_L2_ST,
++	PNE_CORE2_LOAD_BLOCK_L1D,
++	PNE_CORE2_LOAD_BLOCK_OVERLAP_STORE,
++	PNE_CORE2_LOAD_BLOCK_STA,
++	PNE_CORE2_LOAD_BLOCK_STD,
++	PNE_CORE2_LOAD_BLOCK_UNTIL_RETIRE,
++	PNE_CORE2_LOAD_HIT_PRE,
++	PNE_CORE2_MACHINE_NUKES_MEM_ORDER,
++	PNE_CORE2_MACHINE_NUKES_SMC,
++	PNE_CORE2_MACRO_INSTS_CISC_DECODED,
++	PNE_CORE2_MACRO_INSTS_DECODED,
++	PNE_CORE2_MEMORY_DISAMBIGUATION_RESET,
++	PNE_CORE2_MEMORY_DISAMBIGUATION_SUCCESS,
++	PNE_CORE2_MEM_LOAD_RETIRED_DTLB_MISS,
++	PNE_CORE2_MEM_LOAD_RETIRED_L1D_LINE_MISS,
++	PNE_CORE2_MEM_LOAD_RETIRED_L1D_MISS,
++	PNE_CORE2_MEM_LOAD_RETIRED_L2_LINE_MISS,
++	PNE_CORE2_MEM_LOAD_RETIRED_L2_MISS,
++	PNE_CORE2_MUL,
++	PNE_CORE2_PAGE_WALKS_COUNT,
++	PNE_CORE2_PAGE_WALKS_CYCLES,
++	PNE_CORE2_PREF_RQSTS_DN,
++	PNE_CORE2_PREF_RQSTS_UP,
++	PNE_CORE2_RAT_STALLS_ANY,
++	PNE_CORE2_RAT_STALLS_FLAGS,
++	PNE_CORE2_RAT_STALLS_FPSW,
++	PNE_CORE2_RAT_STALLS_PARTIAL_CYCLES,
++	PNE_CORE2_RAT_STALLS_ROB_READ_PORT,
++	PNE_CORE2_RESOURCE_STALLS_ANY,
++	PNE_CORE2_RESOURCE_STALLS_BR_MISS_CLEAR,
++	PNE_CORE2_RESOURCE_STALLS_FPCW,
++	PNE_CORE2_RESOURCE_STALLS_LD_ST,
++	PNE_CORE2_RESOURCE_STALLS_ROB_FULL,
++	PNE_CORE2_RESOURCE_STALLS_RS_FULL,
++	PNE_CORE2_RS_UOPS_DISPATCHED,
++	PNE_CORE2_RS_UOPS_DISPATCHED_PORT0,
++	PNE_CORE2_RS_UOPS_DISPATCHED_PORT1,
++	PNE_CORE2_RS_UOPS_DISPATCHED_PORT2,
++	PNE_CORE2_RS_UOPS_DISPATCHED_PORT3,
++	PNE_CORE2_RS_UOPS_DISPATCHED_PORT4,
++	PNE_CORE2_RS_UOPS_DISPATCHED_PORT5,
++	PNE_CORE2_SB_DRAIN_CYCLES,
++	PNE_CORE2_SEGMENT_REG_LOADS,
++	PNE_CORE2_SEG_REG_RENAMES_ANY,
++	PNE_CORE2_SEG_REG_RENAMES_DS,
++	PNE_CORE2_SEG_REG_RENAMES_ES,
++	PNE_CORE2_SEG_REG_RENAMES_FS,
++	PNE_CORE2_SEG_REG_RENAMES_GS,
++	PNE_CORE2_SEG_RENAME_STALLS_ANY,
++	PNE_CORE2_SEG_RENAME_STALLS_DS,
++	PNE_CORE2_SEG_RENAME_STALLS_ES,
++	PNE_CORE2_SEG_RENAME_STALLS_FS,
++	PNE_CORE2_SEG_RENAME_STALLS_GS,
++	PNE_CORE2_SIMD_ASSIST,
++	PNE_CORE2_SIMD_COMP_INST_RETIRED_PACKED_DOUBLE,
++	PNE_CORE2_SIMD_COMP_INST_RETIRED_PACKED_SINGLE,
++	PNE_CORE2_SIMD_COMP_INST_RETIRED_SCALAR_DOUBLE,
++	PNE_CORE2_SIMD_COMP_INST_RETIRED_SCALAR_SINGLE,
++	PNE_CORE2_SIMD_INSTR_RETIRED,
++	PNE_CORE2_SIMD_INST_RETIRED_ANY,
++	PNE_CORE2_SIMD_INST_RETIRED_PACKED_DOUBLE,
++	PNE_CORE2_SIMD_INST_RETIRED_PACKED_SINGLE,
++	PNE_CORE2_SIMD_INST_RETIRED_SCALAR_DOUBLE,
++	PNE_CORE2_SIMD_INST_RETIRED_SCALAR_SINGLE,
++	PNE_CORE2_SIMD_INST_RETIRED_VECTOR,
++	PNE_CORE2_SIMD_SAT_INSTR_RETIRED,
++	PNE_CORE2_SIMD_SAT_UOP_EXEC,
++	PNE_CORE2_SIMD_UOPS_EXEC,
++	PNE_CORE2_SIMD_UOP_TYPE_EXEC_ARITHMETIC,
++	PNE_CORE2_SIMD_UOP_TYPE_EXEC_LOGICAL,
++	PNE_CORE2_SIMD_UOP_TYPE_EXEC_MUL,
++	PNE_CORE2_SIMD_UOP_TYPE_EXEC_PACK,
++	PNE_CORE2_SIMD_UOP_TYPE_EXEC_SHIFT,
++	PNE_CORE2_SIMD_UOP_TYPE_EXEC_UNPACK,
++	PNE_CORE2_SNOOP_STALL_DRV,
++	PNE_CORE2_SSE_PRE_EXEC_L1,
++	PNE_CORE2_SSE_PRE_EXEC_L2,
++	PNE_CORE2_SSE_PRE_EXEC_NTA,
++	PNE_CORE2_SSE_PRE_EXEC_STORES,
++	PNE_CORE2_SSE_PRE_MISS_L1,
++	PNE_CORE2_SSE_PRE_MISS_L2,
++	PNE_CORE2_SSE_PRE_MISS_NTA,
++	PNE_CORE2_STORE_BLOCK_ORDER,
++	PNE_CORE2_STORE_BLOCK_SNOOP,
++	PNE_CORE2_THERMAL_TRIP,
++	PNE_CORE2_UOPS_RETIRED_ANY,
++	PNE_CORE2_UOPS_RETIRED_FUSED,
++	PNE_CORE2_UOPS_RETIRED_LD_IND_BR,
++	PNE_CORE2_UOPS_RETIRED_MACRO_FUSION,
++	PNE_CORE2_UOPS_RETIRED_NON_FUSED,
++	PNE_CORE2_UOPS_RETIRED_STD_STA,
++	PNE_CORE2_X87_OPS_RETIRED_ANY,
++	PNE_CORE2_X87_OPS_RETIRED_FXCH,
++	PNE_CORE2_NATNAME_GUARD
++};
++
++extern Native_Event_LabelDescription_t Core2Processor_info[];
++extern hwi_search_t Core2Processor_map[];
++
++#endif
diff --git a/devel/papi/files/patch-freebsd__map.c b/devel/papi/files/patch-freebsd__map.c
new file mode 100644
index 000000000000..9d42ffe6fad4
--- /dev/null
+++ b/devel/papi/files/patch-freebsd__map.c
@@ -0,0 +1,33 @@
+--- ./freebsd/map.c.orig	2008-04-26 04:19:39.000000000 -0400
++++ ./freebsd/map.c	2009-07-15 12:05:10.751726000 -0400
+@@ -4,9 +4,9 @@
+ 
+ /* 
+ * File:    freebsd-map.c
+-* CVS:     $Id: map.c,v 1.1 2008-04-26 08:19:39 servat Exp $
++* CVS:     $Id: map.c,v 1.4 2009/07/09 13:02:26 servat Exp $
+ * Author:  Harald Servat
+-*          harald.servat@gmail.com
++*          redcrash@gmail.com
+ */
+ 
+ #include SUBSTRATE
+@@ -46,6 +46,18 @@
+ 	_papi_hwd_native_info[CPU_K8].map = K8Processor_map;
+ 	_papi_hwd_native_info[CPU_K8].info = K8Processor_info;
+ 
++	_papi_hwd_native_info[CPU_ATOM].map = AtomProcessor_map;
++	_papi_hwd_native_info[CPU_ATOM].info = AtomProcessor_info;
++
++	_papi_hwd_native_info[CPU_CORE].map = CoreProcessor_map;
++	_papi_hwd_native_info[CPU_CORE].info = CoreProcessor_info;
++
++	_papi_hwd_native_info[CPU_CORE2].map = Core2Processor_map;
++	_papi_hwd_native_info[CPU_CORE2].info = Core2Processor_info;
++
++	_papi_hwd_native_info[CPU_CORE2EXTREME].map = Core2ExtremeProcessor_map;
++	_papi_hwd_native_info[CPU_CORE2EXTREME].info = Core2ExtremeProcessor_info;
++
+ 	_papi_hwd_native_info[CPU_LAST].map = NULL;
+ 	_papi_hwd_native_info[CPU_LAST].info = NULL;
+ }
diff --git a/devel/papi/files/patch-freebsd__map.h b/devel/papi/files/patch-freebsd__map.h
new file mode 100644
index 000000000000..17b389096027
--- /dev/null
+++ b/devel/papi/files/patch-freebsd__map.h
@@ -0,0 +1,35 @@
+--- ./freebsd/map.h.orig	2008-04-26 04:19:39.000000000 -0400
++++ ./freebsd/map.h	2009-07-15 12:05:10.769719000 -0400
+@@ -4,9 +4,9 @@
+ 
+ /* 
+ * File:    freebsd-map.h
+-* CVS:     $Id: map.h,v 1.1 2008-04-26 08:19:39 servat Exp $
++* CVS:     $Id: map.h,v 1.4 2009/07/09 13:02:26 servat Exp $
+ * Author:  Harald Servat
+-*          harald.servat@gmail.com
++*          redcrash@gmail.com
+ */
+ 
+ #ifndef _FreeBSD_MAP_H_
+@@ -27,6 +27,10 @@
+ 	CPU_P4,
+ 	CPU_K7,
+ 	CPU_K8,
++	CPU_ATOM,
++	CPU_CORE,
++	CPU_CORE2,
++	CPU_CORE2EXTREME,
+ 	CPU_LAST
+ };
+ 
+@@ -57,5 +61,9 @@
+ #include "map-p4.h"
+ #include "map-k7.h"
+ #include "map-k8.h"
++#include "map-atom.h"
++#include "map-core.h"
++#include "map-core2.h"
++#include "map-core2-extreme.h"
+ 
+ #endif /* _FreeBSD_MAP_H_ */
diff --git a/devel/papi/pkg-plist b/devel/papi/pkg-plist
index 2813c7e74772..78e08c3c38c1 100644
--- a/devel/papi/pkg-plist
+++ b/devel/papi/pkg-plist
@@ -13,88 +13,90 @@ include/papi.h
 include/papiStdEventDefs.h
 lib/libpapi.a
 lib/libpapi.so.3
-%%CTESTS%%share/ctests/all_events
-%%CTESTS%%share/ctests/all_native_events
-%%CTESTS%%share/ctests/branches
-%%CTESTS%%share/ctests/byte_profile
-%%CTESTS%%share/ctests/calibrate
-%%CTESTS%%share/ctests/case1
-%%CTESTS%%share/ctests/case2
-%%CTESTS%%share/ctests/clockres_pthreads
-%%CTESTS%%share/ctests/code2name
-%%CTESTS%%share/ctests/derived
-%%CTESTS%%share/ctests/describe
-%%CTESTS%%share/ctests/dmem_info
-%%CTESTS%%share/ctests/encode
-%%CTESTS%%share/ctests/encode2
-%%CTESTS%%share/ctests/eventname
-%%CTESTS%%share/ctests/exeinfo
-%%CTESTS%%share/ctests/first
-%%CTESTS%%share/ctests/flops
-%%CTESTS%%share/ctests/high-level
-%%CTESTS%%share/ctests/high-level2
-%%CTESTS%%share/ctests/hwinfo
-%%CTESTS%%share/ctests/ipc
-%%CTESTS%%share/ctests/johnmay2
-%%CTESTS%%share/ctests/kufrin
-%%CTESTS%%share/ctests/locks_pthreads
-%%CTESTS%%share/ctests/low-level
-%%CTESTS%%share/ctests/matrix-hl
-%%CTESTS%%share/ctests/memory
-%%CTESTS%%share/ctests/mendes-alt
-%%CTESTS%%share/ctests/multiplex1
-%%CTESTS%%share/ctests/multiplex1_pthreads
-%%CTESTS%%share/ctests/multiplex2
-%%CTESTS%%share/ctests/multiplex3_pthreads
-%%CTESTS%%share/ctests/overflow
-%%CTESTS%%share/ctests/overflow2
-%%CTESTS%%share/ctests/overflow3_pthreads
-%%CTESTS%%share/ctests/overflow_force_software
-%%CTESTS%%share/ctests/overflow_index
-%%CTESTS%%share/ctests/overflow_one_and_read
-%%CTESTS%%share/ctests/overflow_pthreads
-%%CTESTS%%share/ctests/overflow_single_event
-%%CTESTS%%share/ctests/overflow_twoevents
-%%CTESTS%%share/ctests/profile
-%%CTESTS%%share/ctests/profile_pthreads
-%%CTESTS%%share/ctests/profile_twoevents
-%%CTESTS%%share/ctests/realtime
-%%CTESTS%%share/ctests/reset
-%%CTESTS%%share/ctests/sdsc-mpx
-%%CTESTS%%share/ctests/sdsc2-mpx
-%%CTESTS%%share/ctests/sdsc4-mpx
-%%CTESTS%%share/ctests/second
-%%CTESTS%%share/ctests/sprofile
-%%CTESTS%%share/ctests/subinfo
-%%CTESTS%%share/ctests/tenth
-%%CTESTS%%share/ctests/thrspecific
-%%CTESTS%%share/ctests/timer_overflow
-%%CTESTS%%share/ctests/unregister_pthreads
-%%CTESTS%%share/ctests/zero
-%%CTESTS%%share/ctests/zero_flip
-%%CTESTS%%share/ctests/zero_fork
-%%CTESTS%%share/ctests/zero_pthreads
-%%FTESTS%%share/ftests/accum
-%%FTESTS%%share/ftests/avail
-%%FTESTS%%share/ftests/case1
-%%FTESTS%%share/ftests/case2
-%%FTESTS%%share/ftests/clockres
-%%FTESTS%%share/ftests/cost
-%%FTESTS%%share/ftests/description
-%%FTESTS%%share/ftests/eventname
-%%FTESTS%%share/ftests/fdmemtest
-%%FTESTS%%share/ftests/first
-%%FTESTS%%share/ftests/flops
-%%FTESTS%%share/ftests/fmatrixlowpapi
-%%FTESTS%%share/ftests/fmatrixpapi
-%%FTESTS%%share/ftests/fmatrixpapi2
-%%FTESTS%%share/ftests/fmultiplex1
-%%FTESTS%%share/ftests/fmultiplex2
-%%FTESTS%%share/ftests/highlevel
-%%FTESTS%%share/ftests/johnmay2
-%%FTESTS%%share/ftests/second
-%%FTESTS%%share/ftests/strtest
-%%FTESTS%%share/ftests/tenth
-%%FTESTS%%share/ftests/zero
-%%FTESTS%%@dirrm share/ftests
-%%CTESTS%%@dirrm share/ctests
+%%CTESTS%%share/papi/ctests/all_events
+%%CTESTS%%share/papi/ctests/all_native_events
+%%CTESTS%%share/papi/ctests/branches
+%%CTESTS%%share/papi/ctests/byte_profile
+%%CTESTS%%share/papi/ctests/calibrate
+%%CTESTS%%share/papi/ctests/case1
+%%CTESTS%%share/papi/ctests/case2
+%%CTESTS%%share/papi/ctests/clockres_pthreads
+%%CTESTS%%share/papi/ctests/code2name
+%%CTESTS%%share/papi/ctests/derived
+%%CTESTS%%share/papi/ctests/describe
+%%CTESTS%%share/papi/ctests/dmem_info
+%%CTESTS%%share/papi/ctests/encode
+%%CTESTS%%share/papi/ctests/encode2
+%%CTESTS%%share/papi/ctests/eventname
+%%CTESTS%%share/papi/ctests/exeinfo
+%%CTESTS%%share/papi/ctests/first
+%%CTESTS%%share/papi/ctests/flops
+%%CTESTS%%share/papi/ctests/high-level
+%%CTESTS%%share/papi/ctests/high-level2
+%%CTESTS%%share/papi/ctests/hwinfo
+%%CTESTS%%share/papi/ctests/ipc
+%%CTESTS%%share/papi/ctests/johnmay2
+%%CTESTS%%share/papi/ctests/kufrin
+%%CTESTS%%share/papi/ctests/locks_pthreads
+%%CTESTS%%share/papi/ctests/low-level
+%%CTESTS%%share/papi/ctests/matrix-hl
+%%CTESTS%%share/papi/ctests/memory
+%%CTESTS%%share/papi/ctests/mendes-alt
+%%CTESTS%%share/papi/ctests/multiplex1
+%%CTESTS%%share/papi/ctests/multiplex1_pthreads
+%%CTESTS%%share/papi/ctests/multiplex2
+%%CTESTS%%share/papi/ctests/multiplex3_pthreads
+%%CTESTS%%share/papi/ctests/overflow
+%%CTESTS%%share/papi/ctests/overflow2
+%%CTESTS%%share/papi/ctests/overflow3_pthreads
+%%CTESTS%%share/papi/ctests/overflow_force_software
+%%CTESTS%%share/papi/ctests/overflow_index
+%%CTESTS%%share/papi/ctests/overflow_one_and_read
+%%CTESTS%%share/papi/ctests/overflow_pthreads
+%%CTESTS%%share/papi/ctests/overflow_single_event
+%%CTESTS%%share/papi/ctests/overflow_twoevents
+%%CTESTS%%share/papi/ctests/profile
+%%CTESTS%%share/papi/ctests/profile_pthreads
+%%CTESTS%%share/papi/ctests/profile_twoevents
+%%CTESTS%%share/papi/ctests/realtime
+%%CTESTS%%share/papi/ctests/reset
+%%CTESTS%%share/papi/ctests/sdsc-mpx
+%%CTESTS%%share/papi/ctests/sdsc2-mpx
+%%CTESTS%%share/papi/ctests/sdsc4-mpx
+%%CTESTS%%share/papi/ctests/second
+%%CTESTS%%share/papi/ctests/sprofile
+%%CTESTS%%share/papi/ctests/subinfo
+%%CTESTS%%share/papi/ctests/tenth
+%%CTESTS%%share/papi/ctests/thrspecific
+%%CTESTS%%share/papi/ctests/timer_overflow
+%%CTESTS%%share/papi/ctests/unregister_pthreads
+%%CTESTS%%share/papi/ctests/zero
+%%CTESTS%%share/papi/ctests/zero_flip
+%%CTESTS%%share/papi/ctests/zero_fork
+%%CTESTS%%share/papi/ctests/zero_pthreads
+%%FTESTS%%share/papi/ftests/accum
+%%FTESTS%%share/papi/ftests/avail
+%%FTESTS%%share/papi/ftests/case1
+%%FTESTS%%share/papi/ftests/case2
+%%FTESTS%%share/papi/ftests/clockres
+%%FTESTS%%share/papi/ftests/cost
+%%FTESTS%%share/papi/ftests/description
+%%FTESTS%%share/papi/ftests/eventname
+%%FTESTS%%share/papi/ftests/fdmemtest
+%%FTESTS%%share/papi/ftests/first
+%%FTESTS%%share/papi/ftests/flops
+%%FTESTS%%share/papi/ftests/fmatrixlowpapi
+%%FTESTS%%share/papi/ftests/fmatrixpapi
+%%FTESTS%%share/papi/ftests/fmatrixpapi2
+%%FTESTS%%share/papi/ftests/fmultiplex1
+%%FTESTS%%share/papi/ftests/fmultiplex2
+%%FTESTS%%share/papi/ftests/highlevel
+%%FTESTS%%share/papi/ftests/johnmay2
+%%FTESTS%%share/papi/ftests/second
+%%FTESTS%%share/papi/ftests/strtest
+%%FTESTS%%share/papi/ftests/tenth
+%%FTESTS%%share/papi/ftests/zero
+%%FTESTS%%@dirrm share/papi/ftests
+%%CTESTS%%@dirrm share/papi/ctests
+%%CTESTS%%@dirrmtry share/papi
+%%FTESTS%%@dirrmtry share/papi