diff options
author | Guy Helmer <ghelmer@FreeBSD.org> | 1998-07-01 15:39:43 +0000 |
---|---|---|
committer | Guy Helmer <ghelmer@FreeBSD.org> | 1998-07-01 15:39:43 +0000 |
commit | 266e501e5dfc0afade882683adbd72c0f7451225 (patch) | |
tree | 8f2cb83ec662a844c418b83e4e05ca33d40318bd /cad | |
parent | Activate gxedit. (diff) |
Sis, a program suite for synthesis of sequential circuits.
PR: ports/5104
Submitted by: Frank Volf <volf@oasis.IAEhv.nl>
Notes
Notes:
svn path=/head/; revision=11640
Diffstat (limited to 'cad')
-rw-r--r-- | cad/sis/Makefile | 62 | ||||
-rw-r--r-- | cad/sis/distinfo | 2 | ||||
-rw-r--r-- | cad/sis/files/Makefile.FreeBSD | 47 | ||||
-rw-r--r-- | cad/sis/pkg-comment | 1 | ||||
-rw-r--r-- | cad/sis/pkg-descr | 26 | ||||
-rw-r--r-- | cad/sis/pkg-plist | 368 |
6 files changed, 506 insertions, 0 deletions
diff --git a/cad/sis/Makefile b/cad/sis/Makefile new file mode 100644 index 000000000000..4d851fa0bd60 --- /dev/null +++ b/cad/sis/Makefile @@ -0,0 +1,62 @@ +# New ports collection makefile for: sis +# Version required: 1.2 (pl1) +# Date created: 10 October 1997 +# Whom: volf@oasis.IAEhv.nl +# +# $Id$ +# + +DISTNAME= sis-1.2 +PKGNAME= sis-1.2.1 +CATEGORIES= cad +MASTER_SITES= ftp://ic.eecs.berkeley.edu/pub/Sis/ +EXTRACT_SUFX= .tar.Z + +PATCH_SITES= ftp://ic.eecs.berkeley.edu/pub/Sis/ +PATCHFILES= sis-1.2.patch1.Z +PATCH_DIST_STRIP= -p1 + +MAINTAINER= volf@oasis.IAEhv.nl + +MAKEFILE= Makefile.FreeBSD +MAN1= espresso.1 jedi.1 nova.1 sis.1 sred.1 stamina.1 \ + vst2blif.1 xsis.1 +MAN5= espresso.5 pla.5 + +pre-build: ${WRKSRC}/Makefile.FreeBSD + +${WRKSRC}/Makefile.FreeBSD: + ${CP} ${FILESDIR}/Makefile.FreeBSD ${WRKSRC} + +do-install: + ${INSTALL_PROGRAM} ${WRKSRC}/sis/sis ${PREFIX}/bin + ${INSTALL_PROGRAM} ${WRKSRC}/jedi/jedi ${PREFIX}/bin + ${INSTALL_PROGRAM} ${WRKSRC}/sred/sred ${PREFIX}/bin + ${INSTALL_PROGRAM} ${WRKSRC}/stamina/bin/stamina ${PREFIX}/bin + ${INSTALL_PROGRAM} ${WRKSRC}/nova/nova ${PREFIX}/bin + ${INSTALL_PROGRAM} ${WRKSRC}/espresso/espresso ${PREFIX}/bin + ${INSTALL_PROGRAM} ${WRKSRC}/vst2blif/vst2blif ${PREFIX}/bin + ${INSTALL_PROGRAM} ${WRKSRC}/blif2vst/blif2vst ${PREFIX}/bin + ${INSTALL_PROGRAM} ${WRKSRC}/xsis/xsis ${PREFIX}/bin + ${INSTALL_MAN} ${WRKSRC}/espresso/espresso.1 ${PREFIX}/man/man1 + ${INSTALL_MAN} ${WRKSRC}/jedi/jedi.1 ${PREFIX}/man/man1 + ${INSTALL_MAN} ${WRKSRC}/nova/nova.1 ${PREFIX}/man/man1 + ${INSTALL_MAN} ${WRKSRC}/sis/sis_lib/help/sis.1 ${PREFIX}/man/man1 + ${INSTALL_MAN} ${WRKSRC}/sred/sred.1 ${PREFIX}/man/man1 + ${INSTALL_MAN} ${WRKSRC}/stamina/stamina.1 ${PREFIX}/man/man1 + ${INSTALL_MAN} ${WRKSRC}/vst2blif/vst2blif.1 ${PREFIX}/man/man1 + ${INSTALL_MAN} ${WRKSRC}/xsis/xsis.1 ${PREFIX}/man/man1 + ${INSTALL_MAN} ${WRKSRC}/espresso/espresso.5 ${PREFIX}/man/man5 + ${INSTALL_MAN} ${WRKSRC}/espresso/pla.5 ${PREFIX}/man/man5 + ${MKDIR} ${PREFIX}/lib/sis + ${CP} -R ${WRKSRC}/sis/sis_lib ${PREFIX}/lib/sis + +.if !defined(NOPORTDOCS) +post-install: + ${INSTALL_DATA} ${WRKSRC}/SIS_paper.ps ${PREFIX}/lib/sis + ${INSTALL_DATA} ${WRKSRC}/RELEASE-NOTES-1.2 ${PREFIX}/lib/sis + ${GZIP_CMD} ${PREFIX}/lib/sis/SIS_paper.ps + chown -R bin:bin ${PREFIX}/lib/sis +.endif + +.include <bsd.port.mk> diff --git a/cad/sis/distinfo b/cad/sis/distinfo new file mode 100644 index 000000000000..e6da765e6a5e --- /dev/null +++ b/cad/sis/distinfo @@ -0,0 +1,2 @@ +MD5 (sis-1.2.tar.Z) = 4a6a427c2e10f166c6c080630713a016 +MD5 (sis-1.2.patch1.Z) = ea713114d925c04463b0ec87dad3ff57 diff --git a/cad/sis/files/Makefile.FreeBSD b/cad/sis/files/Makefile.FreeBSD new file mode 100644 index 000000000000..c5547f3fc20c --- /dev/null +++ b/cad/sis/files/Makefile.FreeBSD @@ -0,0 +1,47 @@ +# +# $Id$ +# + +MACHINE = FreeBSD +SRCDIR = ${.CURDIR} +X11 = /usr/X11R6 + +SIS = $(SRCDIR)/sis +CAD = $(SRCDIR)/cad +LIBDIR = $(PREFIX)/lib/sis + +CC = cc + +all: + cd sis; make -f Makefile.nooct SIS=$(SIS) LIBDIR=$(LIBDIR) CAD=$(CAD) CC=$(CC); cd .. + cd utility; make CAD=$(CAD) CC=$(CC) libutility.a; \ + mv libutility.a $(CAD)/lib; cd .. + cd options; make CAD=$(CAD) CC=$(CC) liboptions.a; \ + mv liboptions.a $(CAD)/lib; cd .. + cd jedi; make CAD=$(CAD) CC=$(CC); cd .. + cd espresso; make CAD=$(CAD) CC=$(CC); cd .. + cd nova; make CAD=$(CAD) SIS=$(SIS) CC=$(CC); cd .. + cd sred; make SIS=$(SIS) CC=$(CC); cd .. + cd stamina; make MACHINE=$(MACHINE) CC=$(CC) SIS=$(SIS); cd .. + cd vst2blif; make MACHINE=$(MACHINE) CC=$(CC); cd .. + cd blif2vst; make MACHINE=$(MACHINE) CC=$(CC); cd .. + cd xsis; make SIS=$(SIS) MACHINE=$(MACHINE) X11=$(X11) CC=$(CC); cd .. + +clean: + cd sis; make SIS=$(SIS) CAD=$(CAD) clean; cd .. + cd utility; make clean; cd .. + -rm $(CAD)/lib/libutility.a + cd options; make clean; cd .. + -rm $(CAD)/lib/liboptions.a + cd jedi; make clean; cd .. + cd stamina; make clean; cd .. + cd sred; make clean; cd .. + cd nova; make clean; cd .. + cd espresso; make clean; cd .. + cd vst2blif; make clean; cd .. + cd blif2vst; make clean; cd .. + cd xsis; make clean; cd .. + cd stamina; make cleanall; cd .. + cd sis; make strip_depend; rm -rf lib/*; cd .. + -rm -rf make.out Makefile + diff --git a/cad/sis/pkg-comment b/cad/sis/pkg-comment new file mode 100644 index 000000000000..8b60d794208f --- /dev/null +++ b/cad/sis/pkg-comment @@ -0,0 +1 @@ +Synthesis program for the synthesis of sequential circuits. diff --git a/cad/sis/pkg-descr b/cad/sis/pkg-descr new file mode 100644 index 000000000000..b3c673746884 --- /dev/null +++ b/cad/sis/pkg-descr @@ -0,0 +1,26 @@ +sis is an interactive program for the synthesis of both synchronous +and asynchronous sequential circuits. The input can be given in state +table format or as logical equations (for synchronous circuits), or +as a signal transition graph (for asynchronous circuits); a target +technology library is given in genlib format. The output is a netlist +of gates in the target technology. + +The system includes various capabilities that are controlled interactively +by the user. These include state minimization, state assignment, +optimization for area and delay using retiming, optimization using +standard algebraic and Boolean combinational techniques from MISII, +performance optimization using restructuring, and technology mapping +for optimal area and delay. Redundancy removal and 100% testability +are provided for combinational and scan-path circuits. Formal verification +is available for both combinational and sequential circuits, even for +circuits with different state encodings. + +This distribution contains sis, nova (state assignment), jedi (state +assignment), stamina (state minimization, from June Rho at University of +Colorado, Boulder), sred (state minimization), espresso, blif2vst (mapped +BLIF to structural VHDL translator), vst2blif (structural VHDL to BLIF +translator), xsis (a front-end graphical interface to sis) and several stripped +down packages from the OctTools (options, port, and utility) that are needed +for some of the programs listed above. + +Frank Volf, volf@oasis.IAEhv.nl diff --git a/cad/sis/pkg-plist b/cad/sis/pkg-plist new file mode 100644 index 000000000000..a263e99985d8 --- /dev/null +++ b/cad/sis/pkg-plist @@ -0,0 +1,368 @@ +bin/sis +bin/jedi +bin/sred +bin/stamina +bin/nova +bin/espresso +bin/vst2blif +bin/blif2vst +bin/xsis +lib/sis/sis_lib/help/print.1.orig +lib/sis/sis_lib/help/sis.1 +lib/sis/sis_lib/help/alias.1 +lib/sis/sis_lib/help/Makefile +lib/sis/sis_lib/help/_astg_cycle.1 +lib/sis/sis_lib/help/format +lib/sis/sis_lib/help/add_inverter.1 +lib/sis/sis_lib/help/astg_contract.1 +lib/sis/sis_lib/help/astg_current.1 +lib/sis/sis_lib/help/_astg_flow.1 +lib/sis/sis_lib/help/_astg_irred.1 +lib/sis/sis_lib/help/_astg_mgc.1 +lib/sis/sis_lib/help/astg_marking.1 +lib/sis/sis_lib/help/trail +lib/sis/sis_lib/help/_astg_smc.1 +lib/sis/sis_lib/help/astg_print_sg.1 +lib/sis/sis_lib/help/astg_syn.1 +lib/sis/sis_lib/help/astg_persist.1 +lib/sis/sis_lib/help/astg_slow.1 +lib/sis/sis_lib/help/act_map.fmt +lib/sis/sis_lib/help/astg_to_f.1 +lib/sis/sis_lib/help/astg_to_stg.1 +lib/sis/sis_lib/help/atpg.1 +lib/sis/sis_lib/help/bdsyn.1 +lib/sis/sis_lib/help/buffer_opt.1 +lib/sis/sis_lib/help/chng_clock.1 +lib/sis/sis_lib/help/chng_name.1 +lib/sis/sis_lib/help/collapse.1 +lib/sis/sis_lib/help/constraints.1 +lib/sis/sis_lib/help/decomp.1 +lib/sis/sis_lib/help/echo.1 +lib/sis/sis_lib/help/eliminate.1 +lib/sis/sis_lib/help/espresso.1 +lib/sis/sis_lib/help/extract_seq_dc.1 +lib/sis/sis_lib/help/factor.1 +lib/sis/sis_lib/help/fanout_alg.1 +lib/sis/sis_lib/help/fanout_param.1 +lib/sis/sis_lib/help/full_simplify.1 +lib/sis/sis_lib/help/fx.1 +lib/sis/sis_lib/help/gcx.1 +lib/sis/sis_lib/help/gkx.1 +lib/sis/sis_lib/help/help.1 +lib/sis/sis_lib/help/invert.1 +lib/sis/sis_lib/help/map.1 +lib/sis/sis_lib/help/.except +lib/sis/sis_lib/help/write_pds.1 +lib/sis/sis_lib/help/one_hot.1 +lib/sis/sis_lib/help/phase.1 +lib/sis/sis_lib/help/fx.fmt +lib/sis/sis_lib/help/plot_blif.1 +lib/sis/sis_lib/help/print.1 +lib/sis/sis_lib/help/print_altname.1 +lib/sis/sis_lib/help/print_clock.1 +lib/sis/sis_lib/help/print_delay.1 +lib/sis/sis_lib/help/print_factor.1 +lib/sis/sis_lib/help/print_gate.1 +lib/sis/sis_lib/help/header.me +lib/sis/sis_lib/help/print_io.1 +lib/sis/sis_lib/help/print_kernel.1 +lib/sis/sis_lib/help/print_latch.1 +lib/sis/sis_lib/help/print_level.1 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