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authorMikael Urankar <mikael@FreeBSD.org>2023-03-16 12:10:29 +0100
committerMikael Urankar <mikael@FreeBSD.org>2023-03-16 12:11:52 +0100
commitebf29acc6ce4942cbc6ee75d81b6b97391e4371f (patch)
treed332496299a32abaf3f793fa38f7115b5240e263 /cad/veryl
parentlang/rust: Update to 1.68.0 (diff)
lang/rust: Bump revisions after 1.68.0
PR: 270080
Diffstat (limited to 'cad/veryl')
-rw-r--r--cad/veryl/Makefile1
1 files changed, 1 insertions, 0 deletions
diff --git a/cad/veryl/Makefile b/cad/veryl/Makefile
index 2cbdbfa0eb3e..8ae39678de62 100644
--- a/cad/veryl/Makefile
+++ b/cad/veryl/Makefile
@@ -1,6 +1,7 @@
PORTNAME= veryl
DISTVERSIONPREFIX= veryl-v
DISTVERSION= 0.5.5
+PORTREVISION= 1
CATEGORIES= cad
MAINTAINER= yuri@FreeBSD.org