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authorWill Andrews <will@FreeBSD.org>2003-05-17 03:17:55 +0000
committerWill Andrews <will@FreeBSD.org>2003-05-17 03:17:55 +0000
commit158f9c87d6c3cb1ceeefc366b6858f52e72e5210 (patch)
tree1ce05a849136455113333d0f2e199e5323a85dea /cad/iverilog/Makefile
parent- update to 1.2.3 (diff)
Fix MAN. This commit completes changes submitted in the PR. I made
the earlier changes unaware that the submitter had sent the PR. PR: 51989 Submitted by: Ports Fury
Notes
Notes: svn path=/head/; revision=81135
Diffstat (limited to 'cad/iverilog/Makefile')
-rw-r--r--cad/iverilog/Makefile7
1 files changed, 3 insertions, 4 deletions
diff --git a/cad/iverilog/Makefile b/cad/iverilog/Makefile
index da95c1926c41..e441e1a25f97 100644
--- a/cad/iverilog/Makefile
+++ b/cad/iverilog/Makefile
@@ -13,13 +13,12 @@ MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v${PORTVERSION}/
DISTNAME= verilog-${PORTVERSION}
MAINTAINER= keichii@FreeBSD.org
-COMMENT= Icarus Verilog is a Verilog simulation and synthesis tool
-
-GNU_CONFIGURE= yes
+COMMENT= A Verilog simulation and synthesis tool
USE_BISON= yes
USE_GMAKE= yes
+GNU_CONFIGURE= yes
-MAN1= iverilog.1 vvp.1
+MAN1= iverilog-vpi.1 iverilog.1 vvp.1
.include <bsd.port.mk>