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authorYing-Chieh Liao <ijliao@FreeBSD.org>2002-02-07 07:07:48 +0000
committerYing-Chieh Liao <ijliao@FreeBSD.org>2002-02-07 07:07:48 +0000
commit845950814a0fdca28b020afaba1e9225780f16ad (patch)
treeef0b26df9e69a351b23f460e68df4c07860efbfa /cad/Makefile
parentUpdate to 2.0 (diff)
add gnucap 0.30
The Gnu Circuit Analysis Package
Notes
Notes: svn path=/head/; revision=54293
Diffstat (limited to 'cad/Makefile')
-rw-r--r--cad/Makefile1
1 files changed, 1 insertions, 0 deletions
diff --git a/cad/Makefile b/cad/Makefile
index 866f72b5f129..1d6963896583 100644
--- a/cad/Makefile
+++ b/cad/Makefile
@@ -9,6 +9,7 @@
SUBDIR += geda
SUBDIR += geda-symbols
SUBDIR += gnetlist
+ SUBDIR += gnucap
SUBDIR += gschem
SUBDIR += irsim
SUBDIR += iverilog