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authorStanislav Sedov <stas@FreeBSD.org>2009-01-12 09:44:37 +0000
committerStanislav Sedov <stas@FreeBSD.org>2009-01-12 09:44:37 +0000
commit08a7bacf70a5d5cb1d347b59656f36e2389941bd (patch)
tree5ce9d90c6c3d7cf539c37c7e35e624d964c2dedc /cad/Makefile
parent- Take maintainership. (diff)
- Add port for verilog-mode.el, Emacs Verilog editing mode.
WWW: http://www.veripool.org/wiki/verilog-mode
Notes
Notes: svn path=/head/; revision=225826
Diffstat (limited to 'cad/Makefile')
-rw-r--r--cad/Makefile1
1 files changed, 1 insertions, 0 deletions
diff --git a/cad/Makefile b/cad/Makefile
index 4d3739b15038..767c85da2c1e 100644
--- a/cad/Makefile
+++ b/cad/Makefile
@@ -82,6 +82,7 @@
SUBDIR += tochnog
SUBDIR += transcalc
SUBDIR += varkon
+ SUBDIR += verilog-mode.el
SUBDIR += vipec
SUBDIR += xcircuit
SUBDIR += z88