diff -ruN linux-mips/include/asm-mips/betty.h linux-vr/include/asm-mips/betty.h
--- linux-mips/include/asm-mips/betty.h	Wed Dec 31 16:00:00 1969
+++ linux-vr/include/asm-mips/betty.h	Tue May  2 07:28:47 2000
@@ -0,0 +1,170 @@
+/* $Id: betty.h,v 1.1 2000/05/02 14:28:47 nop Exp $
+ *
+ * Definitions for "Betty" companion chip (audio/telecom/touch panel)
+ * for the r39xx processors.  Known as the Toshiba TC35143F or Philips UCB1200.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __BETTY_H__
+#define __BETTY_H__
+
+
+#define BIT(x)	(1 << x)
+
+
+/* Registers */
+
+#define BETTY_REG_IO_PORT_DATA                 0
+#define BETTY_REG_IO_PORT_DIRECTION            1
+#define BETTY_REG_RISING_INT_ENABLE            2
+#define BETTY_REG_FALLING_INT_ENABLE           3
+#define BETTY_REG_INT_CLEAR_STATUS             4
+#define BETTY_REG_TEL_CTRL_A                   5
+#define BETTY_REG_TEL_CTRL_B                   6
+#define BETTY_REG_AUD_CTRL_A                   7
+#define BETTY_REG_AUD_CTRL_B                   8
+#define BETTY_REG_TOUCHSCREEN_CTRL             9
+#define BETTY_REG_ADC_CTRL                     10
+#define BETTY_REG_ADC_DATA                     11
+#define BETTY_REG_ID                           12
+#define BETTY_REG_MODE                         13
+
+/* 0 - I/O port data register */
+
+#define BETTY_IO_DATA_MASK            0x03ff
+#define BETTY_IO_DATA_SHIFT           0
+
+/* 1 - I/O port direction register */
+
+#define BETTY_IO_DIR_MASK             0x03ff
+#define BETTY_IO_DIR_SHIFT            0
+#define BETTY_SIB_ZERO                BIT(15)
+
+/* 2 - Rising edge interrupt enable register */
+
+#define BETTY_IO_RIS_INT_MASK         0x03ff
+#define BETTY_IO_RIS_INT_SHIFT        0
+#define BETTY_ADC_RIS_INT             BIT(11)
+#define BETTY_TSPX_RIS_INT            BIT(12)
+#define BETTY_TSMX_RIS_INT            BIT(13)
+#define BETTY_TCLIP_RIS_INT           BIT(14)
+#define BETTY_ACLIP_RIS_INT           BIT(15)
+
+/* 3 - Falling edge interrupt enable register */
+
+#define BETTY_IO_FAL_INT_MASK         0x03ff
+#define BETTY_IO_FAL_INT_SHIFT        0
+#define BETTY_ADC_FAL_INT             BIT(11)
+#define BETTY_TSPX_FAL_INT            BIT(12)
+#define BETTY_TSMX_FAL_INT            BIT(13)
+#define BETTY_TCLIP_FAL_INT           BIT(14)
+#define BETTY_ACLIP_FAL_INT           BIT(15)
+
+/* 4 - Interrupt clear/status register */
+
+#define BETTY_IO_INT_MASK             0x03ff
+#define BETTY_IO_INT_SHIFT            0
+#define BETTY_ADC_INT                 BIT(11)
+#define BETTY_TSPX_INT                BIT(12)
+#define BETTY_TSMX_INT                BIT(13)
+#define BETTY_TCLIP_INT               BIT(14)
+#define BETTY_ACLIP_INT               BIT(15)
+
+/* 5 - Telecom control register A */
+
+#define BETTY_TEL_DIV_MASK            0x007f
+#define BETTY_TEL_DIV_SHIFT           0
+#define BETTY_TEL_LOOP                BIT(7)
+
+/* 6 - Telecom control register B */
+
+#define BETTY_TEL_VOICE_ENA           BIT(3)
+#define BETTY_TEL_CLIP_DETECT         BIT(4)
+#define BETTY_TEL_ATT                 BIT(6)
+#define BETTY_TEL_SIDE_ENA            BIT(11)
+#define BETTY_TEL_MUTE                BIT(13)
+#define BETTY_TEL_IN_ENA              BIT(14)
+#define BETTY_TEL_OUT_ENA             BIT(15)
+
+/* 7 - Audio control register A */
+
+#define BETTY_AUD_DIV_MASK            0x007f
+#define BETTY_AUD_DIV_SHIFT           0
+#define BETTY_AUD_GAIN_MASK           0x0f80
+#define BETTY_AUD_GAIN_SHIFT          7
+
+/* 8 - Audio control register B */
+
+#define BETTY_AUD_ATT_MASK            0x001f
+#define BETTY_AUD_ATT_SHIFT           0
+#define BETTY_AUD_CLIP_DETECT         BIT(6)
+#define BETTY_AUD_LOOP                BIT(8)
+#define BETTY_AUD_MUTE                BIT(13)
+#define BETTY_AUD_IN_ENA              BIT(14)
+#define BETTY_AUD_OUT_ENA             BIT(15)
+
+/* 9 - Touch screen control register */
+
+#define BETTY_TSMX_POW                BIT(0)
+#define BETTY_TSPX_POW                BIT(1)
+#define BETTY_TSMY_POW                BIT(2)
+#define BETTY_TSPY_POW                BIT(3)
+#define BETTY_TSMX_GND                BIT(4)
+#define BETTY_TSPX_GND                BIT(5)
+#define BETTY_TSMY_GND                BIT(6)
+#define BETTY_TSPY_GND                BIT(7)
+#define BETTY_TSC_MODE_MASK           (BIT(8) | BIT(9))
+#define BETTY_TSC_MODE_SHIFT          8
+#define BETTY_TSC_BIAS_ENA            BIT(11)
+#define BETTY_TSPX_LOW                BIT(12)
+#define BETTY_TSMX_LOW                BIT(13)
+
+/* 10 - ADC control register */
+
+#define BETTY_ADC_SYNC_ENA            BIT(0)
+#define BETTY_VREFBYP_CON             BIT(1)
+#define BETTY_ADC_INPUT_MASK          (BIT(2) | BIT(3) | BIT(4))
+#define BETTY_ADC_INPUT_SHIFT         2
+#define BETTY_ADC_INPUT_TSPX          0
+#define BETTY_ADC_INPUT_TSMX          1
+#define BETTY_ADC_INPUT_TSPY          2
+#define BETTY_ADC_INPUT_TSMY          3
+#define BETTY_ADC_INPUT_AD0           4
+#define BETTY_ADC_INPUT_AD1           5
+#define BETTY_ADC_INPUT_AD2           6
+#define BETTY_ADC_INPUT_AD3           7
+#define BETTY_EXT_REF_ENA             BIT(5)
+#define BETTY_ADC_START               BIT(7)
+#define BETTY_ADC_ENA                 BIT(15)
+
+/* 11 - ADC data register */
+
+#define BETTY_ADC_DATA_MASK           0x7fe0
+#define BETTY_ADC_DATA_SHIFT          5
+#define BETTY_ADC_DAT_VAL             BIT(15)
+
+/* 12 - ID register */
+
+#define BETTY_VERSION_MASK            0x003f
+#define BETTY_VERSION_SHIFT           0
+#define BETTY_DEVICE_MASK             0x0fc0
+#define BETTY_DEVICE_SHIFT            6
+#define BETTY_SUPPLIER_MASK           0xf000
+#define BETTY_SUPPLIER_SHIFT          12
+
+/* 13 - Mode register */
+
+#define BETTY_AUD_TEST                BIT(0)
+#define BETTY_TEL_TEST                BIT(1)
+#define BETTY_PROD_TEST_MODE          (BIT(2) | BIT(3) | BIT(4))
+#define BETTY_DYN_VFLAG_ENA           BIT(12)
+#define BETTY_AUD_OFF_CAN             BIT(13)
+
+/* 14 - Reserved */
+
+/* 15 - Null Register - Returns 0xffff */
+
+#endif __BETTY_H__
diff -ruN linux-mips/include/asm-mips/bootinfo.h linux-vr/include/asm-mips/bootinfo.h
--- linux-mips/include/asm-mips/bootinfo.h	Fri Nov 10 00:11:41 2000
+++ linux-vr/include/asm-mips/bootinfo.h	Sun Nov 12 12:33:02 2000
@@ -24,9 +24,13 @@
 #define MACH_GROUP_BAGET	9 /* Baget */
 #define MACH_GROUP_ORION       10 /* CoSine Orion */
 #define MACH_GROUP_GALILEO     11 /* Galileo Eval Boards*/
+#define MACH_GROUP_VR41XX      12 /* NEC VR41XX-based, mostly PDAs and handhelds */
+#define MACH_GROUP_R39XX       13 /* Toshiba R39XX / Philips Poseidon based */
 
 #define GROUP_NAMES { "unknown", "Jazz", "Digital", "ARC", \
-                      "SNI", "ACN", "SGI", "Cobalt", "NEC DDB", "Baget", "Orion", "Galileo" }
+                      "SNI", "ACN", "SGI", "Cobalt", "NEC DDB", "Baget", "Orion", "Galileo" , \
+                      "VR41XX", "R39XX" \
+}
 
 /*
  * Valid machtype values for group unknown (low order halfword of mips_machtype)
@@ -108,6 +112,65 @@
 #define GROUP_NEC_DDB_NAMES { "Vrc-5074", "Vrc-5476"}
 
 /*
+ * Valid machtype for MACH_GROUP_VR41XX
+ */
+#define MACH_VR41XX_UNKNOWN            0
+#define MACH_VR41XX_VADEM_CLIO_1000    1
+#define MACH_VR41XX_CASIO_E105         2
+#define MACH_VR41XX_EVEREX_FREESTYLE   3
+#define MACH_CASIO_E10                 4
+#define MACH_CASIO_E15                 5
+#define MACH_NEC_MOBILEPRO_700         6
+#define MACH_NEC_MOBILEPRO_750C        7
+#define MACH_NEC_MOBILEPRO_770         8
+#define MACH_NEC_MOBILEPRO_800         9
+#define MACH_NEC_MOBILEGEAR2_R300     10
+#define MACH_NEC_MOBILEGEAR2_R320     11
+#define	MACH_NEC_MOBILEGEAR2_R430     12
+#define	MACH_NEC_MOBILEGEAR2_R500     13
+#define	MACH_NEC_MOBILEGEAR2_R510     14
+#define	MACH_NEC_MOBILEGEAR2_R520     15
+#define	MACH_NEC_MOBILEGEAR2_R530     16
+#define	MACH_NEC_MOBILEGEAR2_R700     17
+#define MACH_NEC_OSPREY               18
+#define MACH_NEC_UEB30                19
+#define MACH_VR41XX_VADEM_CLIO_1050   20
+#define MACH_VR41XX_COMPAQ_AERO_21XX  21
+#define MACH_VR41XX_COMPAQ_AERO_15XX  22
+#define MACH_VR41XX_IBM_WORKPAD_Z50   23
+#define MACH_VR41XX_AGENDA_VR3        24
+#define MACH_DOCOMO_SIGMARION         25
+#define MACH_NEC_HARRIER	      26
+#define MACH_VR41XX_CASIO_E125        27
+
+#define GROUP_VR41XX_NAMES { \
+	"unknown", "Vadem Clio", "Casio E-105", \
+	"Everex Freestyle", "Casio E-10", "Casio E-15", "NEC MobilePro 700", \
+	"NEC MobilePro 750C", "NEC MobilePro 770", "NEC MobilePro 800", \
+	"NEC MobileGear2 R300", "NEC MobileGear2 R320", \
+	"NEC MobileGear2 R430", "NEC MobileGear2 R500", \
+	"NEC MobileGear2 R510", "NEC MobileGear2 R520", \
+	"NEC MobileGear2 R530", "NEC MobileGear2 R700", \
+	"NEC Osprey", "NEC Eval Rev30", "Vadem Clio 1050", \
+	"Compaq Aero 21XX", "Compaq Aero 15XX", "IBM Workpad z50", \
+	"Agenda VR3", "DoCoMo sigmarion", "NEC Harrier", "Casio E-125" \
+}
+
+/*
+ * Valid machtype for MACH_GROUP_R39XX
+ */
+#define MACH_R39XX_UNKNOWN            0
+#define MACH_R39XX_PHILIPS_NINO       1
+#define MACH_R39XX_SHARP_MOBILON      2
+#define MACH_R39XX_COMPAQ	      3
+#define MACH_R39XX_VTECH_HELIO        4
+#define MACH_R39XX_PHILIPS_VELO       5
+
+#define GROUP_R39XX_NAMES { \
+	"unknown", "Philips Nino", "Sharp Mobilon", "Compaq 8XX/201X", "VTech Helio", "Philips Velo" \
+}
+
+/*
  * Valid machtype for group BAGET
  */
 #define MACH_BAGET201		0	/* BT23-201 */
@@ -155,15 +218,19 @@
 #define CPU_NEVADA		27	/* RM5230, RM5260 */
 #define CPU_RM7000		28
 #define CPU_R5432               29
-#define CPU_LAST		29
+#define CPU_VR41XX		30
+#define CPU_R3912		31
+#define CPU_LAST		31
 
 #define CPU_NAMES { "unknown", "R2000", "R3000", "R3000A", "R3041", "R3051", \
         "R3052", "R3081", "R3081E", "R4000PC", "R4000SC", "R4000MC",         \
         "R4200", "R4400PC", "R4400SC", "R4400MC", "R4600", "R6000",          \
         "R6000A", "R8000", "R10000", "R4300", "R4650", "R4700", "R5000",     \
-        "R5000A", "R4640", "Nevada", "RM7000", "R5432" }
+        "R5000A", "R4640", "Nevada", "RM7000", "R5432" , \
+        "VR41XX", "R39XX" }
 
-#define CL_SIZE      (80)
+/* Linux VR needs more than 80. */
+#define CL_SIZE      256
 
 #ifndef _LANGUAGE_ASSEMBLY
 
diff -ruN linux-mips/include/asm-mips/cpu.h linux-vr/include/asm-mips/cpu.h
--- linux-mips/include/asm-mips/cpu.h	Fri Nov 10 00:11:41 2000
+++ linux-vr/include/asm-mips/cpu.h	Sun Nov 12 12:33:02 2000
@@ -24,12 +24,14 @@
 #define PRID_IMP_R4700    0x2100
 #define PRID_IMP_R4640    0x2200
 #define PRID_IMP_R4650    0x2200		/* Same as R4640 */
+#define PRID_IMP_R3912    0x2200
 #define PRID_IMP_R5000    0x2300
 #define PRID_IMP_R5432    0x5400
 #define PRID_IMP_SONIC    0x2400
 #define PRID_IMP_MAGIC    0x2500
 #define PRID_IMP_RM7000   0x2700
 #define PRID_IMP_NEVADA   0x2800		/* RM5260 ??? */
+#define PRID_IMP_VR41XX   0x0c00
 
 #define PRID_IMP_UNKNOWN  0xff00
 
diff -ruN linux-mips/include/asm-mips/dma.h linux-vr/include/asm-mips/dma.h
--- linux-mips/include/asm-mips/dma.h	Tue Apr 11 20:57:09 2000
+++ linux-vr/include/asm-mips/dma.h	Thu Nov 23 15:03:56 2000
@@ -83,7 +83,12 @@
  * Deskstations or Acer PICA but not the much more versatile DMA logic used
  * for the local devices on Acer PICA or Magnums.
  */
+#ifdef CONFIG_CPU_VR41XX
+/* VR41xx DMA can transfer under first 32MB physical memory area */
+#define MAX_DMA_ADDRESS		(PAGE_OFFSET + 0x02000000)
+#else
 #define MAX_DMA_ADDRESS		(PAGE_OFFSET + 0x01000000)
+#endif
 
 /* 8237 DMA controllers */
 #define IO_DMA1_BASE	0x00	/* 8 bit slave DMA, channels 0..3 */
diff -ruN linux-mips/include/asm-mips/elf.h linux-vr/include/asm-mips/elf.h
--- linux-mips/include/asm-mips/elf.h	Wed Jul 12 23:25:03 2000
+++ linux-vr/include/asm-mips/elf.h	Sun Nov 12 12:33:02 2000
@@ -28,8 +28,6 @@
 	if ((__h->e_machine != EM_MIPS) &&				\
 	    (__h->e_machine != EM_MIPS_RS4_BE))				\
 		__res = 0;						\
-	if (__h->e_flags & EF_MIPS_ARCH)				\
-		__res = 0;						\
 									\
 	__res;								\
 })
diff -ruN linux-mips/include/asm-mips/fpu_emulator.h linux-vr/include/asm-mips/fpu_emulator.h
--- linux-mips/include/asm-mips/fpu_emulator.h	Wed Dec 31 16:00:00 1969
+++ linux-vr/include/asm-mips/fpu_emulator.h	Tue Apr 25 08:00:22 2000
@@ -0,0 +1,44 @@
+/*
+ * Definitiona for the Algorithmics FPU Emulator port into MIPS Linux
+ */
+/**************************************************************************
+ *
+ *  include/asm-mips/fpu_emulator.h
+ *
+ *  Kevin D. Kissell, kevink@acm.org
+ *  Copyright (C) 1999 MIPS Technologies, Inc.  All rights reserved.
+ *
+ * ########################################################################
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ *************************************************************************/
+/* 
+ * Further private data for which no space exists in mips_fpu_soft_struct.
+ * This should be subsumed into the mips_fpu_soft_struct structure as
+ * defined in processor.h as soon as the absurd wired absolute assembler
+ * offsets become dynamic at compile time.
+ */
+
+struct mips_fpu_emulator_private {
+        unsigned int eir;
+        struct {
+                unsigned int emulated;
+                unsigned int loads;
+                unsigned int stores;
+                unsigned int cp1ops;
+                unsigned int cp1xops;
+                unsigned int errors;
+        } stats;
+};
diff -ruN linux-mips/include/asm-mips/inst.h linux-vr/include/asm-mips/inst.h
--- linux-mips/include/asm-mips/inst.h	Thu Dec  9 21:03:20 1999
+++ linux-vr/include/asm-mips/inst.h	Tue Apr 25 20:20:34 2000
@@ -21,7 +21,7 @@
 	cop0_op, cop1_op, cop2_op, cop1x_op,
 	beql_op, bnel_op, blezl_op, bgtzl_op,
 	daddi_op, daddiu_op, ldl_op, ldr_op,
-	major_1c_op, major_1d_op, major_1e_op, major_1f_op,
+	major_1c_op, jalx_op, major_1e_op, major_1f_op,
 	lb_op, lh_op, lwl_op, lw_op,
 	lbu_op, lhu_op, lwr_op, lwu_op,
 	sb_op, sh_op, swl_op, sw_op,
@@ -80,6 +80,15 @@
 };
 
 /*
+ * rt field of cop.bc_op opcodes
+ */
+
+enum bcop_op {
+	bcf_op, bct_op, bcfl_op, bctl_op
+};
+
+
+/*
  * func field of cop0 coi opcodes.
  */
 enum cop0_coi_func {
@@ -147,6 +156,73 @@
 	madd_op      = 0x08, msub_op      = 0x0a,
 	nmadd_op     = 0x0c, nmsub_op     = 0x0e
 };
+
+/*
+ * Previous versions of this file used bitfields to
+ * decode MIPS instruction. This has been shown
+ * to be non-portable, particularly across little-endian
+ * compilers.
+ *
+ * These macros allow extraction of one of the above
+ * enum values from a MIPS instruction as fetched from
+ * memory.
+ */
+
+/* In case some other massaging is needed, keep MIPSInst as wrapper */
+
+#define MIPSInst(x) x
+
+#define I_OPCODE_SFT	26
+#define MIPSInst_OPCODE(x) (MIPSInst(x) >> I_OPCODE_SFT)
+
+#define I_JTARGET_SFT	0
+#define MIPSInst_JTARGET(x) (MIPSInst(x) & 0x03ffffff)
+
+#define I_RS_SFT	21
+#define MIPSInst_RS(x) ((MIPSInst(x) & 0x03e00000) >> I_RS_SFT)
+
+#define I_RT_SFT	16
+#define MIPSInst_RT(x) ((MIPSInst(x) & 0x001f0000) >> I_RT_SFT)
+
+#define I_IMM_SFT	0
+#define MIPSInst_SIMM(x) ((int)((short)(MIPSInst(x) & 0xffff)))
+#define MIPSInst_UIMM(x) (MIPSInst(x) & 0xffff)
+
+#define I_CACHEOP_SFT	18
+#define MIPSInst_CACHEOP(x) ((MIPSInst(x) & 0x001c0000) >> I_CACHEOP_SFT)
+
+#define I_CACHESEL_SFT	16
+#define MIPSInst_CACHESEL(x) ((MIPSInst(x) & 0x00030000) >> I_CACHESEL_SFT)
+
+#define I_RD_SFT	11
+#define MIPSInst_RD(x) ((MIPSInst(x) & 0x0000f800) >> I_RD_SFT)
+
+#define I_RE_SFT	6
+#define MIPSInst_RE(x) ((MIPSInst(x) & 0x000007c0) >> I_RE_SFT)
+
+#define I_FUNC_SFT	0
+#define MIPSInst_FUNC(x) (MIPSInst(x) & 0x0000003f)
+
+#define I_FFMT_SFT	21
+#define MIPSInst_FFMT(x) ((MIPSInst(x) & 0x01e00000) >> I_FFMT_SFT)
+
+#define I_FT_SFT	16
+#define MIPSInst_FT(x) ((MIPSInst(x) & 0x001f0000) >> I_FT_SFT)
+
+#define I_FS_SFT	11
+#define MIPSInst_FS(x) ((MIPSInst(x) & 0x0000f800) >> I_FS_SFT)
+
+#define I_FD_SFT	6
+#define MIPSInst_FD(x) ((MIPSInst(x) & 0x000007c0) >> I_FD_SFT)
+
+#define I_FR_SFT	21
+#define MIPSInst_FR(x) ((MIPSInst(x) & 0x03e00000) >> I_FR_SFT)
+
+#define I_FMA_FUNC_SFT	2
+#define MIPSInst_FMA_FUNC(x) ((MIPSInst(x) & 0x0000003c) >> I_FMA_FUNC_SFT)
+
+#define I_FMA_FFMT_SFT	0
+#define MIPSInst_FMA_FFMT(x) (MIPSInst(x) & 0x00000003)
 
 /*
  * Damn ...  bitfields depend from byteorder :-(
diff -ruN linux-mips/include/asm-mips/io.h linux-vr/include/asm-mips/io.h
--- linux-mips/include/asm-mips/io.h	Fri Nov 10 00:11:47 2000
+++ linux-vr/include/asm-mips/io.h	Thu Nov 23 15:03:51 2000
@@ -13,6 +13,10 @@
 
 /*
  * Slowdown I/O port space accesses for antique hardware.
+ *	
+ * Notice: just because this is mips you can't assume it has no broken
+ * hardware. For example I've just inserted pcmcia ne2k into my 
+ * philips velo. Ouch.
  */
 #undef CONF_SLOWDOWN_IO
 
@@ -48,34 +52,19 @@
  * instruction, so the lower 16 bits must be zero.  Should be true on
  * on any sane architecture; generic code does not use this assumption.
  */
-extern unsigned long mips_io_port_base;
 
-/*
- * Thanks to James van Artsdalen for a better timing-fix than
- * the two short jumps: using outb's to a nonexistent port seems
- * to guarantee better timings even on fast machines.
- *
- * On the other hand, I'd like to be sure of a non-existent port:
- * I feel a bit unsafe about using 0x80 (should be safe, though)
- *
- *		Linus
- *
- */
+#include <asm/delay.h>
 
+extern unsigned long mips_io_port_base;
 #define __SLOW_DOWN_IO \
-	__asm__ __volatile__( \
-		"sb\t$0,0x80(%0)" \
-		: : "r" (mips_io_port_base));
+	{ int i; for (i=0; i<100; i++) barrier(); }
 
-#ifdef CONF_SLOWDOWN_IO
 #ifdef REALLY_SLOW_IO
 #define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; }
 #else
 #define SLOW_DOWN_IO __SLOW_DOWN_IO
 #endif
-#else
-#define SLOW_DOWN_IO
-#endif
+
 
 /*
  * Change virtual addresses to physical addresses and vv.
@@ -91,11 +80,10 @@
 	return (void *)KSEG0ADDR(address);
 }
 
-extern void * ioremap(unsigned long phys_addr, unsigned long size);
-extern void iounmap(void *addr);
-
 /*
  * IO bus memory addresses are also 1:1 with the physical address
+ * Note: These functions are only to be used to translate between
+ * bus and vitual for system RAM, not for shared peripheral RAM
  */
 extern inline unsigned long virt_to_bus(volatile void * address)
 {
@@ -114,11 +102,6 @@
 extern unsigned long isa_slot_offset;
 
 /*
- * readX/writeX() are used to access memory mapped devices. On some
- * architectures the memory mapped IO stuff needs to be accessed
- * differently. On the x86 architecture, we just read/write the
- * memory location directly.
- *
  * On MIPS, we have the whole physical address space mapped at all
  * times, so "ioremap()" and "iounmap()" do not need to do anything.
  * (This isn't true for all machines but we still handle these cases
@@ -126,10 +109,33 @@
  *
  * We cheat a bit and always return uncachable areas until we've fixed
  * the drivers to handle caching properly.
+ *
+ * Note that although the return value of these functions looks like a
+ * virtual address (and is used as such by read/write[bwl]), it cannot
+ * simply be used as such, but must only be used with read/write[bwl]()
+ * or mem*io(), below.
+ *
+ * The offset argument is supposedly a bus address, but we mask off the
+ * non-significant bits because sometimes they contain extra information
+ * (for systems with multiple PCI busses, at least).
  */
 extern inline void * ioremap(unsigned long offset, unsigned long size)
 {
+#ifdef CONFIG_CPU_VR4122
+	return (void *) KSEG1ADDR(offset);
+#else
+#ifdef CONFIG_ISA
+	return (void *)(isa_slot_offset + (offset & 0x03ffffff));
+#ifdef CONFIG_PCI
+#error "using ISA mapping for PCI bus addresses, that's just wrong"
+#endif
+#else
 	return (void *) KSEG1ADDR(offset);
+#if 0 // I'm silencing this warning, because it makes r39xx compiles annoying
+#warning "using 1:1 bus to pyhsical mapping, not sure if that's right"
+#endif
+#endif
+#endif
 }
 
 /*
@@ -139,7 +145,21 @@
  */
 extern inline void * ioremap_nocache (unsigned long offset, unsigned long size)
 {
+#ifdef CONFIG_CPU_VR4122
 	return (void *) KSEG1ADDR(offset);
+#else
+#ifdef CONFIG_ISA
+	return (void *) KSEG1ADDR(isa_slot_offset + (offset & 0x03ffffff));
+#ifdef CONFIG_PCI
+#error "using ISA mapping for PCI bus addresses, that's just wrong"
+#endif
+#else
+	return (void *) KSEG1ADDR(offset);
+#if 0 // this one too - note that these do need to be addressed for non-isa
+#warning "using 1:1 bus to pyhsical mapping, not sure if that's right"
+#endif
+#endif
+#endif
 }
 
 extern inline void iounmap(void *addr)
@@ -147,10 +167,17 @@
 }
 
 /*
- * XXX We need system specific versions of these to handle EISA address bits
- * 24-31 on SNI.
- * XXX more SNI hacks.
+ * readX/writeX() are used to access memory mapped devices. Some architectures
+ * require special handling for this, but MIPS can just read/write the memory
+ * location directly.
+ *
+ * Note that the argument to these is niether a virtual addresses, a physical
+ * addresses, nor a bus addresses.  The address argument is a "ioremap cookie",
+ * (cleverly disguised as a virtual address) as returned by ioremap().  The
+ * return value of ioremap() should never be used directly and nothing but the
+ * return value of ioremap() should be used with readX/writeX (or memXio).
  */
+
 #define readb(addr) (*(volatile unsigned char *)(addr))
 #define readw(addr) (*(volatile unsigned short *)(addr))
 #define readl(addr) (*(volatile unsigned int *)(addr))
@@ -169,28 +196,21 @@
 #define memcpy_fromio(a,b,c)	memcpy((a),(void *)(b),(c))
 #define memcpy_toio(a,b,c)	memcpy((void *)(a),(b),(c))
 
-/* END SNI HACKS ... */
-
 /*
- * ISA space is 'always mapped' on currently supported MIPS systems, no need
- * to explicitly ioremap() it. The fact that the ISA IO space is mapped
- * to PAGE_OFFSET is pure coincidence - it does not mean ISA values
- * are physical addresses. The following constant pointer can be
- * used as the IO-area pointer (it can be iounmapped as well, so the
- * analogy with PCI is quite large):
- */
-#define __ISA_IO_base ((char *)(PAGE_OFFSET))
-
-#define isa_readb(a) readb(a)
-#define isa_readw(a) readw(a)
-#define isa_readl(a) readl(a)
-#define isa_writeb(b,a) writeb(b,a)
-#define isa_writew(w,a) writew(w,a)
-#define isa_writel(l,a) writel(l,a)
-
-#define isa_memset_io(a,b,c)     memset_io((a),(b),(c))
-#define isa_memcpy_fromio(a,b,c) memcpy_fromio((a),(b),(c))
-#define isa_memcpy_toio(a,b,c)   memcpy_toio((a),(b),(c))
+ * These are for convenience porting old ISA drivers, as an alternative to
+ * adding a call to ioremap().  The proper thing to do is use ioremap(),
+ * these are here mostly becuase they're easy to implement.
+ */
+
+#define isa_readb(a) readb(isa_slot_offset + (a))
+#define isa_readw(a) readw(isa_slot_offset + (a))
+#define isa_readl(a) readl(isa_slot_offset + (a))
+#define isa_writeb(b,a) writeb(b,isa_slot_offset + (a))
+#define isa_writew(w,a) writew(w,isa_slot_offset + (a))
+#define isa_writel(l,a) writel(l,isa_slot_offset + (a))
+#define isa_memset_io(a,b,c)		memset_io(isa_slot_offset + (a),(b),(c))
+#define isa_memcpy_fromio(a,b,c)	memcpy_fromio((a),isa_slot_offset + (b),(c))
+#define isa_memcpy_toio(a,b,c)		memcpy_toio(isa_slot_offset + (a),(b),(c)
 
 /*
  * We don't have csum_partial_copy_fromio() yet, so we cheat here and
@@ -465,7 +485,11 @@
 	__insl((port),(addr),(count)))
 #endif
 
+#ifdef CONFIG_CPU_VR4122
+#define IO_SPACE_LIMIT 0xffffffff
+#else
 #define IO_SPACE_LIMIT 0xffff
+#endif
 
 /*
  * The caches on some architectures aren't dma-coherent and have need to
diff -ruN linux-mips/include/asm-mips/isadep.h linux-vr/include/asm-mips/isadep.h
--- linux-mips/include/asm-mips/isadep.h	Tue Apr 11 20:57:14 2000
+++ linux-vr/include/asm-mips/isadep.h	Tue Sep 19 07:39:30 2000
@@ -12,7 +12,7 @@
 #ifndef __ASM_MIPS_ISADEP_H
 #define __ASM_MIPS_ISADEP_H
 
-#if defined(CONFIG_CPU_R3000)
+#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_R39XX)
 /*
  * R2000 or R3000
  */
diff -ruN linux-mips/include/asm-mips/keyboard.h linux-vr/include/asm-mips/keyboard.h
--- linux-mips/include/asm-mips/keyboard.h	Mon Jul 10 15:22:07 2000
+++ linux-vr/include/asm-mips/keyboard.h	Thu Nov 23 15:04:53 2000
@@ -1,4 +1,4 @@
-/* $Id: keyboard.h,v 1.14 1999/08/19 22:56:33 ralf Exp $
+/* $Id: keyboard.h,v 1.18 1999/12/01 17:14:54 harald Exp $
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -15,6 +15,18 @@
 #include <linux/ioport.h>
 #include <asm/bootinfo.h>
 
+#if defined(CONFIG_CLASS_PDA) || defined(CONFIG_NEC_HARRIER)
+
+extern int kbd_setkeycode(unsigned int scancode, unsigned int keycode);
+extern int kbd_getkeycode(unsigned int scancode);
+extern int kbd_translate(unsigned char scancode, unsigned char *keycode,
+	char raw_mode);
+extern char kbd_unexpected_up(unsigned char keycode);
+extern void kbd_leds(unsigned char leds);
+extern void kbd_init_hw(void);
+
+#else
+
 #define DISABLE_KBD_DURING_INTERRUPTS 0
 
 extern int pckbd_setkeycode(unsigned int scancode, unsigned int keycode);
@@ -35,7 +47,11 @@
 #define kbd_init_hw		pckbd_init_hw
 #define kbd_sysrq_xlate         pckbd_sysrq_xlate
 
+#ifndef CONFIG_CLASS_PDA
 #define SYSRQ_KEY 0x54
+#else
+#define SYSRQ_KEY 12345678 /* Impossible value: we'd have to provide translation map, and that's not exactly easy */
+#endif
 
 /* Some stoneage hardware needs delays after some operations.  */
 #define kbd_pause() do { } while(0)
@@ -69,6 +85,8 @@
 #define kbd_write_output(val) kbd_ops->kbd_write_output(val)
 #define kbd_write_command(val) kbd_ops->kbd_write_command(val)
 #define kbd_read_status() kbd_ops->kbd_read_status()
+
+#endif /* CONFIG_CLASS_PDA */
 
 #endif /* __KERNEL */
 
diff -ruN linux-mips/include/asm-mips/linux_logo.h linux-vr/include/asm-mips/linux_logo.h
--- linux-mips/include/asm-mips/linux_logo.h	Tue Apr 11 20:57:19 2000
+++ linux-vr/include/asm-mips/linux_logo.h	Thu Nov 23 15:04:44 2000
@@ -21,921 +21,21 @@
  
 #include <linux/init.h>
 #include <linux/version.h>
+#include <linux/config.h>
 
-#define linux_logo_banner "Linux/MIPS version " UTS_RELEASE
+#ifdef CONFIG_CPU_VR41XX
+  #include <linux/init.h>
+  #include <linux/version.h>
 
-#define LINUX_LOGO_COLORS 212
+  #define linux_logo_banner "Linux VR version " UTS_RELEASE
 
-#ifdef INCLUDE_LINUX_LOGO_DATA
-
-unsigned char linux_logo_red[] __initdata = {
-  0x03, 0x82, 0xE9, 0xBF, 0x42, 0xC9, 0x7E, 0xC0,
-  0xE9, 0xE3, 0xC2, 0x24, 0xA4, 0x65, 0xEC, 0xC4,
-  0x82, 0x9F, 0xF3, 0x12, 0x5F, 0xA0, 0xC2, 0xED,
-  0x3E, 0xD5, 0xDB, 0xA0, 0x1C, 0xF4, 0xEB, 0xA4,
-  0xCD, 0x0A, 0x9A, 0x51, 0xCC, 0xBE, 0xC0, 0xBA,
-  0x74, 0xDC, 0xAA, 0xF6, 0xD3, 0xC5, 0xE6, 0x26,
-  0xC2, 0x83, 0x38, 0xEA, 0x49, 0xB0, 0xED, 0xE5,
-  0xF4, 0x96, 0x96, 0x1B, 0xFA, 0xCC, 0xF2, 0x0F,
-  0xCD, 0xE5, 0xF4, 0xD3, 0x50, 0x7A, 0xB5, 0xDE,
-  0xD5, 0xB6, 0x60, 0x0A, 0x6A, 0xEA, 0xD4, 0xEB,
-  0xC1, 0xCA, 0xEA, 0xEC, 0x2A, 0x96, 0x95, 0xDC,
-  0xE4, 0xCE, 0xEC, 0x1E, 0xDC, 0x8A, 0xD1, 0xF6,
-  0x3C, 0x5E, 0xC6, 0xB4, 0xB2, 0xAC, 0xBA, 0x9E,
-  0x0F, 0x59, 0xBA, 0xFA, 0xCC, 0xBF, 0x82, 0xCE,
-  0xE6, 0x4F, 0xAA, 0x4C, 0xCA, 0x8E, 0x8E, 0xDF,
-  0x2C, 0xB6, 0x3B, 0xDE, 0xCE, 0xEE, 0x46, 0x4A,
-  0x6F, 0x7A, 0x82, 0xE4, 0xAA, 0x88, 0xE2, 0xCE,
-  0xAE, 0xB6, 0x70, 0xC2, 0x9A, 0xDA, 0x35, 0x9E,
-  0x95, 0xC0, 0x7E, 0x8C, 0xC2, 0xB6, 0xCE, 0xB9,
-  0xD5, 0xAA, 0xC1, 0xF4, 0xC7, 0xB6, 0xB6, 0xA3,
-  0xF2, 0x68, 0xDB, 0x76, 0xDC, 0x57, 0xD3, 0xA8,
-  0xC0, 0xEF, 0x46, 0xF4, 0x2F, 0xD7, 0x53, 0x36,
-  0xE6, 0xA7, 0xCA, 0xCB, 0x7E, 0xE4, 0x86, 0x9A,
-  0xCE, 0x94, 0xB4, 0x1D, 0xDA, 0xCE, 0x6C, 0xE6,
-  0x9E, 0xC6, 0xDA, 0x16, 0xFA, 0xAA, 0x56, 0xB6,
-  0xFE, 0x6E, 0xEA, 0xCE, 0xE5, 0xCC, 0xDB, 0xD3,
-  0xED, 0xDC, 0xF4, 0x72
-};
-
-unsigned char linux_logo_green[] __initdata = {
-  0x03, 0x82, 0xC4, 0x83, 0x42, 0xA2, 0x4A, 0xA4,
-  0xE5, 0xA6, 0xC2, 0x24, 0xA4, 0x65, 0xB4, 0x94,
-  0x66, 0x87, 0xB6, 0x12, 0x44, 0x6C, 0x96, 0xD4,
-  0x36, 0x95, 0xB2, 0x92, 0x0E, 0xF4, 0xBC, 0x77,
-  0xA5, 0x0A, 0x92, 0x52, 0xB4, 0x9A, 0x8C, 0xB2,
-  0x74, 0xC2, 0x8E, 0xBD, 0xA2, 0xCA, 0xD2, 0x12,
-  0xB6, 0x61, 0x24, 0xDA, 0x33, 0x79, 0xCB, 0xAC,
-  0xDA, 0x84, 0x7A, 0x1B, 0xFA, 0x8D, 0xBE, 0x06,
-  0x93, 0xBB, 0xBC, 0xAB, 0x44, 0x62, 0x83, 0xDA,
-  0x9B, 0xA2, 0x4C, 0x04, 0x6A, 0xB6, 0xC8, 0xBD,
-  0x8D, 0xB6, 0xAD, 0xEC, 0x2A, 0x68, 0x62, 0x9D,
-  0xC4, 0xC4, 0xB4, 0x13, 0xA3, 0x8A, 0xD2, 0xD6,
-  0x3C, 0x5D, 0x8C, 0x7E, 0x82, 0xAC, 0x96, 0x7E,
-  0x0D, 0x5A, 0xBA, 0xBB, 0xCC, 0xBE, 0x76, 0xB6,
-  0xDE, 0x4E, 0x9A, 0x3C, 0xBE, 0x8E, 0x6E, 0xCB,
-  0x1C, 0xAA, 0x2E, 0xBE, 0xAA, 0xDE, 0x3E, 0x4B,
-  0x4D, 0x7A, 0x54, 0xE4, 0x8E, 0x6E, 0xCA, 0x9B,
-  0x70, 0x9E, 0x5A, 0xAA, 0x9A, 0xBE, 0x34, 0x9E,
-  0x71, 0x9E, 0x7E, 0x5F, 0xAA, 0x8A, 0xBE, 0x91,
-  0xCE, 0x88, 0x92, 0xDB, 0xC6, 0xAB, 0x8A, 0x72,
-  0xE2, 0x44, 0xC3, 0x54, 0xAA, 0x45, 0xBB, 0x92,
-  0xBA, 0xC4, 0x46, 0xCA, 0x2D, 0xD6, 0x3B, 0x1A,
-  0xC2, 0x7E, 0xA6, 0xCB, 0x7A, 0xDC, 0x86, 0x72,
-  0xB6, 0x94, 0xB4, 0x1C, 0xBC, 0xAE, 0x4C, 0xD6,
-  0x62, 0x86, 0xD3, 0x16, 0xF6, 0x7A, 0x55, 0x79,
-  0xFE, 0x6E, 0xC6, 0xC6, 0xAA, 0x93, 0xDC, 0x9D,
-  0xAE, 0xA4, 0xD4, 0x56
-};
-
-unsigned char linux_logo_blue[] __initdata = {
-  0x04, 0x84, 0x10, 0x0C, 0x41, 0x14, 0x04, 0x78,
-  0xC7, 0x0E, 0xC4, 0x24, 0xA4, 0x64, 0x0C, 0x0D,
-  0x17, 0x24, 0x0D, 0x13, 0x11, 0x07, 0x40, 0x22,
-  0x0C, 0x0C, 0x11, 0x78, 0x06, 0xF4, 0x0B, 0x0A,
-  0x47, 0x0B, 0x7C, 0x54, 0x6C, 0x0C, 0x0D, 0x9C,
-  0x73, 0x54, 0x14, 0x0C, 0x0F, 0xC7, 0x94, 0x04,
-  0x94, 0x17, 0x0A, 0x6C, 0x08, 0x0F, 0x14, 0x0B,
-  0x12, 0x68, 0x28, 0x11, 0xFA, 0x0A, 0x34, 0x09,
-  0x0A, 0x2F, 0x15, 0x19, 0x14, 0x3C, 0x06, 0xC4,
-  0x0B, 0x84, 0x24, 0x08, 0x69, 0x38, 0xBC, 0x15,
-  0x1F, 0xA0, 0x0A, 0xEC, 0x2A, 0x0C, 0x0C, 0x0C,
-  0x2C, 0xA0, 0x15, 0x07, 0x0B, 0x8C, 0xD3, 0x10,
-  0x3B, 0x5C, 0x0C, 0x04, 0x3C, 0xAC, 0x54, 0x1C,
-  0x0B, 0x5B, 0xBB, 0x0A, 0xC1, 0xBB, 0x5C, 0x3C,
-  0xBC, 0x4D, 0x74, 0x10, 0x8C, 0x8C, 0x14, 0x91,
-  0x0C, 0x74, 0x17, 0x0C, 0x48, 0x9C, 0x3C, 0x4C,
-  0x09, 0x7C, 0x05, 0xE4, 0x34, 0x38, 0x6C, 0x11,
-  0x08, 0x7C, 0x18, 0x2C, 0x9C, 0x4C, 0x34, 0x9C,
-  0x29, 0x54, 0x7C, 0x0C, 0x78, 0x18, 0x9C, 0x14,
-  0xBA, 0x30, 0x27, 0x31, 0xC2, 0x97, 0x24, 0x09,
-  0xB4, 0x04, 0x87, 0x0C, 0x14, 0x1F, 0x7C, 0x64,
-  0xB0, 0x0F, 0x45, 0x10, 0x2C, 0xD4, 0x0A, 0x04,
-  0x44, 0x1F, 0x2C, 0xCC, 0x7C, 0xD8, 0x84, 0x0C,
-  0x8C, 0x94, 0xB4, 0x1D, 0x20, 0x5C, 0x18, 0xB4,
-  0x04, 0x09, 0xBC, 0x14, 0xF4, 0x08, 0x54, 0x07,
-  0xFC, 0x6C, 0x24, 0xB4, 0x15, 0x18, 0xDB, 0x17,
-  0x17, 0x18, 0x21, 0x24
-};
-
-unsigned char linux_logo[] __initdata = {
-  0xBC, 0xAC, 0x7D, 0x95, 0xAF, 0x85, 0x2C, 0x2C,
-  0xAC, 0xD9, 0x95, 0x7D, 0x95, 0xAC, 0x2C, 0xAF,
-  0x7D, 0x48, 0xB2, 0xAC, 0x85, 0xDA, 0xDA, 0x2C,
-  0x7D, 0x48, 0x21, 0x2C, 0x8D, 0x2A, 0x8A, 0xDA,
-  0x85, 0x2C, 0xD9, 0xAC, 0x2C, 0x2C, 0xD9, 0xD9,
-  0xAF, 0x85, 0x85, 0x85, 0x8D, 0xBC, 0x2A, 0x2A,
-  0xBC, 0x8C, 0xBC, 0xAC, 0x7D, 0x95, 0xAF, 0x85,
-  0x2C, 0x2C, 0xAC, 0xD9, 0x95, 0x7D, 0x95, 0xAC,
-  0x2C, 0xAF, 0x7D, 0x48, 0xB2, 0xAC, 0x85, 0xDA,
-  0xDA, 0x2C, 0x7D, 0x48, 0x21, 0x2C, 0x8D, 0x2A,
-  0xAF, 0xA1, 0x48, 0x7D, 0xAF, 0x2C, 0x2C, 0xAC,
-  0xD9, 0xD9, 0x95, 0x7D, 0x95, 0xAC, 0xD9, 0x7D,
-  0x48, 0xE9, 0x21, 0xAF, 0xDA, 0xDA, 0x85, 0x2C,
-  0xD9, 0xD9, 0xAC, 0xDA, 0x8A, 0xDA, 0x85, 0x2C,
-  0x2C, 0xAC, 0xD9, 0xAC, 0xAF, 0xAF, 0x2C, 0x2C,
-  0x2C, 0x85, 0x2C, 0x2C, 0x85, 0xDA, 0xDA, 0xDA,
-  0xDA, 0xDA, 0xAF, 0xA1, 0x48, 0x7D, 0xAF, 0x2C,
-  0x2C, 0xAC, 0xD9, 0xD9, 0x95, 0x7D, 0x95, 0xAC,
-  0xD9, 0x7D, 0x48, 0xE9, 0x21, 0xAF, 0xDA, 0xDA,
-  0x85, 0x2C, 0xD9, 0xD9, 0xAC, 0xDA, 0x8A, 0xDA,
-  0x7D, 0x48, 0x48, 0x7D, 0x2C, 0x85, 0x2C, 0xAF,
-  0xD9, 0xD9, 0x7D, 0x95, 0xD9, 0xD9, 0xD9, 0x7D,
-  0xB2, 0x21, 0xD9, 0x85, 0xDA, 0xDA, 0x85, 0x2C,
-  0xAF, 0x2C, 0x2C, 0xDA, 0x85, 0x85, 0x2C, 0x2C,
-  0xAC, 0xD9, 0xD9, 0xAF, 0xDA, 0x85, 0x2C, 0x2C,
-  0x85, 0xDA, 0xDA, 0x85, 0x85, 0xDA, 0x85, 0x85,
-  0x85, 0xAF, 0x7D, 0x48, 0x48, 0x7D, 0x2C, 0x85,
-  0x2C, 0xAF, 0xD9, 0xD9, 0x7D, 0x95, 0xD9, 0xD9,
-  0xD9, 0x7D, 0xB2, 0x21, 0xD9, 0x85, 0xDA, 0xDA,
-  0x85, 0x2C, 0xAF, 0x2C, 0x2C, 0xDA, 0xDA, 0x85,
-  0xA1, 0xE9, 0x48, 0x95, 0x85, 0xDA, 0x85, 0xAF,
-  0xD9, 0xD9, 0x95, 0x95, 0xD9, 0xD9, 0x95, 0x95,
-  0xD9, 0xAC, 0x85, 0x85, 0xDA, 0xDA, 0x85, 0x2C,
-  0xAC, 0xAC, 0x2C, 0x2C, 0x85, 0x2C, 0x2C, 0xAC,
-  0xD9, 0xD9, 0x2C, 0x91, 0x41, 0x20, 0x6B, 0x20,
-  0x6B, 0x20, 0x6B, 0xAE, 0x2C, 0x85, 0x2C, 0x2C,
-  0xAC, 0xD9, 0xA1, 0xE9, 0x48, 0x95, 0x85, 0xDA,
-  0x85, 0xAF, 0xD9, 0xD9, 0x95, 0x95, 0xD9, 0xD9,
-  0x95, 0x95, 0xD9, 0xAC, 0x85, 0x85, 0xDA, 0xDA,
-  0x85, 0x2C, 0xAC, 0xAC, 0x2C, 0x2C, 0x2C, 0x2C,
-  0xA1, 0xA1, 0xD6, 0xAF, 0xDA, 0xDA, 0x85, 0x2C,
-  0xD9, 0xD9, 0x95, 0x95, 0xD9, 0xD9, 0xD9, 0xD9,
-  0x2C, 0x2C, 0xDA, 0xDA, 0xDA, 0x85, 0x2C, 0xD9,
-  0xD9, 0xD9, 0xD9, 0xAC, 0xAC, 0xAC, 0xAF, 0xAC,
-  0x2C, 0xB2, 0x88, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0x20, 0x20, 0x20, 0x6B, 0x80, 0x85, 0x2C,
-  0xD9, 0xD6, 0xA1, 0xA1, 0xD6, 0xAF, 0xDA, 0xDA,
-  0x85, 0x2C, 0xD9, 0xD9, 0x95, 0x95, 0xD9, 0xD9,
-  0xD9, 0xD9, 0x2C, 0x2C, 0xDA, 0xDA, 0xDA, 0x85,
-  0x2C, 0xD9, 0xD9, 0xD9, 0xD9, 0xAF, 0xAF, 0xAF,
-  0xD6, 0xD6, 0xD9, 0x2C, 0xDA, 0xDA, 0x2C, 0xAC,
-  0xD9, 0x7D, 0x95, 0xD9, 0xD9, 0xD9, 0xAF, 0x2C,
-  0x85, 0x85, 0x85, 0x85, 0x2C, 0x2C, 0xAC, 0xD9,
-  0xD9, 0xD9, 0xAF, 0xAF, 0x2C, 0x2C, 0xAF, 0xDA,
-  0xAE, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0x20, 0x20, 0x41, 0xE3, 0x20, 0x6B, 0x48,
-  0xAC, 0x95, 0xD6, 0xD6, 0xD9, 0x2C, 0xDA, 0xDA,
-  0x2C, 0xAC, 0xD9, 0x7D, 0x95, 0xD9, 0xD9, 0xD9,
-  0xAF, 0x2C, 0x85, 0x85, 0x85, 0x85, 0x2C, 0x2C,
-  0xAC, 0xD9, 0xD9, 0xD9, 0xAF, 0xAF, 0xAF, 0xAF,
-  0xD9, 0xD9, 0xD9, 0x2C, 0x85, 0x85, 0x2C, 0xD9,
-  0x7D, 0x21, 0xD6, 0xD9, 0xAF, 0x2C, 0x85, 0x85,
-  0x85, 0x85, 0x85, 0x85, 0x2C, 0xAF, 0xAF, 0xAC,
-  0xAF, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0x89,
-  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0x20, 0x20, 0x74, 0x43, 0x80, 0x41, 0x20,
-  0x9F, 0x2C, 0xD9, 0xD9, 0xD9, 0x2C, 0x85, 0x85,
-  0x2C, 0xD9, 0x7D, 0x21, 0xD6, 0xD9, 0xAF, 0x2C,
-  0x85, 0x85, 0x85, 0x85, 0x85, 0x85, 0x2C, 0xAF,
-  0xAF, 0xAC, 0xAF, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C,
-  0xD9, 0x7D, 0xD9, 0xAF, 0x85, 0x85, 0x2C, 0xD9,
-  0xB2, 0x21, 0x7D, 0xD9, 0xAF, 0x2C, 0x85, 0x85,
-  0x85, 0x2C, 0x2C, 0x2C, 0x2C, 0xAF, 0xAF, 0xAC,
-  0xAF, 0xAC, 0xAF, 0xAF, 0xAC, 0xAC, 0x85, 0x41,
-  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0x20, 0x20, 0xAE, 0x48, 0x89, 0x74, 0x41,
-  0x6B, 0xD6, 0xD9, 0x7D, 0xD9, 0xAF, 0x85, 0x85,
-  0x2C, 0xD9, 0xB2, 0x21, 0x7D, 0xD9, 0xAF, 0x2C,
-  0x85, 0x85, 0x85, 0x2C, 0x2C, 0x2C, 0x2C, 0xAF,
-  0xAF, 0xAC, 0xAF, 0xAC, 0xAC, 0x2C, 0xAF, 0xAC,
-  0x2C, 0x7D, 0xD9, 0x2C, 0xDA, 0x85, 0x2C, 0x7D,
-  0xB2, 0xD6, 0xD9, 0xAF, 0x85, 0x85, 0x85, 0x85,
-  0xAF, 0xAC, 0xAC, 0xAF, 0xAF, 0xAC, 0xAC, 0xD9,
-  0x95, 0x7D, 0x95, 0x95, 0xD9, 0xD9, 0x48, 0x20,
-  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0x20, 0x6B, 0xAE, 0xE6, 0x80, 0x2B, 0x88,
-  0x20, 0x33, 0xDA, 0x95, 0xD9, 0x2C, 0xDA, 0x85,
-  0x2C, 0x7D, 0xB2, 0xD6, 0xD9, 0xAF, 0x85, 0x85,
-  0x85, 0x85, 0xAF, 0xAC, 0xAC, 0xAF, 0xAF, 0xAC,
-  0xAC, 0xD9, 0x95, 0x95, 0x7D, 0x95, 0x95, 0xD9,
-  0x85, 0xD9, 0x2C, 0x85, 0xDA, 0xDA, 0xD9, 0x21,
-  0xA1, 0xD9, 0xAF, 0x2C, 0x85, 0xDA, 0x85, 0xAF,
-  0xD9, 0xD9, 0xAC, 0xAC, 0xAC, 0xD9, 0x7D, 0xD6,
-  0xD6, 0x7D, 0x95, 0xD9, 0xD9, 0x85, 0xDB, 0x20,
-  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0x20, 0x20, 0xDB, 0xE3, 0x6B, 0x20, 0x20,
-  0x20, 0x20, 0xE9, 0xD9, 0x2C, 0x85, 0xDA, 0xDA,
-  0xD9, 0x21, 0xA1, 0xD9, 0xAF, 0x2C, 0x85, 0xDA,
-  0x85, 0xAF, 0xD9, 0xD9, 0xAC, 0xAC, 0xAC, 0xD9,
-  0x7D, 0xD6, 0xD6, 0x7D, 0x95, 0xD9, 0xD9, 0xD9,
-  0xDA, 0x2C, 0x85, 0xDA, 0xDA, 0x85, 0x95, 0x21,
-  0x21, 0xD9, 0x85, 0x85, 0x85, 0x2C, 0x2C, 0xD9,
-  0x95, 0x95, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9,
-  0xAC, 0xAC, 0x2C, 0xAF, 0x2C, 0x85, 0x20, 0x20,
-  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0x20, 0x88, 0xDA, 0x85, 0xDA, 0xDA, 0x85,
-  0x95, 0x21, 0x21, 0xD9, 0x85, 0x85, 0x85, 0x2C,
-  0x2C, 0xD9, 0x95, 0x95, 0xD9, 0xD9, 0xD9, 0xD9,
-  0xD9, 0xD9, 0xD9, 0xAF, 0x2C, 0x2C, 0x2C, 0x2C,
-  0xDA, 0x2C, 0x85, 0x85, 0x2C, 0xD9, 0xD6, 0xB2,
-  0x95, 0x2C, 0x85, 0x85, 0xAF, 0xAC, 0x95, 0x95,
-  0x7D, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0x2C, 0x85,
-  0x85, 0x85, 0x85, 0x85, 0x85, 0xAC, 0x20, 0x20,
-  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0x20, 0x20, 0xAC, 0x85, 0x85, 0x2C, 0xD9,
-  0xD6, 0xB2, 0x95, 0x2C, 0x85, 0x85, 0xAF, 0xAC,
-  0x95, 0x95, 0x7D, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9,
-  0x2C, 0x85, 0x85, 0x85, 0x85, 0x85, 0x85, 0x85,
-  0x85, 0x2C, 0x2C, 0x2C, 0xAC, 0x95, 0xD6, 0x7D,
-  0xD9, 0x2C, 0x2C, 0xAF, 0x95, 0x7D, 0x7D, 0x95,
-  0x95, 0xD9, 0xD9, 0x95, 0xD9, 0xD9, 0x2C, 0x85,
-  0xDA, 0xDA, 0xDA, 0x85, 0x85, 0x21, 0x20, 0x20,
-  0x6B, 0x41, 0xDB, 0x6B, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0x20, 0x20, 0x41, 0xDB, 0xDB, 0x20, 0x20,
-  0x20, 0x20, 0x20, 0xE6, 0x2C, 0x2C, 0xAC, 0x95,
-  0xD6, 0x7D, 0xD9, 0x2C, 0x2C, 0xAF, 0x95, 0x7D,
-  0x7D, 0x95, 0x95, 0xD9, 0xD9, 0x95, 0xD9, 0xD9,
-  0x2C, 0x85, 0xDA, 0xDA, 0xDA, 0x85, 0x2C, 0x2C,
-  0x2C, 0xAF, 0xAC, 0xD9, 0x95, 0xD6, 0xD6, 0xD9,
-  0x2C, 0x2C, 0x2C, 0xD9, 0xD6, 0xD6, 0xD9, 0xAF,
-  0xAC, 0x95, 0xD6, 0x7D, 0x7D, 0xD9, 0x2C, 0x85,
-  0xDA, 0xDA, 0x2C, 0xAF, 0xAF, 0x21, 0x20, 0x20,
-  0x88, 0x2B, 0x88, 0x74, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0xAE, 0x2D, 0x2D, 0x74, 0x74, 0x88, 0x20,
-  0x20, 0x20, 0x20, 0x80, 0xAC, 0xD9, 0x95, 0xD6,
-  0xD6, 0xD9, 0x2C, 0x2C, 0x2C, 0xD9, 0xD6, 0xD6,
-  0xD9, 0xAF, 0xAC, 0x95, 0xD6, 0x7D, 0x7D, 0xD9,
-  0x2C, 0xDA, 0xDA, 0x85, 0x2C, 0xAF, 0xAF, 0xAF,
-  0x2C, 0xAF, 0xD9, 0x95, 0xD6, 0xD6, 0x95, 0xAF,
-  0x2C, 0x2C, 0xD9, 0x95, 0xD6, 0x95, 0xAF, 0x2C,
-  0xAC, 0x7D, 0x21, 0x95, 0xD9, 0x2C, 0x85, 0x85,
-  0x85, 0xAF, 0xD9, 0x95, 0xD9, 0x7D, 0x20, 0x33,
-  0x7D, 0x8A, 0x7D, 0x5B, 0x6B, 0x20, 0x20, 0x6B,
-  0xE6, 0xD9, 0x85, 0x2A, 0xDA, 0x2B, 0x41, 0x20,
-  0x20, 0x20, 0x6B, 0x74, 0xD9, 0x95, 0xD6, 0xD6,
-  0x95, 0xAF, 0x2C, 0x2C, 0xD9, 0x95, 0xD6, 0x95,
-  0xAF, 0x2C, 0xAC, 0x7D, 0x21, 0x95, 0xD9, 0x2C,
-  0x85, 0x85, 0x85, 0x2C, 0xD9, 0xD9, 0xD9, 0xD9,
-  0x85, 0xD9, 0x7D, 0x21, 0x21, 0x7D, 0xAC, 0x2C,
-  0x2C, 0xAC, 0xD9, 0x7D, 0xD9, 0xAF, 0x2C, 0x85,
-  0xAC, 0x7D, 0x7D, 0xAC, 0x85, 0xDA, 0x8A, 0xDA,
-  0x85, 0xAF, 0xD9, 0x7D, 0xD9, 0x95, 0x20, 0x91,
-  0xBC, 0x73, 0xEE, 0x7D, 0x20, 0x20, 0x20, 0x80,
-  0x4D, 0x3D, 0x73, 0x73, 0xA3, 0xD6, 0x20, 0x20,
-  0x20, 0x20, 0x20, 0x2B, 0x7D, 0x21, 0x21, 0x7D,
-  0xAC, 0x2C, 0x2C, 0xAC, 0xD9, 0x7D, 0xD9, 0xAF,
-  0x2C, 0x85, 0xAC, 0x7D, 0x7D, 0xAC, 0x85, 0xDA,
-  0x8A, 0x8A, 0x85, 0xAC, 0xD9, 0x7D, 0xD9, 0xAC,
-  0x2C, 0xD9, 0xD6, 0xB2, 0xB2, 0x7D, 0xAF, 0x85,
-  0x2C, 0xD9, 0x95, 0x95, 0xAF, 0x2C, 0x2C, 0x2C,
-  0xD9, 0xD9, 0xAC, 0x85, 0x8D, 0x2A, 0x2A, 0xDA,
-  0xAF, 0xD9, 0x95, 0x95, 0xD9, 0xAC, 0x20, 0xAF,
-  0x2C, 0xE6, 0x8D, 0x73, 0xE3, 0x20, 0x20, 0x48,
-  0x5C, 0xDA, 0x5B, 0x43, 0xBC, 0x73, 0x2B, 0x20,
-  0x20, 0x20, 0x20, 0x41, 0xD6, 0xB2, 0xB2, 0x7D,
-  0xAF, 0x85, 0x2C, 0xD9, 0x95, 0x95, 0xAF, 0x2C,
-  0x2C, 0x2C, 0xD9, 0xD9, 0xAC, 0x85, 0x8A, 0x2A,
-  0x8D, 0xDA, 0xAF, 0xD9, 0x95, 0x95, 0xD9, 0xAF,
-  0xAC, 0xD9, 0xD6, 0xB2, 0x21, 0xD9, 0x2C, 0x85,
-  0x2C, 0xD9, 0x95, 0xD9, 0xAF, 0x2C, 0x2C, 0xAC,
-  0xAC, 0xAF, 0x85, 0x8D, 0xBC, 0xBC, 0xDA, 0xD9,
-  0xD6, 0xA1, 0xA1, 0x21, 0xD9, 0xAC, 0x20, 0x2A,
-  0xCC, 0xAE, 0x9F, 0xE4, 0xAE, 0x5B, 0x74, 0xA1,
-  0xE4, 0xAE, 0x20, 0x9F, 0x89, 0xE8, 0xE6, 0x20,
-  0x20, 0x20, 0x20, 0x41, 0xD6, 0xB2, 0x21, 0xD9,
-  0x2C, 0x85, 0x2C, 0xD9, 0x95, 0xD9, 0xAF, 0x2C,
-  0x2C, 0xAC, 0xAC, 0xAF, 0x85, 0x8D, 0xBC, 0x2A,
-  0xDA, 0xD9, 0xD6, 0xA1, 0xA1, 0x21, 0xD9, 0xD9,
-  0xD9, 0x95, 0x21, 0xA1, 0x21, 0xAC, 0x85, 0x85,
-  0xAC, 0xD9, 0xD9, 0xAF, 0x2C, 0x2C, 0xAF, 0xAC,
-  0xAF, 0x85, 0x8A, 0x2A, 0x2A, 0xDA, 0xD9, 0xA1,
-  0x48, 0xE9, 0x48, 0x21, 0x95, 0xAC, 0x20, 0x2A,
-  0xDB, 0x41, 0x74, 0xBC, 0x2B, 0x7B, 0x7B, 0x80,
-  0x73, 0x41, 0x20, 0x6B, 0x2B, 0xE8, 0x2D, 0x20,
-  0x20, 0x20, 0x20, 0x33, 0x21, 0xA1, 0x21, 0xAC,
-  0x85, 0x85, 0xAC, 0xD9, 0xD9, 0xAF, 0x2C, 0x2C,
-  0xAF, 0xAC, 0xAF, 0x85, 0x8A, 0xBC, 0x2A, 0xDA,
-  0xD9, 0xA1, 0x48, 0xE9, 0x48, 0x21, 0xD9, 0xD9,
-  0xA1, 0xB2, 0xB2, 0x48, 0xD6, 0xAC, 0x2C, 0x2C,
-  0xD9, 0x95, 0xAF, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C,
-  0x85, 0x8A, 0x8D, 0x8D, 0x85, 0x95, 0xA1, 0x6C,
-  0x6C, 0x48, 0xD6, 0xD9, 0x2C, 0x85, 0x20, 0x2C,
-  0x89, 0x20, 0x3C, 0xB9, 0xA7, 0x63, 0xD2, 0xB9,
-  0xC6, 0x9A, 0x20, 0x20, 0x43, 0x5C, 0xE6, 0x20,
-  0x20, 0x20, 0x20, 0x33, 0xB2, 0x48, 0xD6, 0xAC,
-  0x2C, 0x2C, 0xD9, 0x95, 0xAF, 0x2C, 0x2C, 0x2C,
-  0x2C, 0x2C, 0x85, 0x8A, 0x8D, 0x8D, 0x85, 0x95,
-  0xA1, 0x6C, 0x6C, 0x48, 0xD6, 0xD9, 0xAF, 0xAC,
-  0xA1, 0xD6, 0x7D, 0xB2, 0xD6, 0xAF, 0x85, 0x85,
-  0xD9, 0x95, 0x2C, 0x85, 0xDA, 0x85, 0x85, 0x2C,
-  0x85, 0x8A, 0x8D, 0xDA, 0xD9, 0x48, 0x81, 0x2D,
-  0x48, 0xD6, 0xD9, 0xAC, 0x2C, 0x85, 0x20, 0x2D,
-  0xEE, 0x93, 0xD1, 0xA7, 0x3E, 0x3E, 0x3A, 0x25,
-  0x56, 0xAB, 0xAA, 0xC5, 0xEE, 0xEE, 0x33, 0x20,
-  0x20, 0x20, 0x20, 0x41, 0xD9, 0xB2, 0xD6, 0xAF,
-  0x85, 0x85, 0xD9, 0x95, 0x2C, 0x85, 0xDA, 0x85,
-  0x85, 0x2C, 0x85, 0x8A, 0x8D, 0xDA, 0xD9, 0x48,
-  0x81, 0x2D, 0x48, 0xD6, 0xD9, 0xAF, 0x2C, 0x2C,
-  0xAC, 0xAF, 0xD9, 0x7D, 0xD6, 0x2C, 0x85, 0x2C,
-  0xD9, 0xD9, 0x2C, 0xDA, 0xDA, 0xDA, 0x2C, 0x2C,
-  0x85, 0x8D, 0x8D, 0x2C, 0x21, 0x2D, 0x2D, 0xE9,
-  0xD6, 0xD9, 0xAF, 0x2C, 0x85, 0xDA, 0x20, 0xE3,
-  0xB4, 0xBE, 0xF1, 0x3E, 0x9B, 0x22, 0x56, 0xF2,
-  0xBB, 0x7F, 0x56, 0xDC, 0x8F, 0x5A, 0x5F, 0x20,
-  0x20, 0x20, 0x20, 0x6B, 0x2C, 0x7D, 0xD6, 0x2C,
-  0x85, 0x2C, 0xD9, 0xD9, 0x2C, 0xDA, 0xDA, 0xDA,
-  0x2C, 0x2C, 0x85, 0x8D, 0x8A, 0x85, 0x21, 0x2D,
-  0x2D, 0xE9, 0xD6, 0xD9, 0xAF, 0x2C, 0x85, 0x85,
-  0x2A, 0x85, 0xAC, 0x95, 0x95, 0x2C, 0x85, 0x85,
-  0xAC, 0xAF, 0x85, 0xDA, 0xDA, 0x85, 0x2C, 0x2C,
-  0xDA, 0x8A, 0x8A, 0xAF, 0xA1, 0x2D, 0xE9, 0xD6,
-  0xD9, 0xAC, 0x85, 0x85, 0x85, 0xDA, 0x20, 0x52,
-  0x55, 0xED, 0x57, 0x3E, 0x22, 0x56, 0x37, 0xBB,
-  0xBB, 0x58, 0x7F, 0x7F, 0x56, 0x5E, 0xC5, 0x20,
-  0x20, 0x20, 0x20, 0x20, 0x2C, 0x95, 0x95, 0x2C,
-  0x85, 0x85, 0xAC, 0xAF, 0x85, 0xDA, 0xDA, 0x85,
-  0x2C, 0x2C, 0xDA, 0x8D, 0xDA, 0xAF, 0xA1, 0x2D,
-  0xE9, 0xD6, 0xD9, 0xAF, 0x2C, 0x85, 0x85, 0x85,
-  0xCD, 0xAF, 0xD9, 0x95, 0xD9, 0x2C, 0xDA, 0x85,
-  0xAF, 0xD9, 0x85, 0xDA, 0x85, 0x2C, 0xAC, 0xAF,
-  0x85, 0x8A, 0x85, 0xD9, 0x48, 0x48, 0xB2, 0x95,
-  0x95, 0xAC, 0x2C, 0x85, 0xDA, 0xDA, 0x6B, 0xB3,
-  0x46, 0x7C, 0x2E, 0x9B, 0x22, 0x56, 0xBB, 0x37,
-  0x58, 0x58, 0xF2, 0x3A, 0x46, 0x63, 0x64, 0x20,
-  0x20, 0x20, 0x20, 0x20, 0x2D, 0x95, 0xD9, 0x2C,
-  0xDA, 0x85, 0xAF, 0xD9, 0x85, 0xDA, 0x85, 0x2C,
-  0xAC, 0xAF, 0x85, 0xDA, 0x85, 0xD9, 0x48, 0x48,
-  0xB2, 0x95, 0x95, 0xD9, 0x85, 0xDA, 0x85, 0x85,
-  0xBC, 0xB2, 0xB2, 0x7D, 0xD9, 0x2C, 0xDA, 0x85,
-  0xAF, 0xD9, 0x85, 0xDA, 0x85, 0x85, 0xAF, 0x2C,
-  0x85, 0xDA, 0x2C, 0x7D, 0xA1, 0x48, 0xB2, 0x21,
-  0xD6, 0xD9, 0x85, 0xDA, 0x85, 0xDA, 0x41, 0x51,
-  0xB7, 0xEC, 0x2E, 0x22, 0x56, 0x37, 0xBB, 0xF2,
-  0x37, 0xEA, 0x2F, 0x2F, 0x77, 0xA7, 0x38, 0x20,
-  0x20, 0x6B, 0x20, 0x20, 0x5B, 0x2C, 0xD9, 0x2C,
-  0xDA, 0x85, 0xAF, 0xD9, 0x85, 0xDA, 0x85, 0x85,
-  0xAF, 0x2C, 0xDA, 0xDA, 0x2C, 0x7D, 0xA1, 0x48,
-  0xB2, 0x21, 0xD6, 0xD9, 0x2C, 0xDA, 0x85, 0xAF,
-  0x2C, 0x2D, 0x48, 0x7D, 0xAF, 0x2C, 0x85, 0x2C,
-  0xD9, 0xAC, 0xAF, 0x85, 0x85, 0x2C, 0x2C, 0x2C,
-  0x85, 0x2C, 0xD9, 0xD6, 0xA1, 0xA1, 0x48, 0xA1,
-  0x21, 0x2C, 0xDA, 0xDA, 0x2C, 0x85, 0x41, 0x98,
-  0xA2, 0xA7, 0x6F, 0xC9, 0x37, 0xF2, 0xF2, 0x9B,
-  0xB7, 0x66, 0x60, 0x4C, 0xED, 0x84, 0x3C, 0x20,
-  0x5B, 0x2D, 0x2B, 0x6B, 0x20, 0xAF, 0xAF, 0x2C,
-  0x85, 0x2C, 0xD9, 0xAC, 0xAF, 0x85, 0x85, 0x2C,
-  0x2C, 0x2C, 0x2C, 0x85, 0xD9, 0xD6, 0xA1, 0xA1,
-  0x48, 0xA1, 0xD6, 0xAF, 0xDA, 0x8A, 0x2C, 0xD9,
-  0xB2, 0x2D, 0x48, 0x95, 0x2C, 0x2C, 0x2C, 0x85,
-  0xAC, 0xAC, 0xAF, 0x85, 0xDA, 0x85, 0xAF, 0xAC,
-  0xAF, 0x2C, 0xD9, 0xD6, 0xD6, 0xD6, 0x21, 0xD6,
-  0xD9, 0xDA, 0x8D, 0xDA, 0xAF, 0x2C, 0x20, 0x88,
-  0x42, 0x51, 0x3F, 0x2F, 0x45, 0xB7, 0x66, 0x55,
-  0x46, 0x60, 0x5D, 0x36, 0xD8, 0x71, 0x43, 0x20,
-  0x20, 0x2D, 0xB2, 0x80, 0x20, 0x2D, 0x2C, 0x2C,
-  0x2C, 0x85, 0xAC, 0xAC, 0xAF, 0x85, 0xDA, 0x85,
-  0xAF, 0xAC, 0xAC, 0xAF, 0xD9, 0xD6, 0xD6, 0xD6,
-  0x21, 0xD6, 0xD9, 0xDA, 0x8D, 0x8A, 0x2C, 0xD9,
-  0xB2, 0x48, 0xD6, 0xAC, 0xAF, 0x2C, 0x2C, 0x85,
-  0x2C, 0xAC, 0x2C, 0xDA, 0xDA, 0x85, 0xAF, 0xD9,
-  0xD9, 0xAC, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xAC,
-  0x85, 0x8D, 0xBC, 0xDA, 0xD9, 0xDA, 0x20, 0xE3,
-  0xDA, 0x69, 0x96, 0xB5, 0xF1, 0x68, 0x5D, 0x82,
-  0xE1, 0xBE, 0x27, 0x8D, 0x4D, 0xD3, 0x7D, 0x20,
-  0x20, 0xDB, 0xA1, 0xCA, 0x20, 0x88, 0x85, 0x2C,
-  0x2C, 0x85, 0x2C, 0xAC, 0x2C, 0xDA, 0xDA, 0x85,
-  0xAF, 0xD9, 0xAC, 0xAF, 0xD9, 0xD9, 0xD9, 0xD9,
-  0xD9, 0xAC, 0xDA, 0x8D, 0xBC, 0xDA, 0xD9, 0x95,
-  0xD9, 0x95, 0xAC, 0x2C, 0x2C, 0x2C, 0x2C, 0x85,
-  0x85, 0xAF, 0xAF, 0x85, 0x85, 0x2C, 0x2C, 0xAC,
-  0xD9, 0xAC, 0xAF, 0x2C, 0x2C, 0x2C, 0x2C, 0x85,
-  0x8D, 0x2A, 0x2A, 0x85, 0xD9, 0x95, 0x20, 0xDB,
-  0x8D, 0x8D, 0x99, 0xB0, 0x35, 0xE5, 0x3F, 0x35,
-  0xB9, 0x50, 0x8A, 0x4D, 0x73, 0xE8, 0xA3, 0xCC,
-  0x20, 0x20, 0x33, 0x6B, 0x20, 0x20, 0xCC, 0x85,
-  0x2C, 0x85, 0x85, 0xAF, 0xAF, 0x85, 0x85, 0x85,
-  0x2C, 0xD9, 0xD9, 0xAC, 0xAF, 0x2C, 0x2C, 0x2C,
-  0x2C, 0x85, 0x8A, 0x2A, 0x8D, 0x2C, 0xD9, 0xD9,
-  0xAF, 0xAF, 0xAC, 0xAF, 0x2C, 0x2C, 0x2C, 0x85,
-  0x2C, 0xAF, 0xAF, 0xAF, 0x2C, 0x2C, 0x2C, 0xAC,
-  0xD9, 0xAC, 0xAF, 0x2C, 0x85, 0x85, 0xDA, 0xDA,
-  0x8A, 0x8A, 0x85, 0xD9, 0x2C, 0x2B, 0x20, 0xAE,
-  0xA3, 0xBC, 0x8D, 0xC8, 0xA9, 0xC7, 0x92, 0x47,
-  0x8D, 0x8D, 0x7E, 0xE4, 0xE8, 0xE8, 0x5C, 0x2C,
-  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x6B, 0xAF,
-  0x2C, 0x85, 0x2C, 0xAF, 0xAF, 0xAF, 0x2C, 0x2C,
-  0x2C, 0xAF, 0xD9, 0xAC, 0x2C, 0x2C, 0x85, 0x85,
-  0x85, 0xDA, 0x8D, 0x8A, 0x85, 0xAC, 0x95, 0xD9,
-  0xAC, 0xAC, 0xAC, 0xAC, 0x2C, 0xAF, 0xAF, 0x2C,
-  0x2C, 0xAF, 0xAF, 0xAC, 0x2C, 0xAF, 0x2C, 0xAF,
-  0xD9, 0xAC, 0x2C, 0x2C, 0x85, 0x85, 0x85, 0x85,
-  0x85, 0x2C, 0xD9, 0xD9, 0x2D, 0x6B, 0x41, 0x2A,
-  0xE8, 0xA3, 0xC8, 0x8D, 0x8A, 0x8A, 0x8A, 0x8D,
-  0x4D, 0xA3, 0x3D, 0xE8, 0xE8, 0xE8, 0xE8, 0x5C,
-  0xAE, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0xDB,
-  0xDA, 0x2C, 0x2C, 0xAF, 0xAF, 0xAC, 0xAC, 0xAF,
-  0x2C, 0xAC, 0xD9, 0xAC, 0x2C, 0x2C, 0x85, 0x85,
-  0x85, 0x85, 0x85, 0x2C, 0xD9, 0x95, 0x7D, 0xD9,
-  0x7D, 0x7D, 0xD9, 0xAC, 0xAC, 0xAF, 0xAF, 0xAF,
-  0x2C, 0x2C, 0xAC, 0xAC, 0xD9, 0xAC, 0xAC, 0xD9,
-  0x95, 0xD9, 0xAC, 0xAF, 0xAF, 0xAC, 0xAF, 0xAC,
-  0xD9, 0x7D, 0x7D, 0x7D, 0x33, 0x41, 0x2D, 0xE8,
-  0xE8, 0x5C, 0xD3, 0x8D, 0x8D, 0x8D, 0x8D, 0x7E,
-  0x3D, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8,
-  0xDA, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x81, 0x2C, 0x2C, 0x2C, 0xAC, 0xAC, 0xAC, 0xAC,
-  0xAC, 0xD9, 0x95, 0x95, 0xAC, 0xAF, 0xAF, 0xAF,
-  0xAF, 0xAC, 0xD9, 0x95, 0x7D, 0xD6, 0xD6, 0x7D,
-  0x21, 0xD6, 0x95, 0xD9, 0xD9, 0xAC, 0xAF, 0xAF,
-  0x2C, 0xAF, 0xAC, 0xAC, 0xD9, 0xD9, 0xD9, 0xD9,
-  0x21, 0x21, 0x7D, 0x95, 0x95, 0x7D, 0xD6, 0x21,
-  0xB2, 0xA1, 0x2C, 0x88, 0x20, 0xE3, 0xA3, 0xE8,
-  0xE8, 0xE8, 0xE4, 0xEE, 0xD3, 0x7E, 0x73, 0x5C,
-  0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8,
-  0x5C, 0x2B, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0x2C, 0xAF, 0xAF, 0xAC, 0xD9, 0xD9, 0xD9,
-  0xD9, 0xD9, 0xD6, 0x21, 0x7D, 0x95, 0x95, 0x7D,
-  0xD6, 0xB2, 0xA1, 0xA1, 0xB2, 0xD6, 0x21, 0x21,
-  0x21, 0xD9, 0xD9, 0xD9, 0xAC, 0xAF, 0xAC, 0xAF,
-  0x2C, 0x2C, 0xAC, 0xD9, 0xD9, 0xD9, 0xD9, 0x95,
-  0x7D, 0xB2, 0xD6, 0x95, 0xD9, 0x95, 0xD6, 0xA1,
-  0xA1, 0xAF, 0x5B, 0x20, 0x20, 0xD6, 0xE8, 0xE8,
-  0xE8, 0xE8, 0xE8, 0xE8, 0x5C, 0xE8, 0xE8, 0xE8,
-  0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8,
-  0xE8, 0x48, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0xE3, 0x8A, 0x2C, 0xAC, 0xAC, 0xD9, 0xD9,
-  0xD9, 0x95, 0xD6, 0xB2, 0xD6, 0x95, 0xD9, 0x95,
-  0x21, 0xB2, 0xA1, 0xB2, 0xD6, 0xD6, 0xD6, 0xA1,
-  0xD9, 0x2C, 0x2C, 0x2C, 0xAF, 0xAF, 0xAC, 0xAF,
-  0x2C, 0x2C, 0xAF, 0xAC, 0xD9, 0xAC, 0xD9, 0xD9,
-  0xD9, 0x95, 0xAC, 0x2C, 0x2C, 0xAC, 0x95, 0x7D,
-  0xD9, 0x91, 0x20, 0x20, 0xE3, 0xA3, 0xE8, 0xE8,
-  0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8,
-  0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8,
-  0xE8, 0x85, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0x20, 0x2B, 0x8A, 0xAF, 0xAC, 0xD9, 0xAC,
-  0xD9, 0xD9, 0xD9, 0x95, 0xAC, 0x2C, 0x2C, 0xAC,
-  0x95, 0x7D, 0x95, 0x95, 0xD9, 0x95, 0x7D, 0x21,
-  0x2C, 0xDA, 0xDA, 0x85, 0x2C, 0xAF, 0xAF, 0xAF,
-  0xAF, 0xAF, 0x2C, 0xAF, 0xAF, 0xAC, 0xAC, 0xAC,
-  0xD9, 0xAF, 0x85, 0x85, 0x2C, 0xAF, 0xD9, 0xAF,
-  0x48, 0x20, 0x20, 0x20, 0xE6, 0xA3, 0xE8, 0xE8,
-  0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8,
-  0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0x5C,
-  0xE4, 0x73, 0x41, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0x20, 0x20, 0x2B, 0xDA, 0xAF, 0xAF, 0xAC,
-  0xAC, 0xAF, 0xD9, 0x2C, 0x85, 0x85, 0x2C, 0xAF,
-  0xD9, 0xD9, 0xAC, 0xAF, 0xAC, 0xD9, 0xD9, 0xD9,
-  0x85, 0xDA, 0xDA, 0x85, 0x2C, 0x2C, 0xAC, 0xAF,
-  0xAF, 0xAF, 0xAF, 0x2C, 0xAF, 0xAF, 0xAC, 0xAC,
-  0xAF, 0x2C, 0x2C, 0x2C, 0xAC, 0x95, 0x95, 0xA1,
-  0x20, 0x20, 0x20, 0x20, 0xE9, 0x8C, 0x5C, 0xE8,
-  0xE8, 0xE8, 0xE8, 0x3D, 0x73, 0x73, 0xE8, 0xE8,
-  0xE8, 0xE8, 0xE8, 0xE4, 0x73, 0x73, 0x73, 0xCD,
-  0x7E, 0xA3, 0x74, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0x20, 0x20, 0x20, 0x24, 0x85, 0xAF, 0xAF,
-  0xAC, 0xAC, 0xAC, 0xAF, 0x85, 0x2C, 0xAC, 0x95,
-  0x95, 0xD9, 0xAC, 0xAC, 0xAC, 0xD9, 0xAC, 0xAF,
-  0x8A, 0x8A, 0xDA, 0xDA, 0x85, 0x2C, 0x2C, 0x2C,
-  0x2C, 0x2C, 0x2C, 0xAF, 0xAF, 0xAC, 0xAF, 0xAC,
-  0xAC, 0xAF, 0xAF, 0xD9, 0xD6, 0xD6, 0x2C, 0x88,
-  0x20, 0x20, 0x20, 0x88, 0xB2, 0xDA, 0x7E, 0x73,
-  0xE8, 0xE8, 0xE8, 0x3D, 0x73, 0xE8, 0xE8, 0xE8,
-  0xE8, 0xE8, 0xE8, 0xA3, 0xCD, 0xD3, 0x2A, 0x2A,
-  0x2A, 0x8C, 0x8D, 0x88, 0x20, 0xE3, 0x6B, 0x20,
-  0x20, 0x20, 0x20, 0x20, 0x41, 0x85, 0xAF, 0xAC,
-  0xAC, 0xAC, 0xAC, 0xAF, 0xAC, 0xD9, 0x7D, 0xD6,
-  0x7D, 0x7D, 0xD9, 0x95, 0xD9, 0xAC, 0xAC, 0xAF,
-  0xD3, 0x8D, 0xDA, 0xDA, 0x85, 0x85, 0x2C, 0x2C,
-  0x2C, 0xAF, 0xAF, 0xAC, 0xD9, 0xD9, 0xD9, 0xD9,
-  0xAF, 0xAF, 0xAC, 0xD9, 0x95, 0x7D, 0xAC, 0x20,
-  0x20, 0x20, 0x20, 0xDB, 0x2C, 0xA3, 0x5C, 0xE8,
-  0xE8, 0xE8, 0xE8, 0x5C, 0x3D, 0x3D, 0xE8, 0xE8,
-  0xE8, 0xE4, 0xE8, 0xE8, 0xE8, 0xE4, 0x73, 0xEE,
-  0xD3, 0x2A, 0xEE, 0xAC, 0x20, 0x33, 0x2B, 0xE3,
-  0x20, 0x20, 0x20, 0x20, 0x20, 0x9F, 0xAF, 0xD9,
-  0xD9, 0xAC, 0xAF, 0xAF, 0xAC, 0xD9, 0x95, 0x7D,
-  0xD9, 0x95, 0x95, 0x95, 0x95, 0xD9, 0xAF, 0xAF,
-  0x7E, 0x85, 0x85, 0x2C, 0x85, 0x85, 0x85, 0x2C,
-  0x2C, 0x2C, 0xAF, 0xD9, 0xD9, 0x95, 0xD9, 0xAC,
-  0xAC, 0xAF, 0xAF, 0xAC, 0xAC, 0xAC, 0x91, 0x20,
-  0x33, 0xE3, 0x41, 0x48, 0x73, 0x5C, 0xE8, 0xE8,
-  0xE8, 0xE8, 0xE8, 0xA3, 0xD6, 0x6C, 0x85, 0xE8,
-  0xDA, 0xAE, 0xB2, 0xA3, 0x5C, 0xE8, 0xE8, 0xE8,
-  0x3D, 0xEE, 0x4D, 0xA3, 0x24, 0x20, 0x6B, 0xDB,
-  0x2B, 0x20, 0x20, 0x20, 0x20, 0x20, 0x85, 0x95,
-  0xD9, 0xD9, 0xAC, 0xAF, 0xAF, 0xAC, 0xD9, 0xAC,
-  0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xAC, 0xD9, 0xAC,
-  0x8A, 0xD9, 0xAC, 0xD9, 0xAC, 0xAC, 0x2C, 0x2C,
-  0xAF, 0xAF, 0xAF, 0xAC, 0xD9, 0xD9, 0xD9, 0xD9,
-  0xAF, 0xAF, 0xAF, 0xAC, 0xAC, 0x85, 0x33, 0x20,
-  0xCC, 0x20, 0xE3, 0xA3, 0xE8, 0xE8, 0xE8, 0xE8,
-  0xE8, 0xA3, 0xD9, 0x81, 0xAC, 0xDA, 0x2D, 0x5C,
-  0x48, 0x41, 0x88, 0x74, 0x21, 0xA3, 0xE8, 0xE8,
-  0xE8, 0xE8, 0x73, 0x8C, 0x8A, 0x20, 0x20, 0x20,
-  0xDB, 0x33, 0x20, 0x20, 0x20, 0x20, 0xE6, 0xD9,
-  0xD9, 0xAC, 0xAC, 0xAF, 0xAC, 0xAF, 0xAC, 0xAF,
-  0xAF, 0xAC, 0xD9, 0xAF, 0xD9, 0xAC, 0xAC, 0xAF,
-  0x85, 0xD9, 0x95, 0xD9, 0x95, 0xD9, 0xD9, 0xAC,
-  0xAF, 0xAC, 0xAF, 0xAF, 0x2C, 0xAF, 0x2C, 0x2C,
-  0xAF, 0xAF, 0xAF, 0xAC, 0xAC, 0x2C, 0x20, 0x5B,
-  0x33, 0x20, 0xD6, 0xE8, 0xE8, 0xE8, 0xE8, 0x73,
-  0xAF, 0x2D, 0xD9, 0xDA, 0xB2, 0x81, 0x81, 0xE4,
-  0xA1, 0x91, 0x2B, 0x88, 0x33, 0x80, 0xAF, 0x73,
-  0xE8, 0xE8, 0xE8, 0x5C, 0xA3, 0x80, 0x41, 0xCC,
-  0x2B, 0xCC, 0x20, 0x20, 0x20, 0x20, 0x88, 0xDA,
-  0x2C, 0x2C, 0x2C, 0xAF, 0xAF, 0xAC, 0xAC, 0xAF,
-  0xAF, 0xAF, 0xAF, 0xAC, 0xAF, 0xAF, 0xAF, 0x2C,
-  0x85, 0xD9, 0xD9, 0xD9, 0xD9, 0xAC, 0xAC, 0xD9,
-  0xD9, 0xD9, 0xAC, 0x2C, 0x2C, 0x2C, 0x85, 0x85,
-  0x85, 0x2C, 0x2C, 0xAF, 0x2C, 0x91, 0x20, 0xAE,
-  0x20, 0xDB, 0x3D, 0xE8, 0xE8, 0x5C, 0xB2, 0x80,
-  0xB2, 0xAF, 0x48, 0xB2, 0x48, 0x89, 0x89, 0x3D,
-  0x21, 0x48, 0x6C, 0x2D, 0x2B, 0x41, 0xE3, 0xAE,
-  0xD9, 0x5C, 0xE8, 0xE8, 0xE8, 0x95, 0x33, 0x80,
-  0xAE, 0x33, 0x2B, 0x20, 0x20, 0x20, 0x20, 0x95,
-  0x85, 0x2C, 0x85, 0x2C, 0x2C, 0xAF, 0x2C, 0x2C,
-  0x2C, 0xAF, 0xAC, 0xAF, 0xAF, 0x2C, 0x2C, 0x2C,
-  0xDA, 0xAF, 0xD9, 0xD9, 0xAF, 0x2C, 0x2C, 0x2C,
-  0xAC, 0xD9, 0xAC, 0xAF, 0x2C, 0x85, 0x2C, 0x85,
-  0x85, 0x2C, 0x2C, 0x2C, 0x8A, 0x41, 0xDB, 0x33,
-  0x20, 0x95, 0xE8, 0xE8, 0xE8, 0xA3, 0xDB, 0x88,
-  0xDB, 0x80, 0xD6, 0x7E, 0x85, 0x2D, 0xE6, 0x5C,
-  0x21, 0x48, 0xD9, 0x7E, 0xD6, 0x2B, 0xCC, 0xAC,
-  0x85, 0xBC, 0xE8, 0xE8, 0xE8, 0xCD, 0x88, 0x5B,
-  0x41, 0x20, 0xAE, 0x20, 0x20, 0x20, 0x20, 0x74,
-  0xDA, 0x85, 0x85, 0x85, 0x2C, 0x2C, 0x2C, 0x2C,
-  0xAF, 0xAC, 0xD9, 0xD9, 0xAC, 0xAC, 0xAC, 0xD9,
-  0x8A, 0xAF, 0xAC, 0xAC, 0x2C, 0x85, 0x2C, 0xAF,
-  0xD9, 0xD9, 0xAF, 0xAF, 0xAF, 0x2C, 0xAF, 0x2C,
-  0x2C, 0x2C, 0x2C, 0xAF, 0x95, 0x20, 0x74, 0x20,
-  0x33, 0xA3, 0xE8, 0xE8, 0xE8, 0xE4, 0x7D, 0xCC,
-  0x6B, 0x33, 0xAE, 0x2C, 0x85, 0x2D, 0x9F, 0x73,
-  0xA1, 0x2D, 0x2C, 0xDA, 0x89, 0x48, 0xD3, 0xD9,
-  0x21, 0xA3, 0xE8, 0xE8, 0xE8, 0xE8, 0xE3, 0x20,
-  0x20, 0x20, 0xDB, 0x41, 0x20, 0x20, 0x20, 0x20,
-  0xDA, 0x2C, 0x2C, 0x2C, 0x2C, 0xAF, 0xAC, 0xAC,
-  0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0x95, 0x95, 0xD9,
-  0x2C, 0xD9, 0xD9, 0xAC, 0x2C, 0x2C, 0x85, 0xAF,
-  0xAF, 0xAF, 0xAC, 0xAC, 0xD9, 0xAC, 0xAF, 0xAC,
-  0xAC, 0x95, 0xD6, 0x7D, 0xAE, 0x88, 0x2B, 0x20,
-  0x6C, 0xE8, 0xE8, 0xE8, 0x73, 0xEE, 0x73, 0x2C,
-  0x89, 0x2B, 0x41, 0x33, 0xCC, 0xCC, 0x80, 0x3D,
-  0x2D, 0x74, 0x80, 0x48, 0x8D, 0x95, 0x48, 0x95,
-  0xEE, 0x5C, 0x5C, 0xE8, 0xE8, 0xE8, 0x24, 0x20,
-  0x20, 0x20, 0x5B, 0xDB, 0x20, 0x20, 0x20, 0x20,
-  0xAF, 0xAC, 0xD9, 0x95, 0xD6, 0xD6, 0xD6, 0x7D,
-  0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0xD9, 0xAC,
-  0xAC, 0xD9, 0xD9, 0xAC, 0x2C, 0x2C, 0x2C, 0xAF,
-  0xAC, 0xAC, 0xAC, 0xAC, 0xD9, 0xAC, 0xAC, 0xD9,
-  0xD6, 0x48, 0xE9, 0x95, 0x20, 0x2B, 0x41, 0x6B,
-  0x8D, 0xE8, 0xE8, 0xCD, 0x2B, 0x2B, 0x2C, 0x73,
-  0xCD, 0x48, 0xCA, 0x5B, 0x41, 0x5B, 0x74, 0xDA,
-  0x80, 0xE6, 0xC8, 0x85, 0xA1, 0x7D, 0x8D, 0x3D,
-  0x7E, 0xE9, 0x7D, 0xEE, 0xE8, 0xE8, 0x81, 0x20,
-  0x20, 0x20, 0xE3, 0xE3, 0x20, 0x20, 0x20, 0x20,
-  0x2D, 0xD9, 0xD6, 0x48, 0x6C, 0xE9, 0xA1, 0xD6,
-  0xD9, 0xD9, 0xAC, 0xD9, 0xD9, 0x95, 0xAC, 0x2C,
-  0x2C, 0x2C, 0x2C, 0xD9, 0xAC, 0x2C, 0x2C, 0x2C,
-  0xAF, 0x2C, 0xAF, 0xD9, 0xAC, 0xAF, 0xAF, 0x95,
-  0xB2, 0xE9, 0x21, 0x2B, 0x41, 0x2B, 0x20, 0x5B,
-  0x3D, 0xE8, 0xE8, 0x8D, 0x2B, 0x88, 0x5B, 0xE6,
-  0xBC, 0x73, 0x85, 0x89, 0x80, 0x5B, 0xE3, 0xAE,
-  0x2C, 0x8A, 0xD6, 0xB2, 0x2C, 0xA3, 0xA3, 0xD9,
-  0xA1, 0x2C, 0x85, 0x8D, 0xE8, 0xE8, 0x48, 0x20,
-  0x20, 0x20, 0xE3, 0x88, 0x20, 0x20, 0x20, 0x20,
-  0xAE, 0xD9, 0xB2, 0xE9, 0x6C, 0x48, 0xD6, 0xD9,
-  0x2C, 0x85, 0x2C, 0xD9, 0x7D, 0xD9, 0x2C, 0x85,
-  0x8D, 0x85, 0x2C, 0xAC, 0xAF, 0x2C, 0x2C, 0x85,
-  0x2C, 0x2C, 0xAF, 0xAC, 0xAC, 0xAF, 0xAF, 0xD9,
-  0xB2, 0x48, 0xB2, 0x20, 0x20, 0xCC, 0x20, 0x9F,
-  0xE8, 0xE8, 0xE8, 0xCD, 0x48, 0x89, 0xDB, 0x88,
-  0x2B, 0xE9, 0xCD, 0x2A, 0x48, 0x80, 0xAE, 0xAE,
-  0x7D, 0x48, 0x21, 0xEE, 0x3D, 0x2C, 0x48, 0x85,
-  0x2C, 0x95, 0x7D, 0x8C, 0xE8, 0xE8, 0xB2, 0x20,
-  0x20, 0x20, 0xDB, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0xDB, 0x2C, 0xB2, 0x48, 0x48, 0x7D, 0xD9, 0xAF,
-  0x85, 0x8A, 0x85, 0x7D, 0xB2, 0x95, 0x85, 0xDA,
-  0xD3, 0x85, 0xAF, 0xAC, 0x2C, 0x85, 0x85, 0x2C,
-  0xAC, 0xAC, 0xAC, 0xD9, 0xD9, 0xAC, 0x2C, 0x2C,
-  0xD9, 0xAC, 0x5B, 0x20, 0x20, 0xAE, 0x20, 0x2D,
-  0xE8, 0xE8, 0xE8, 0x7E, 0xD6, 0x48, 0xE9, 0xAE,
-  0x88, 0x5B, 0x80, 0x6C, 0xAE, 0xCA, 0x91, 0xE9,
-  0x43, 0x9F, 0xE6, 0x2C, 0x48, 0x21, 0xBC, 0x95,
-  0x95, 0xD6, 0x21, 0x7E, 0xE8, 0xE8, 0x7D, 0x20,
-  0x20, 0x20, 0x2B, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x6B, 0xDA, 0xD9, 0x48, 0xB2, 0xD9, 0x2C, 0x85,
-  0xDA, 0xDA, 0x2C, 0xA1, 0x48, 0xAC, 0xDA, 0x8D,
-  0x2A, 0xAC, 0x7D, 0x95, 0xAF, 0x85, 0x2C, 0x2C,
-  0xAC, 0xD9, 0x95, 0x7D, 0x95, 0xAC, 0x2C, 0xAF,
-  0x7D, 0xD6, 0x20, 0x20, 0x88, 0x9F, 0x20, 0xA1,
-  0xE8, 0xE8, 0xE8, 0xA3, 0xD6, 0x6C, 0xB2, 0x2C,
-  0x89, 0xE3, 0x88, 0xDB, 0xCC, 0x24, 0x7D, 0xEE,
-  0xB2, 0xCC, 0xAE, 0x2D, 0xDA, 0x2C, 0xD6, 0x2C,
-  0xB2, 0x2D, 0xD6, 0xEE, 0xE8, 0xE8, 0x95, 0x20,
-  0x20, 0x20, 0xDB, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x6B, 0xDA, 0x95, 0xA1, 0xB2, 0xAC, 0x85, 0x85,
-  0xDA, 0x2C, 0x95, 0xA1, 0x21, 0x2C, 0x8A, 0x2A,
-  0xAF, 0xA1, 0x48, 0xD6, 0xAF, 0x2C, 0x2C, 0xAC,
-  0xD9, 0xD9, 0x95, 0x7D, 0x95, 0xAC, 0xD9, 0x7D,
-  0x48, 0xE6, 0x20, 0x20, 0x33, 0x89, 0x6B, 0x95,
-  0xE8, 0xE8, 0xE8, 0xA3, 0x21, 0x48, 0xAF, 0xAF,
-  0x9F, 0xE9, 0x43, 0x33, 0x33, 0x2D, 0xDA, 0xCD,
-  0xD6, 0xAE, 0x85, 0x2C, 0x7D, 0xD6, 0x91, 0xB8,
-  0xD4, 0x48, 0x7D, 0xA3, 0xE8, 0xE8, 0x95, 0x20,
-  0x20, 0x33, 0xE3, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0x2C, 0x48, 0x6C, 0xB2, 0xAF, 0xDA, 0xDA,
-  0x85, 0xAF, 0xD9, 0x95, 0xAC, 0xDA, 0x8A, 0xDA,
-  0x7D, 0x48, 0x48, 0x7D, 0x2C, 0x85, 0x2C, 0xAF,
-  0xD9, 0xD9, 0x7D, 0x95, 0xD9, 0xD9, 0x95, 0xD6,
-  0x21, 0x24, 0x20, 0x20, 0x20, 0x5B, 0xDB, 0xAC,
-  0xE8, 0xE8, 0xE8, 0x3D, 0x7D, 0x48, 0xE6, 0x2D,
-  0x85, 0x81, 0x81, 0x48, 0xAE, 0xCA, 0x89, 0xCC,
-  0xAE, 0xDB, 0x2D, 0x95, 0x21, 0xCC, 0xDB, 0xAE,
-  0x91, 0xE9, 0x7D, 0x73, 0xE8, 0xE8, 0x48, 0x20,
-  0x6B, 0x74, 0x41, 0x88, 0x6B, 0x20, 0x20, 0x20,
-  0x6B, 0x95, 0xB2, 0xD6, 0xD9, 0x85, 0xDA, 0xDA,
-  0xDA, 0x2C, 0xAF, 0xAF, 0x2C, 0xDA, 0xDA, 0x85,
-  0xA1, 0xE9, 0x48, 0x95, 0x85, 0xDA, 0x85, 0xAC,
-  0xD9, 0xD9, 0x95, 0x95, 0xD9, 0xD9, 0xD9, 0x95,
-  0x95, 0x6C, 0x41, 0x93, 0x93, 0x41, 0xDB, 0x95,
-  0xE8, 0xE8, 0xE8, 0x3D, 0x95, 0xD4, 0x6C, 0x21,
-  0x2D, 0x95, 0xCD, 0x2C, 0xD6, 0xD9, 0x6C, 0x91,
-  0x89, 0x7D, 0xAC, 0x2A, 0x8D, 0xE6, 0xCC, 0x88,
-  0x74, 0x48, 0xD9, 0xE4, 0xE8, 0xE8, 0xE6, 0x88,
-  0x2B, 0x88, 0x20, 0x33, 0xDB, 0x2B, 0xDB, 0x20,
-  0x91, 0x7D, 0xD9, 0xD9, 0x85, 0x85, 0xDA, 0xDA,
-  0x85, 0xAF, 0xAC, 0xAF, 0x2C, 0x2C, 0x2C, 0x2C,
-  0xA1, 0xA1, 0xD6, 0xAF, 0x85, 0xDA, 0x85, 0x2C,
-  0xD9, 0xD9, 0x95, 0x95, 0xD9, 0xD9, 0xD9, 0xAC,
-  0x2C, 0x47, 0x87, 0x3E, 0x3E, 0xA4, 0x7B, 0x80,
-  0xA3, 0xE8, 0xE8, 0x5C, 0x7D, 0x48, 0xE6, 0xD9,
-  0xBC, 0xEE, 0x7D, 0x43, 0xD6, 0x21, 0x43, 0x6C,
-  0x43, 0x7D, 0x7D, 0xB2, 0x8A, 0xEE, 0x2C, 0xCA,
-  0xAE, 0x48, 0x2C, 0xE4, 0xE8, 0x5C, 0xCC, 0x88,
-  0x20, 0x20, 0x20, 0x20, 0x20, 0x41, 0x91, 0xE3,
-  0x21, 0xD9, 0x2C, 0x2C, 0xDA, 0xDA, 0xDA, 0x85,
-  0x2C, 0xAC, 0xD9, 0xD9, 0xAC, 0xAF, 0xAF, 0xAF,
-  0xD6, 0x7D, 0xD9, 0x2C, 0xDA, 0xDA, 0x85, 0xAC,
-  0xD9, 0x7D, 0x7D, 0xD9, 0xD9, 0xD9, 0x2C, 0x2C,
-  0xB8, 0x9C, 0xEC, 0x62, 0x6F, 0x62, 0x70, 0x3C,
-  0xAE, 0xCD, 0xE8, 0xE8, 0x8C, 0x7D, 0xC8, 0x3D,
-  0x8A, 0xE9, 0x2D, 0x9E, 0xA1, 0xD6, 0x48, 0x73,
-  0x81, 0xD6, 0xD6, 0xAE, 0x5B, 0x2D, 0xA3, 0xA3,
-  0x21, 0x21, 0xCD, 0xE8, 0xC0, 0x56, 0x31, 0x20,
-  0x20, 0x20, 0x20, 0x20, 0x20, 0x33, 0xCC, 0xDB,
-  0x42, 0x85, 0x85, 0x85, 0x85, 0x85, 0x2C, 0x2C,
-  0xAC, 0xD9, 0xD9, 0xD9, 0xAC, 0xAF, 0xAF, 0xAF,
-  0xD9, 0x95, 0xAC, 0x2C, 0x85, 0x85, 0x2C, 0xD9,
-  0x7D, 0xD6, 0xD6, 0xD9, 0xAC, 0xAF, 0x8A, 0xBC,
-  0xC2, 0x68, 0x2E, 0x4B, 0xC9, 0x8B, 0x62, 0x87,
-  0x3C, 0x74, 0xBC, 0xE8, 0xE8, 0xE4, 0xEE, 0xA1,
-  0xE9, 0x21, 0xE6, 0x89, 0x48, 0x7D, 0xB2, 0x5C,
-  0x6C, 0x7D, 0x21, 0x80, 0xE3, 0x33, 0xCC, 0x2C,
-  0x3D, 0x3D, 0xE8, 0xE8, 0xEC, 0xCB, 0x5A, 0x6B,
-  0x20, 0x20, 0x20, 0x20, 0x20, 0x88, 0x41, 0x51,
-  0x49, 0x28, 0x85, 0x85, 0x85, 0x85, 0x2C, 0xAF,
-  0xAC, 0xAC, 0xAF, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C,
-  0xD9, 0x95, 0xD9, 0x2C, 0x85, 0x85, 0x2C, 0xD9,
-  0xB2, 0xB2, 0x2C, 0x2A, 0x79, 0x79, 0x97, 0x44,
-  0xED, 0x29, 0x32, 0x62, 0x4B, 0x62, 0x6F, 0x22,
-  0xF3, 0x6B, 0x33, 0x85, 0x73, 0xE4, 0x2D, 0x2B,
-  0xCC, 0x9F, 0xDA, 0xBC, 0x48, 0xD6, 0xA1, 0xE4,
-  0xE9, 0xD6, 0xD9, 0x2A, 0xB2, 0x2B, 0x2B, 0xA1,
-  0xB8, 0xE8, 0xE8, 0xE8, 0xEC, 0x3E, 0x30, 0x20,
-  0x20, 0x20, 0x20, 0x20, 0x20, 0x6B, 0x54, 0xDC,
-  0xC9, 0x53, 0xBC, 0x2C, 0x2C, 0x2C, 0xAF, 0xAF,
-  0xAF, 0xAC, 0xAF, 0xAC, 0xAC, 0x2C, 0xAF, 0xAC,
-  0x2C, 0x7D, 0xD9, 0x2C, 0x85, 0xDA, 0xAF, 0x7D,
-  0xB2, 0xAC, 0xC6, 0xBA, 0x4C, 0xEF, 0xA7, 0xEF,
-  0xEC, 0x7A, 0x62, 0x4B, 0x62, 0x4B, 0x8B, 0x4B,
-  0x3A, 0x52, 0x20, 0x6B, 0x21, 0x73, 0xAC, 0x2B,
-  0x41, 0x33, 0x48, 0x67, 0xA1, 0xD6, 0xD6, 0x5C,
-  0xE9, 0xD6, 0x2C, 0xEE, 0xB2, 0x9F, 0x8A, 0x95,
-  0x4D, 0xE8, 0xE8, 0x3D, 0x7A, 0x57, 0xD1, 0x7B,
-  0x20, 0x20, 0x20, 0x20, 0x6B, 0xCF, 0xBA, 0x3E,
-  0x3E, 0xD0, 0xBC, 0xAC, 0xAC, 0x2C, 0x2C, 0xAC,
-  0xD9, 0xD9, 0x95, 0x95, 0x7D, 0x95, 0x95, 0xD9,
-  0x85, 0xD9, 0xAF, 0xDA, 0xDA, 0x85, 0xAC, 0x21,
-  0xB2, 0x2A, 0xBA, 0x57, 0x2E, 0x2E, 0x2E, 0x7A,
-  0x32, 0x62, 0x8B, 0x4B, 0x8B, 0x4B, 0x4B, 0x4B,
-  0xC9, 0x4A, 0x5F, 0x20, 0x20, 0x2D, 0xA3, 0xD9,
-  0xCA, 0x88, 0xDB, 0x24, 0x48, 0x7D, 0xB2, 0xE4,
-  0x2D, 0x7D, 0x7D, 0x81, 0xA1, 0xDA, 0x21, 0xDA,
-  0xE4, 0xE8, 0xEE, 0xF1, 0x2E, 0x57, 0x82, 0x76,
-  0x52, 0x4F, 0x4F, 0x98, 0xDE, 0xB5, 0xEC, 0x2E,
-  0x3E, 0x6D, 0x85, 0x2C, 0xAC, 0xAC, 0xD9, 0xD9,
-  0x95, 0xD6, 0x7D, 0x7D, 0x95, 0xD9, 0xD9, 0xD9,
-  0xDA, 0x2C, 0x85, 0xDA, 0xDA, 0x2C, 0x95, 0xB2,
-  0x21, 0xB8, 0xED, 0x2E, 0x3E, 0x4B, 0xC9, 0x4B,
-  0x8B, 0x62, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B,
-  0x22, 0x6F, 0xCE, 0x20, 0x20, 0x20, 0x80, 0xCD,
-  0xDA, 0x2D, 0x2B, 0xDB, 0xE9, 0xD6, 0x95, 0x5C,
-  0x2D, 0x7D, 0x7D, 0xAF, 0xAF, 0xAC, 0xEE, 0x5C,
-  0xE8, 0xE8, 0xEB, 0x25, 0x7A, 0x57, 0x39, 0xE1,
-  0x83, 0xA8, 0x55, 0x83, 0x82, 0x57, 0x32, 0x8B,
-  0x62, 0x6D, 0xEB, 0x95, 0xD9, 0xD9, 0xD9, 0xD9,
-  0xD9, 0xD9, 0xD9, 0xAF, 0x2C, 0x2C, 0x2C, 0x2C,
-  0xDA, 0x2C, 0x85, 0x85, 0x85, 0xAC, 0xD6, 0x21,
-  0x95, 0x6E, 0xED, 0x57, 0x62, 0x4B, 0x8B, 0x4B,
-  0x4B, 0x62, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x62,
-  0x62, 0x62, 0x25, 0x3C, 0x20, 0x20, 0x20, 0xE3,
-  0x2A, 0xBC, 0x7D, 0xCA, 0x6C, 0xD6, 0x95, 0x3D,
-  0x81, 0x7D, 0xD6, 0xD6, 0xDA, 0x73, 0xE8, 0xE8,
-  0xE8, 0x4D, 0x94, 0xED, 0x72, 0x3A, 0xF1, 0xA7,
-  0x39, 0xED, 0x39, 0xEF, 0x57, 0x32, 0x8B, 0x4B,
-  0x62, 0x62, 0xA6, 0x2A, 0xD9, 0xD9, 0xD9, 0xD9,
-  0x2C, 0x2C, 0x85, 0x85, 0x85, 0x85, 0x85, 0x85,
-  0x85, 0x2C, 0x2C, 0xAF, 0xAC, 0x95, 0x21, 0x7D,
-  0xAC, 0x8C, 0x46, 0xC4, 0x62, 0x8B, 0x4B, 0x4B,
-  0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B,
-  0x4B, 0x62, 0xC9, 0x30, 0x7B, 0x20, 0x20, 0x20,
-  0x41, 0x4D, 0x3D, 0x85, 0x48, 0x21, 0xDA, 0x3D,
-  0xE9, 0xD6, 0xD9, 0xCD, 0x5C, 0xE8, 0xE8, 0xE8,
-  0xE8, 0x4D, 0x71, 0x46, 0xEC, 0x2E, 0x72, 0xEC,
-  0x29, 0x29, 0x7C, 0x29, 0x2E, 0x4B, 0x4B, 0x62,
-  0x62, 0x4B, 0x3A, 0xAD, 0xE2, 0xAF, 0xD9, 0xD9,
-  0x2C, 0xDA, 0xDA, 0xDA, 0xDA, 0x85, 0x2C, 0x2C,
-  0x2C, 0xAF, 0xAC, 0xD9, 0x95, 0xD6, 0xD6, 0xD9,
-  0x2C, 0x8C, 0xBA, 0x7C, 0x2E, 0x4B, 0x4B, 0x4B,
-  0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B,
-  0x4B, 0x62, 0xC9, 0xDC, 0x34, 0x20, 0x20, 0x20,
-  0x20, 0xAC, 0xE8, 0x5C, 0x8C, 0xBC, 0xE4, 0xE8,
-  0xEE, 0x2A, 0xA3, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8,
-  0xE4, 0x7E, 0x65, 0x46, 0x29, 0x62, 0x62, 0x2E,
-  0x2E, 0x72, 0x2E, 0x2E, 0x32, 0x4B, 0x4B, 0x62,
-  0x4B, 0x4B, 0x4B, 0x32, 0x61, 0x9D, 0x2C, 0xD9,
-  0x2C, 0x85, 0xDA, 0x85, 0x2C, 0xAF, 0xAF, 0xAF,
-  0x2C, 0xAC, 0xD9, 0x95, 0xD6, 0x7D, 0x95, 0xAC,
-  0x2C, 0xDA, 0x40, 0x7C, 0x2E, 0x4B, 0x4B, 0x4B,
-  0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B,
-  0x4B, 0x62, 0x62, 0x22, 0xB7, 0xCE, 0x20, 0x20,
-  0x20, 0x95, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8,
-  0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0x5C,
-  0x3D, 0xE9, 0x9A, 0x46, 0x7C, 0x32, 0x8B, 0x62,
-  0x4B, 0x8B, 0x8B, 0x4B, 0x4B, 0x4B, 0x4B, 0x62,
-  0x4B, 0x4B, 0x4B, 0x4B, 0x62, 0x61, 0x4E, 0xDA,
-  0x85, 0x85, 0x85, 0x2C, 0xD9, 0xD9, 0xD9, 0xD9,
-  0x85, 0xD9, 0x7D, 0x21, 0x21, 0xD6, 0xAC, 0x2C,
-  0x2C, 0xDA, 0xDD, 0x77, 0x8B, 0x62, 0x4B, 0x4B,
-  0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B,
-  0x3E, 0x8B, 0x32, 0xC9, 0x22, 0x68, 0x88, 0x33,
-  0xA1, 0x73, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8,
-  0xE8, 0xE8, 0xE8, 0x5C, 0x5C, 0x5C, 0x5C, 0x3D,
-  0x89, 0x20, 0x54, 0x23, 0x29, 0x2E, 0x4B, 0x62,
-  0x4B, 0x3E, 0x4B, 0x62, 0x4B, 0x4B, 0x4B, 0x8B,
-  0x8B, 0xC9, 0x6F, 0x4B, 0x8B, 0x4B, 0x78, 0xE2,
-  0x8A, 0x8A, 0x85, 0xAC, 0xD9, 0x7D, 0xD9, 0xAC,
-  0x2C, 0xD9, 0xD6, 0xB2, 0x21, 0x7D, 0xAF, 0x85,
-  0x2C, 0xDA, 0x40, 0xEF, 0x62, 0x62, 0x4B, 0x4B,
-  0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B,
-  0x4B, 0x4B, 0x8B, 0x4B, 0xC9, 0x63, 0xB4, 0x5C,
-  0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8,
-  0xE8, 0xE8, 0xE8, 0xE8, 0x5C, 0x5C, 0xCD, 0xAE,
-  0x20, 0x20, 0xCE, 0xE1, 0x57, 0x32, 0x4B, 0x4B,
-  0x8B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B,
-  0x8B, 0x4B, 0x62, 0x4B, 0x62, 0x2E, 0x61, 0x28,
-  0x8D, 0xDA, 0xAF, 0xD9, 0x95, 0x95, 0xD9, 0xAF,
-  0xAF, 0xD9, 0xD6, 0xB2, 0x21, 0xD9, 0x2C, 0x85,
-  0xAF, 0xEB, 0xE1, 0x57, 0x2E, 0x62, 0x4B, 0x4B,
-  0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B,
-  0x4B, 0x4B, 0x4B, 0x4B, 0x3E, 0x9B, 0x31, 0x6E,
-  0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8,
-  0x5C, 0xE8, 0xE8, 0xE8, 0x3D, 0x7D, 0x33, 0x6B,
-  0x20, 0x20, 0x34, 0x23, 0x29, 0x3E, 0x4B, 0x4B,
-  0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B,
-  0x4B, 0x3E, 0x62, 0x62, 0x2E, 0xC4, 0x49, 0xD5,
-  0xDA, 0xD9, 0xD6, 0xA1, 0xA1, 0x21, 0xD9, 0xD9,
-  0xD9, 0x95, 0x21, 0x48, 0xD6, 0xAC, 0x85, 0x85,
-  0xAF, 0xB6, 0x5D, 0x2E, 0x32, 0x4B, 0x4B, 0x4B,
-  0x4B, 0x4B, 0x62, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B,
-  0x4B, 0x4B, 0x4B, 0x4B, 0x62, 0x2E, 0x45, 0xDE,
-  0xDA, 0x5C, 0xE8, 0x5C, 0xE8, 0xE8, 0x5C, 0xE8,
-  0x5C, 0x5C, 0xA3, 0xAC, 0x2B, 0x20, 0x20, 0x20,
-  0x20, 0x20, 0x34, 0x23, 0x29, 0x62, 0x4B, 0x4B,
-  0x4B, 0x4B, 0x4B, 0x4B, 0x62, 0x4B, 0x4B, 0x4B,
-  0x4B, 0x3E, 0x3E, 0x63, 0x40, 0x97, 0x28, 0xDA,
-  0xD9, 0xA1, 0x48, 0xE9, 0x48, 0x21, 0xD9, 0xD9,
-  0xA1, 0xB2, 0xB2, 0xA1, 0x21, 0xAC, 0x85, 0x2C,
-  0xDA, 0x36, 0x77, 0x72, 0x62, 0x8B, 0x62, 0x4B,
-  0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B,
-  0x4B, 0x4B, 0x4B, 0x4B, 0x3E, 0xEC, 0x2F, 0x51,
-  0xE3, 0xAE, 0x48, 0x2C, 0xDA, 0xDA, 0x85, 0xAC,
-  0x48, 0x9E, 0x88, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0x41, 0xA0, 0x23, 0x72, 0x2E, 0x4B, 0x4B,
-  0x4B, 0x62, 0x62, 0x4B, 0x4B, 0x4B, 0x2E, 0x8B,
-  0xF0, 0x4C, 0x40, 0xC2, 0x90, 0x8D, 0x85, 0xD9,
-  0xA1, 0x6C, 0x6C, 0x48, 0xD6, 0xD9, 0xAF, 0xAC,
-  0xA1, 0xD6, 0xD6, 0xB2, 0xD6, 0xAC, 0x85, 0x85,
-  0x4D, 0xBE, 0x39, 0x4C, 0x57, 0x2E, 0x2E, 0x2E,
-  0x3E, 0x3E, 0x62, 0x3E, 0x4B, 0x4B, 0x4B, 0x4B,
-  0x4B, 0x4B, 0x4B, 0x8B, 0x8B, 0x57, 0x60, 0x76,
-  0x52, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0x3C, 0xA0, 0x23, 0x7C, 0x2E, 0x4B, 0x4B,
-  0x8B, 0x62, 0x4B, 0x4B, 0x3E, 0x7A, 0xF0, 0x29,
-  0x36, 0x97, 0xBC, 0x8A, 0x8D, 0xDA, 0xD9, 0x48,
-  0x81, 0x2D, 0x48, 0xD6, 0xD9, 0xAF, 0x2C, 0x2C,
-  0xAC, 0xAF, 0xD9, 0x7D, 0x7D, 0x2C, 0x85, 0x85,
-  0x85, 0xB4, 0x66, 0x23, 0x46, 0x2F, 0x60, 0x68,
-  0x77, 0x29, 0x29, 0xF0, 0x2E, 0x2E, 0x62, 0x4B,
-  0x4B, 0x4B, 0x4B, 0x4B, 0x32, 0x7C, 0x83, 0xB3,
-  0x54, 0x6B, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x6B, 0x7B, 0xC3, 0xE7, 0x39, 0x72, 0x62, 0x62,
-  0x62, 0x62, 0x62, 0x2E, 0x29, 0x77, 0xA7, 0x36,
-  0xB8, 0x85, 0x85, 0x8D, 0x8D, 0x85, 0xB2, 0x2D,
-  0x2D, 0xE9, 0xD6, 0xD9, 0xAF, 0x2C, 0x85, 0x85,
-  0x2A, 0x85, 0xAC, 0x95, 0x95, 0xAF, 0x85, 0x85,
-  0xAF, 0x8C, 0xDF, 0xC6, 0xB1, 0xD1, 0xE5, 0xE7,
-  0x83, 0x23, 0x5D, 0x60, 0x39, 0x77, 0xEC, 0x2E,
-  0x2E, 0x32, 0x32, 0x2E, 0x7C, 0x5D, 0x35, 0xA2,
-  0x54, 0x6B, 0x6B, 0x20, 0x6B, 0x20, 0x20, 0x20,
-  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x6B, 0x88, 0xC1, 0x35, 0xE1, 0x77, 0x57, 0x2E,
-  0x2E, 0x72, 0x29, 0x77, 0x60, 0xB5, 0x44, 0xE2,
-  0x2C, 0x2C, 0xDA, 0x8A, 0xDA, 0xAF, 0xA1, 0x2D,
-  0xE9, 0xD6, 0xD9, 0xAF, 0x2C, 0x85, 0x85, 0x85,
-  0xEE, 0xAF, 0xD9, 0x7D, 0xD9, 0x2C, 0xDA, 0x85,
-  0xAC, 0xAF, 0x85, 0xDA, 0x8A, 0x2A, 0xE2, 0x50,
-  0x86, 0xD7, 0x75, 0x35, 0xA8, 0xE7, 0xE1, 0x5D,
-  0x68, 0x7C, 0xF1, 0x68, 0xE1, 0xBF, 0xA2, 0xC1,
-  0x52, 0x2B, 0x7D, 0xAC, 0xAF, 0x2C, 0x2C, 0x2C,
-  0x2C, 0x85, 0x85, 0x85, 0x2C, 0x2C, 0x2C, 0x95,
-  0xE9, 0x74, 0xCE, 0xE0, 0xE7, 0x60, 0x77, 0x77,
-  0x7C, 0xEF, 0x5D, 0x23, 0x3F, 0xB6, 0x8A, 0x2C,
-  0xAC, 0xAF, 0x85, 0x8A, 0x85, 0xD9, 0x48, 0x48,
-  0xB2, 0x95, 0x95, 0xD9, 0x85, 0xDA, 0x85, 0x85,
-  0xD3, 0xB2, 0x21, 0x7D, 0xAC, 0x2C, 0xDA, 0x85,
-  0xAC, 0xAC, 0x85, 0x85, 0x85, 0x2C, 0xAF, 0x2C,
-  0xDA, 0x8C, 0x79, 0xC7, 0xB0, 0x51, 0xB3, 0x35,
-  0xBF, 0xE5, 0xE7, 0xA8, 0xE0, 0xA2, 0xC1, 0x34,
-  0x7D, 0x85, 0xAC, 0xD9, 0xAC, 0xAF, 0xAC, 0xAC,
-  0xAF, 0x2C, 0x2C, 0x2C, 0x2C, 0xAF, 0xAF, 0x85,
-  0xC8, 0xCD, 0x6A, 0x26, 0x35, 0x3F, 0x83, 0x23,
-  0x23, 0xE7, 0xBF, 0x96, 0xEB, 0xDA, 0xDA, 0x2C,
-  0x2C, 0x2C, 0x85, 0xDA, 0x2C, 0x7D, 0xA1, 0x48,
-  0xB2, 0x21, 0xD6, 0xD9, 0x2C, 0xDA, 0x85, 0xAF,
-  0xAF, 0x2D, 0xE9, 0x7D, 0xAC, 0x2C, 0x85, 0x2C,
-  0xD9, 0xD9, 0xAF, 0x85, 0x85, 0x85, 0x2C, 0x2C,
-  0x2C, 0x85, 0xD9, 0x21, 0xAC, 0x2C, 0xBD, 0xA5,
-  0xC3, 0xA2, 0xA2, 0xA2, 0x26, 0xC1, 0xCE, 0x2A,
-  0xAF, 0x95, 0xD9, 0x2C, 0x2C, 0x85, 0x2C, 0xAF,
-  0xAC, 0x2C, 0x85, 0x2C, 0xAF, 0x2C, 0x85, 0xDA,
-  0x8D, 0x2A, 0x85, 0x34, 0xC1, 0xB3, 0x76, 0x35,
-  0xE0, 0x30, 0xA5, 0xB6, 0x2C, 0x85, 0x85, 0x85,
-  0xAF, 0x2C, 0x85, 0x85, 0xD9, 0xD6, 0xA1, 0xA1,
-  0x48, 0xA1, 0xD6, 0xAF, 0xDA, 0x8A, 0x2C, 0xD9,
-  0xB2, 0x2D, 0x48, 0xD9, 0xAF, 0x2C, 0x2C, 0x85,
-  0xAF, 0xAC, 0x2C, 0x85, 0x85, 0x85, 0xAF, 0xAC,
-  0xAC, 0x2C, 0xD9, 0xD6, 0xD6, 0x21, 0xB2, 0x2C,
-  0xC8, 0x3B, 0x65, 0xC5, 0xCE, 0x8E, 0xC8, 0x2C,
-  0xD9, 0x95, 0xAC, 0x2C, 0x2C, 0x2C, 0xAF, 0xAC,
-  0xAC, 0xAF, 0x2C, 0x85, 0x2C, 0x2C, 0x2C, 0x85,
-  0xDA, 0x2C, 0xD6, 0xAF, 0x59, 0x65, 0xDE, 0xF3,
-  0xF3, 0x59, 0xBC, 0xAC, 0xAF, 0x85, 0x85, 0x85,
-  0xAF, 0xD9, 0xAF, 0x2C, 0xD9, 0xD6, 0xD6, 0xD6,
-  0x21, 0xD6, 0xD9, 0xDA, 0x8D, 0x8A, 0x2C, 0xD9,
-  0xB2, 0xA1, 0xD6, 0xAC, 0x2C, 0x2C, 0x2C, 0x85,
-  0x2C, 0xAC, 0x2C, 0xDA, 0xDA, 0x85, 0xAF, 0xD9,
-  0xD9, 0xAC, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xAC,
-  0x85, 0x2A, 0x4D, 0xBC, 0x85, 0xAC, 0xAF, 0xAF,
-  0xAC, 0xD9, 0xAF, 0x2C, 0xAF, 0xD9, 0xD9, 0xAC,
-  0xAC, 0xAF, 0x85, 0x2C, 0x85, 0x2C, 0x2C, 0x2C,
-  0x2C, 0xD9, 0xB2, 0xD4, 0xD6, 0x2C, 0x8A, 0xDA,
-  0xC8, 0x85, 0x2C, 0xAC, 0x2C, 0xDA, 0xDA, 0x85,
-  0xAF, 0xAC, 0xD9, 0xAC, 0xD9, 0xD9, 0xD9, 0xD9,
-  0xD9, 0xAC, 0xDA, 0x8D, 0xBC, 0xDA, 0xD9, 0x95,
-  0x95, 0xD9, 0xD9, 0xAF, 0x2C, 0x2C, 0x2C, 0x85,
-  0x2C, 0xAF, 0xAF, 0x85, 0x85, 0x85, 0x2C, 0xAC,
-  0xD9, 0xAF, 0xAF, 0xAF, 0x2C, 0x2C, 0x2C, 0x85,
-  0x8A, 0x2A, 0x8D, 0x2C, 0xD9, 0x95, 0xAC, 0xAC,
-  0xD9, 0xD9, 0xD9, 0xD9, 0x95, 0x95, 0xD9, 0xAF,
-  0xAF, 0x2C, 0x85, 0x85, 0x85, 0x85, 0x85, 0x2C,
-  0x85, 0x2C, 0xD9, 0xD9, 0xD9, 0x2C, 0x2C, 0x2C,
-  0x2C, 0x85, 0x85, 0xAF, 0xAF, 0x85, 0x85, 0x85,
-  0xAF, 0xD9, 0xD9, 0xAC, 0xAF, 0x2C, 0x2C, 0x2C,
-  0x2C, 0x85, 0x8A, 0x2A, 0x8D, 0x2C, 0xD9, 0xD9,
-  0x2C, 0xAC, 0xAF, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C,
-  0x85, 0xAF, 0xAC, 0x2C, 0x2C, 0x2C, 0x2C, 0xAC,
-  0xD9, 0xD9, 0xAF, 0x85, 0x85, 0x85, 0xDA, 0xDA,
-  0x8A, 0x8A, 0x85, 0xAC, 0xD9, 0xD9, 0xAC, 0xD9,
-  0xD6, 0xD6, 0x7D, 0x95, 0x7D, 0xD9, 0xAF, 0xAF,
-  0xAF, 0x2C, 0x85, 0x85, 0xDA, 0x85, 0x2C, 0x85,
-  0x85, 0x2C, 0xAF, 0xAC, 0xAF, 0xAF, 0x2C, 0x2C,
-  0x2C, 0x2C, 0x2C, 0xAF, 0xAC, 0x2C, 0x2C, 0x2C,
-  0x2C, 0xAF, 0xD9, 0xAC, 0xAF, 0x2C, 0x85, 0x85,
-  0x85, 0xDA, 0x8D, 0x8A, 0x85, 0xAC, 0x95, 0xD9
-};
-
-#define INCLUDE_LINUX_LOGOBW
-#define INCLUDE_LINUX_LOGO16
-#include <linux/linux_logo.h>
+  #define LINUX_LOGO_COLORS 214
+  #define INCLUDE_LINUX_LOGO16
+  #define INCLUDE_LINUX_LOGOBW
 
+  #ifdef INCLUDE_LINUX_LOGO_DATA
+    #include "linux_logo_vr.h"
+  #endif
 #else
-
-/* prototypes only */
-extern unsigned char linux_logo_red[];
-extern unsigned char linux_logo_green[];
-extern unsigned char linux_logo_blue[];
-extern unsigned char linux_logo[];
-extern unsigned char linux_logo_bw[];
-extern unsigned char linux_logo16_red[];
-extern unsigned char linux_logo16_green[];
-extern unsigned char linux_logo16_blue[];
-extern unsigned char linux_logo16[];
-
+  #include "linux_logo_sgi.h"
 #endif
diff -ruN linux-mips/include/asm-mips/linux_logo_sgi.h linux-vr/include/asm-mips/linux_logo_sgi.h
--- linux-mips/include/asm-mips/linux_logo_sgi.h	Wed Dec 31 16:00:00 1969
+++ linux-vr/include/asm-mips/linux_logo_sgi.h	Tue Feb 15 05:38:58 2000
@@ -0,0 +1,941 @@
+/* $Id: linux_logo_sgi.h,v 1.1 2000/02/15 13:38:58 brad Exp $
+ *
+ * include/asm-mips/linux_logo.h: This is a linux logo
+ *                                to be displayed on boot.
+ *
+ * Copyright (C) 1996 Larry Ewing (lewing@isc.tamu.edu)
+ * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
+ *
+ * You can put anything here, but:
+ * LINUX_LOGO_COLORS has to be less than 224
+ * image size has to be 80x80
+ * values have to start from 0x20
+ * (i.e. RGB(linux_logo_red[0],
+ *	     linux_logo_green[0],
+ *	     linux_logo_blue[0]) is color 0x20)
+ * BW image has to be 80x80 as well, with MS bit
+ * on the left
+ * Serial_console ascii image can be any size,
+ * but should contain %s to display the version
+ */
+ 
+#include <linux/init.h>
+#include <linux/version.h>
+
+#define linux_logo_banner "Linux/MIPS version " UTS_RELEASE
+
+#define LINUX_LOGO_COLORS 212
+
+#ifdef INCLUDE_LINUX_LOGO_DATA
+
+unsigned char linux_logo_red[] __initdata = {
+  0x03, 0x82, 0xE9, 0xBF, 0x42, 0xC9, 0x7E, 0xC0,
+  0xE9, 0xE3, 0xC2, 0x24, 0xA4, 0x65, 0xEC, 0xC4,
+  0x82, 0x9F, 0xF3, 0x12, 0x5F, 0xA0, 0xC2, 0xED,
+  0x3E, 0xD5, 0xDB, 0xA0, 0x1C, 0xF4, 0xEB, 0xA4,
+  0xCD, 0x0A, 0x9A, 0x51, 0xCC, 0xBE, 0xC0, 0xBA,
+  0x74, 0xDC, 0xAA, 0xF6, 0xD3, 0xC5, 0xE6, 0x26,
+  0xC2, 0x83, 0x38, 0xEA, 0x49, 0xB0, 0xED, 0xE5,
+  0xF4, 0x96, 0x96, 0x1B, 0xFA, 0xCC, 0xF2, 0x0F,
+  0xCD, 0xE5, 0xF4, 0xD3, 0x50, 0x7A, 0xB5, 0xDE,
+  0xD5, 0xB6, 0x60, 0x0A, 0x6A, 0xEA, 0xD4, 0xEB,
+  0xC1, 0xCA, 0xEA, 0xEC, 0x2A, 0x96, 0x95, 0xDC,
+  0xE4, 0xCE, 0xEC, 0x1E, 0xDC, 0x8A, 0xD1, 0xF6,
+  0x3C, 0x5E, 0xC6, 0xB4, 0xB2, 0xAC, 0xBA, 0x9E,
+  0x0F, 0x59, 0xBA, 0xFA, 0xCC, 0xBF, 0x82, 0xCE,
+  0xE6, 0x4F, 0xAA, 0x4C, 0xCA, 0x8E, 0x8E, 0xDF,
+  0x2C, 0xB6, 0x3B, 0xDE, 0xCE, 0xEE, 0x46, 0x4A,
+  0x6F, 0x7A, 0x82, 0xE4, 0xAA, 0x88, 0xE2, 0xCE,
+  0xAE, 0xB6, 0x70, 0xC2, 0x9A, 0xDA, 0x35, 0x9E,
+  0x95, 0xC0, 0x7E, 0x8C, 0xC2, 0xB6, 0xCE, 0xB9,
+  0xD5, 0xAA, 0xC1, 0xF4, 0xC7, 0xB6, 0xB6, 0xA3,
+  0xF2, 0x68, 0xDB, 0x76, 0xDC, 0x57, 0xD3, 0xA8,
+  0xC0, 0xEF, 0x46, 0xF4, 0x2F, 0xD7, 0x53, 0x36,
+  0xE6, 0xA7, 0xCA, 0xCB, 0x7E, 0xE4, 0x86, 0x9A,
+  0xCE, 0x94, 0xB4, 0x1D, 0xDA, 0xCE, 0x6C, 0xE6,
+  0x9E, 0xC6, 0xDA, 0x16, 0xFA, 0xAA, 0x56, 0xB6,
+  0xFE, 0x6E, 0xEA, 0xCE, 0xE5, 0xCC, 0xDB, 0xD3,
+  0xED, 0xDC, 0xF4, 0x72
+};
+
+unsigned char linux_logo_green[] __initdata = {
+  0x03, 0x82, 0xC4, 0x83, 0x42, 0xA2, 0x4A, 0xA4,
+  0xE5, 0xA6, 0xC2, 0x24, 0xA4, 0x65, 0xB4, 0x94,
+  0x66, 0x87, 0xB6, 0x12, 0x44, 0x6C, 0x96, 0xD4,
+  0x36, 0x95, 0xB2, 0x92, 0x0E, 0xF4, 0xBC, 0x77,
+  0xA5, 0x0A, 0x92, 0x52, 0xB4, 0x9A, 0x8C, 0xB2,
+  0x74, 0xC2, 0x8E, 0xBD, 0xA2, 0xCA, 0xD2, 0x12,
+  0xB6, 0x61, 0x24, 0xDA, 0x33, 0x79, 0xCB, 0xAC,
+  0xDA, 0x84, 0x7A, 0x1B, 0xFA, 0x8D, 0xBE, 0x06,
+  0x93, 0xBB, 0xBC, 0xAB, 0x44, 0x62, 0x83, 0xDA,
+  0x9B, 0xA2, 0x4C, 0x04, 0x6A, 0xB6, 0xC8, 0xBD,
+  0x8D, 0xB6, 0xAD, 0xEC, 0x2A, 0x68, 0x62, 0x9D,
+  0xC4, 0xC4, 0xB4, 0x13, 0xA3, 0x8A, 0xD2, 0xD6,
+  0x3C, 0x5D, 0x8C, 0x7E, 0x82, 0xAC, 0x96, 0x7E,
+  0x0D, 0x5A, 0xBA, 0xBB, 0xCC, 0xBE, 0x76, 0xB6,
+  0xDE, 0x4E, 0x9A, 0x3C, 0xBE, 0x8E, 0x6E, 0xCB,
+  0x1C, 0xAA, 0x2E, 0xBE, 0xAA, 0xDE, 0x3E, 0x4B,
+  0x4D, 0x7A, 0x54, 0xE4, 0x8E, 0x6E, 0xCA, 0x9B,
+  0x70, 0x9E, 0x5A, 0xAA, 0x9A, 0xBE, 0x34, 0x9E,
+  0x71, 0x9E, 0x7E, 0x5F, 0xAA, 0x8A, 0xBE, 0x91,
+  0xCE, 0x88, 0x92, 0xDB, 0xC6, 0xAB, 0x8A, 0x72,
+  0xE2, 0x44, 0xC3, 0x54, 0xAA, 0x45, 0xBB, 0x92,
+  0xBA, 0xC4, 0x46, 0xCA, 0x2D, 0xD6, 0x3B, 0x1A,
+  0xC2, 0x7E, 0xA6, 0xCB, 0x7A, 0xDC, 0x86, 0x72,
+  0xB6, 0x94, 0xB4, 0x1C, 0xBC, 0xAE, 0x4C, 0xD6,
+  0x62, 0x86, 0xD3, 0x16, 0xF6, 0x7A, 0x55, 0x79,
+  0xFE, 0x6E, 0xC6, 0xC6, 0xAA, 0x93, 0xDC, 0x9D,
+  0xAE, 0xA4, 0xD4, 0x56
+};
+
+unsigned char linux_logo_blue[] __initdata = {
+  0x04, 0x84, 0x10, 0x0C, 0x41, 0x14, 0x04, 0x78,
+  0xC7, 0x0E, 0xC4, 0x24, 0xA4, 0x64, 0x0C, 0x0D,
+  0x17, 0x24, 0x0D, 0x13, 0x11, 0x07, 0x40, 0x22,
+  0x0C, 0x0C, 0x11, 0x78, 0x06, 0xF4, 0x0B, 0x0A,
+  0x47, 0x0B, 0x7C, 0x54, 0x6C, 0x0C, 0x0D, 0x9C,
+  0x73, 0x54, 0x14, 0x0C, 0x0F, 0xC7, 0x94, 0x04,
+  0x94, 0x17, 0x0A, 0x6C, 0x08, 0x0F, 0x14, 0x0B,
+  0x12, 0x68, 0x28, 0x11, 0xFA, 0x0A, 0x34, 0x09,
+  0x0A, 0x2F, 0x15, 0x19, 0x14, 0x3C, 0x06, 0xC4,
+  0x0B, 0x84, 0x24, 0x08, 0x69, 0x38, 0xBC, 0x15,
+  0x1F, 0xA0, 0x0A, 0xEC, 0x2A, 0x0C, 0x0C, 0x0C,
+  0x2C, 0xA0, 0x15, 0x07, 0x0B, 0x8C, 0xD3, 0x10,
+  0x3B, 0x5C, 0x0C, 0x04, 0x3C, 0xAC, 0x54, 0x1C,
+  0x0B, 0x5B, 0xBB, 0x0A, 0xC1, 0xBB, 0x5C, 0x3C,
+  0xBC, 0x4D, 0x74, 0x10, 0x8C, 0x8C, 0x14, 0x91,
+  0x0C, 0x74, 0x17, 0x0C, 0x48, 0x9C, 0x3C, 0x4C,
+  0x09, 0x7C, 0x05, 0xE4, 0x34, 0x38, 0x6C, 0x11,
+  0x08, 0x7C, 0x18, 0x2C, 0x9C, 0x4C, 0x34, 0x9C,
+  0x29, 0x54, 0x7C, 0x0C, 0x78, 0x18, 0x9C, 0x14,
+  0xBA, 0x30, 0x27, 0x31, 0xC2, 0x97, 0x24, 0x09,
+  0xB4, 0x04, 0x87, 0x0C, 0x14, 0x1F, 0x7C, 0x64,
+  0xB0, 0x0F, 0x45, 0x10, 0x2C, 0xD4, 0x0A, 0x04,
+  0x44, 0x1F, 0x2C, 0xCC, 0x7C, 0xD8, 0x84, 0x0C,
+  0x8C, 0x94, 0xB4, 0x1D, 0x20, 0x5C, 0x18, 0xB4,
+  0x04, 0x09, 0xBC, 0x14, 0xF4, 0x08, 0x54, 0x07,
+  0xFC, 0x6C, 0x24, 0xB4, 0x15, 0x18, 0xDB, 0x17,
+  0x17, 0x18, 0x21, 0x24
+};
+
+unsigned char linux_logo[] __initdata = {
+  0xBC, 0xAC, 0x7D, 0x95, 0xAF, 0x85, 0x2C, 0x2C,
+  0xAC, 0xD9, 0x95, 0x7D, 0x95, 0xAC, 0x2C, 0xAF,
+  0x7D, 0x48, 0xB2, 0xAC, 0x85, 0xDA, 0xDA, 0x2C,
+  0x7D, 0x48, 0x21, 0x2C, 0x8D, 0x2A, 0x8A, 0xDA,
+  0x85, 0x2C, 0xD9, 0xAC, 0x2C, 0x2C, 0xD9, 0xD9,
+  0xAF, 0x85, 0x85, 0x85, 0x8D, 0xBC, 0x2A, 0x2A,
+  0xBC, 0x8C, 0xBC, 0xAC, 0x7D, 0x95, 0xAF, 0x85,
+  0x2C, 0x2C, 0xAC, 0xD9, 0x95, 0x7D, 0x95, 0xAC,
+  0x2C, 0xAF, 0x7D, 0x48, 0xB2, 0xAC, 0x85, 0xDA,
+  0xDA, 0x2C, 0x7D, 0x48, 0x21, 0x2C, 0x8D, 0x2A,
+  0xAF, 0xA1, 0x48, 0x7D, 0xAF, 0x2C, 0x2C, 0xAC,
+  0xD9, 0xD9, 0x95, 0x7D, 0x95, 0xAC, 0xD9, 0x7D,
+  0x48, 0xE9, 0x21, 0xAF, 0xDA, 0xDA, 0x85, 0x2C,
+  0xD9, 0xD9, 0xAC, 0xDA, 0x8A, 0xDA, 0x85, 0x2C,
+  0x2C, 0xAC, 0xD9, 0xAC, 0xAF, 0xAF, 0x2C, 0x2C,
+  0x2C, 0x85, 0x2C, 0x2C, 0x85, 0xDA, 0xDA, 0xDA,
+  0xDA, 0xDA, 0xAF, 0xA1, 0x48, 0x7D, 0xAF, 0x2C,
+  0x2C, 0xAC, 0xD9, 0xD9, 0x95, 0x7D, 0x95, 0xAC,
+  0xD9, 0x7D, 0x48, 0xE9, 0x21, 0xAF, 0xDA, 0xDA,
+  0x85, 0x2C, 0xD9, 0xD9, 0xAC, 0xDA, 0x8A, 0xDA,
+  0x7D, 0x48, 0x48, 0x7D, 0x2C, 0x85, 0x2C, 0xAF,
+  0xD9, 0xD9, 0x7D, 0x95, 0xD9, 0xD9, 0xD9, 0x7D,
+  0xB2, 0x21, 0xD9, 0x85, 0xDA, 0xDA, 0x85, 0x2C,
+  0xAF, 0x2C, 0x2C, 0xDA, 0x85, 0x85, 0x2C, 0x2C,
+  0xAC, 0xD9, 0xD9, 0xAF, 0xDA, 0x85, 0x2C, 0x2C,
+  0x85, 0xDA, 0xDA, 0x85, 0x85, 0xDA, 0x85, 0x85,
+  0x85, 0xAF, 0x7D, 0x48, 0x48, 0x7D, 0x2C, 0x85,
+  0x2C, 0xAF, 0xD9, 0xD9, 0x7D, 0x95, 0xD9, 0xD9,
+  0xD9, 0x7D, 0xB2, 0x21, 0xD9, 0x85, 0xDA, 0xDA,
+  0x85, 0x2C, 0xAF, 0x2C, 0x2C, 0xDA, 0xDA, 0x85,
+  0xA1, 0xE9, 0x48, 0x95, 0x85, 0xDA, 0x85, 0xAF,
+  0xD9, 0xD9, 0x95, 0x95, 0xD9, 0xD9, 0x95, 0x95,
+  0xD9, 0xAC, 0x85, 0x85, 0xDA, 0xDA, 0x85, 0x2C,
+  0xAC, 0xAC, 0x2C, 0x2C, 0x85, 0x2C, 0x2C, 0xAC,
+  0xD9, 0xD9, 0x2C, 0x91, 0x41, 0x20, 0x6B, 0x20,
+  0x6B, 0x20, 0x6B, 0xAE, 0x2C, 0x85, 0x2C, 0x2C,
+  0xAC, 0xD9, 0xA1, 0xE9, 0x48, 0x95, 0x85, 0xDA,
+  0x85, 0xAF, 0xD9, 0xD9, 0x95, 0x95, 0xD9, 0xD9,
+  0x95, 0x95, 0xD9, 0xAC, 0x85, 0x85, 0xDA, 0xDA,
+  0x85, 0x2C, 0xAC, 0xAC, 0x2C, 0x2C, 0x2C, 0x2C,
+  0xA1, 0xA1, 0xD6, 0xAF, 0xDA, 0xDA, 0x85, 0x2C,
+  0xD9, 0xD9, 0x95, 0x95, 0xD9, 0xD9, 0xD9, 0xD9,
+  0x2C, 0x2C, 0xDA, 0xDA, 0xDA, 0x85, 0x2C, 0xD9,
+  0xD9, 0xD9, 0xD9, 0xAC, 0xAC, 0xAC, 0xAF, 0xAC,
+  0x2C, 0xB2, 0x88, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x6B, 0x80, 0x85, 0x2C,
+  0xD9, 0xD6, 0xA1, 0xA1, 0xD6, 0xAF, 0xDA, 0xDA,
+  0x85, 0x2C, 0xD9, 0xD9, 0x95, 0x95, 0xD9, 0xD9,
+  0xD9, 0xD9, 0x2C, 0x2C, 0xDA, 0xDA, 0xDA, 0x85,
+  0x2C, 0xD9, 0xD9, 0xD9, 0xD9, 0xAF, 0xAF, 0xAF,
+  0xD6, 0xD6, 0xD9, 0x2C, 0xDA, 0xDA, 0x2C, 0xAC,
+  0xD9, 0x7D, 0x95, 0xD9, 0xD9, 0xD9, 0xAF, 0x2C,
+  0x85, 0x85, 0x85, 0x85, 0x2C, 0x2C, 0xAC, 0xD9,
+  0xD9, 0xD9, 0xAF, 0xAF, 0x2C, 0x2C, 0xAF, 0xDA,
+  0xAE, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x41, 0xE3, 0x20, 0x6B, 0x48,
+  0xAC, 0x95, 0xD6, 0xD6, 0xD9, 0x2C, 0xDA, 0xDA,
+  0x2C, 0xAC, 0xD9, 0x7D, 0x95, 0xD9, 0xD9, 0xD9,
+  0xAF, 0x2C, 0x85, 0x85, 0x85, 0x85, 0x2C, 0x2C,
+  0xAC, 0xD9, 0xD9, 0xD9, 0xAF, 0xAF, 0xAF, 0xAF,
+  0xD9, 0xD9, 0xD9, 0x2C, 0x85, 0x85, 0x2C, 0xD9,
+  0x7D, 0x21, 0xD6, 0xD9, 0xAF, 0x2C, 0x85, 0x85,
+  0x85, 0x85, 0x85, 0x85, 0x2C, 0xAF, 0xAF, 0xAC,
+  0xAF, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0x89,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x74, 0x43, 0x80, 0x41, 0x20,
+  0x9F, 0x2C, 0xD9, 0xD9, 0xD9, 0x2C, 0x85, 0x85,
+  0x2C, 0xD9, 0x7D, 0x21, 0xD6, 0xD9, 0xAF, 0x2C,
+  0x85, 0x85, 0x85, 0x85, 0x85, 0x85, 0x2C, 0xAF,
+  0xAF, 0xAC, 0xAF, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C,
+  0xD9, 0x7D, 0xD9, 0xAF, 0x85, 0x85, 0x2C, 0xD9,
+  0xB2, 0x21, 0x7D, 0xD9, 0xAF, 0x2C, 0x85, 0x85,
+  0x85, 0x2C, 0x2C, 0x2C, 0x2C, 0xAF, 0xAF, 0xAC,
+  0xAF, 0xAC, 0xAF, 0xAF, 0xAC, 0xAC, 0x85, 0x41,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0xAE, 0x48, 0x89, 0x74, 0x41,
+  0x6B, 0xD6, 0xD9, 0x7D, 0xD9, 0xAF, 0x85, 0x85,
+  0x2C, 0xD9, 0xB2, 0x21, 0x7D, 0xD9, 0xAF, 0x2C,
+  0x85, 0x85, 0x85, 0x2C, 0x2C, 0x2C, 0x2C, 0xAF,
+  0xAF, 0xAC, 0xAF, 0xAC, 0xAC, 0x2C, 0xAF, 0xAC,
+  0x2C, 0x7D, 0xD9, 0x2C, 0xDA, 0x85, 0x2C, 0x7D,
+  0xB2, 0xD6, 0xD9, 0xAF, 0x85, 0x85, 0x85, 0x85,
+  0xAF, 0xAC, 0xAC, 0xAF, 0xAF, 0xAC, 0xAC, 0xD9,
+  0x95, 0x7D, 0x95, 0x95, 0xD9, 0xD9, 0x48, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x6B, 0xAE, 0xE6, 0x80, 0x2B, 0x88,
+  0x20, 0x33, 0xDA, 0x95, 0xD9, 0x2C, 0xDA, 0x85,
+  0x2C, 0x7D, 0xB2, 0xD6, 0xD9, 0xAF, 0x85, 0x85,
+  0x85, 0x85, 0xAF, 0xAC, 0xAC, 0xAF, 0xAF, 0xAC,
+  0xAC, 0xD9, 0x95, 0x95, 0x7D, 0x95, 0x95, 0xD9,
+  0x85, 0xD9, 0x2C, 0x85, 0xDA, 0xDA, 0xD9, 0x21,
+  0xA1, 0xD9, 0xAF, 0x2C, 0x85, 0xDA, 0x85, 0xAF,
+  0xD9, 0xD9, 0xAC, 0xAC, 0xAC, 0xD9, 0x7D, 0xD6,
+  0xD6, 0x7D, 0x95, 0xD9, 0xD9, 0x85, 0xDB, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0xDB, 0xE3, 0x6B, 0x20, 0x20,
+  0x20, 0x20, 0xE9, 0xD9, 0x2C, 0x85, 0xDA, 0xDA,
+  0xD9, 0x21, 0xA1, 0xD9, 0xAF, 0x2C, 0x85, 0xDA,
+  0x85, 0xAF, 0xD9, 0xD9, 0xAC, 0xAC, 0xAC, 0xD9,
+  0x7D, 0xD6, 0xD6, 0x7D, 0x95, 0xD9, 0xD9, 0xD9,
+  0xDA, 0x2C, 0x85, 0xDA, 0xDA, 0x85, 0x95, 0x21,
+  0x21, 0xD9, 0x85, 0x85, 0x85, 0x2C, 0x2C, 0xD9,
+  0x95, 0x95, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9,
+  0xAC, 0xAC, 0x2C, 0xAF, 0x2C, 0x85, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x88, 0xDA, 0x85, 0xDA, 0xDA, 0x85,
+  0x95, 0x21, 0x21, 0xD9, 0x85, 0x85, 0x85, 0x2C,
+  0x2C, 0xD9, 0x95, 0x95, 0xD9, 0xD9, 0xD9, 0xD9,
+  0xD9, 0xD9, 0xD9, 0xAF, 0x2C, 0x2C, 0x2C, 0x2C,
+  0xDA, 0x2C, 0x85, 0x85, 0x2C, 0xD9, 0xD6, 0xB2,
+  0x95, 0x2C, 0x85, 0x85, 0xAF, 0xAC, 0x95, 0x95,
+  0x7D, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0x2C, 0x85,
+  0x85, 0x85, 0x85, 0x85, 0x85, 0xAC, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0xAC, 0x85, 0x85, 0x2C, 0xD9,
+  0xD6, 0xB2, 0x95, 0x2C, 0x85, 0x85, 0xAF, 0xAC,
+  0x95, 0x95, 0x7D, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9,
+  0x2C, 0x85, 0x85, 0x85, 0x85, 0x85, 0x85, 0x85,
+  0x85, 0x2C, 0x2C, 0x2C, 0xAC, 0x95, 0xD6, 0x7D,
+  0xD9, 0x2C, 0x2C, 0xAF, 0x95, 0x7D, 0x7D, 0x95,
+  0x95, 0xD9, 0xD9, 0x95, 0xD9, 0xD9, 0x2C, 0x85,
+  0xDA, 0xDA, 0xDA, 0x85, 0x85, 0x21, 0x20, 0x20,
+  0x6B, 0x41, 0xDB, 0x6B, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x41, 0xDB, 0xDB, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0xE6, 0x2C, 0x2C, 0xAC, 0x95,
+  0xD6, 0x7D, 0xD9, 0x2C, 0x2C, 0xAF, 0x95, 0x7D,
+  0x7D, 0x95, 0x95, 0xD9, 0xD9, 0x95, 0xD9, 0xD9,
+  0x2C, 0x85, 0xDA, 0xDA, 0xDA, 0x85, 0x2C, 0x2C,
+  0x2C, 0xAF, 0xAC, 0xD9, 0x95, 0xD6, 0xD6, 0xD9,
+  0x2C, 0x2C, 0x2C, 0xD9, 0xD6, 0xD6, 0xD9, 0xAF,
+  0xAC, 0x95, 0xD6, 0x7D, 0x7D, 0xD9, 0x2C, 0x85,
+  0xDA, 0xDA, 0x2C, 0xAF, 0xAF, 0x21, 0x20, 0x20,
+  0x88, 0x2B, 0x88, 0x74, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0xAE, 0x2D, 0x2D, 0x74, 0x74, 0x88, 0x20,
+  0x20, 0x20, 0x20, 0x80, 0xAC, 0xD9, 0x95, 0xD6,
+  0xD6, 0xD9, 0x2C, 0x2C, 0x2C, 0xD9, 0xD6, 0xD6,
+  0xD9, 0xAF, 0xAC, 0x95, 0xD6, 0x7D, 0x7D, 0xD9,
+  0x2C, 0xDA, 0xDA, 0x85, 0x2C, 0xAF, 0xAF, 0xAF,
+  0x2C, 0xAF, 0xD9, 0x95, 0xD6, 0xD6, 0x95, 0xAF,
+  0x2C, 0x2C, 0xD9, 0x95, 0xD6, 0x95, 0xAF, 0x2C,
+  0xAC, 0x7D, 0x21, 0x95, 0xD9, 0x2C, 0x85, 0x85,
+  0x85, 0xAF, 0xD9, 0x95, 0xD9, 0x7D, 0x20, 0x33,
+  0x7D, 0x8A, 0x7D, 0x5B, 0x6B, 0x20, 0x20, 0x6B,
+  0xE6, 0xD9, 0x85, 0x2A, 0xDA, 0x2B, 0x41, 0x20,
+  0x20, 0x20, 0x6B, 0x74, 0xD9, 0x95, 0xD6, 0xD6,
+  0x95, 0xAF, 0x2C, 0x2C, 0xD9, 0x95, 0xD6, 0x95,
+  0xAF, 0x2C, 0xAC, 0x7D, 0x21, 0x95, 0xD9, 0x2C,
+  0x85, 0x85, 0x85, 0x2C, 0xD9, 0xD9, 0xD9, 0xD9,
+  0x85, 0xD9, 0x7D, 0x21, 0x21, 0x7D, 0xAC, 0x2C,
+  0x2C, 0xAC, 0xD9, 0x7D, 0xD9, 0xAF, 0x2C, 0x85,
+  0xAC, 0x7D, 0x7D, 0xAC, 0x85, 0xDA, 0x8A, 0xDA,
+  0x85, 0xAF, 0xD9, 0x7D, 0xD9, 0x95, 0x20, 0x91,
+  0xBC, 0x73, 0xEE, 0x7D, 0x20, 0x20, 0x20, 0x80,
+  0x4D, 0x3D, 0x73, 0x73, 0xA3, 0xD6, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x2B, 0x7D, 0x21, 0x21, 0x7D,
+  0xAC, 0x2C, 0x2C, 0xAC, 0xD9, 0x7D, 0xD9, 0xAF,
+  0x2C, 0x85, 0xAC, 0x7D, 0x7D, 0xAC, 0x85, 0xDA,
+  0x8A, 0x8A, 0x85, 0xAC, 0xD9, 0x7D, 0xD9, 0xAC,
+  0x2C, 0xD9, 0xD6, 0xB2, 0xB2, 0x7D, 0xAF, 0x85,
+  0x2C, 0xD9, 0x95, 0x95, 0xAF, 0x2C, 0x2C, 0x2C,
+  0xD9, 0xD9, 0xAC, 0x85, 0x8D, 0x2A, 0x2A, 0xDA,
+  0xAF, 0xD9, 0x95, 0x95, 0xD9, 0xAC, 0x20, 0xAF,
+  0x2C, 0xE6, 0x8D, 0x73, 0xE3, 0x20, 0x20, 0x48,
+  0x5C, 0xDA, 0x5B, 0x43, 0xBC, 0x73, 0x2B, 0x20,
+  0x20, 0x20, 0x20, 0x41, 0xD6, 0xB2, 0xB2, 0x7D,
+  0xAF, 0x85, 0x2C, 0xD9, 0x95, 0x95, 0xAF, 0x2C,
+  0x2C, 0x2C, 0xD9, 0xD9, 0xAC, 0x85, 0x8A, 0x2A,
+  0x8D, 0xDA, 0xAF, 0xD9, 0x95, 0x95, 0xD9, 0xAF,
+  0xAC, 0xD9, 0xD6, 0xB2, 0x21, 0xD9, 0x2C, 0x85,
+  0x2C, 0xD9, 0x95, 0xD9, 0xAF, 0x2C, 0x2C, 0xAC,
+  0xAC, 0xAF, 0x85, 0x8D, 0xBC, 0xBC, 0xDA, 0xD9,
+  0xD6, 0xA1, 0xA1, 0x21, 0xD9, 0xAC, 0x20, 0x2A,
+  0xCC, 0xAE, 0x9F, 0xE4, 0xAE, 0x5B, 0x74, 0xA1,
+  0xE4, 0xAE, 0x20, 0x9F, 0x89, 0xE8, 0xE6, 0x20,
+  0x20, 0x20, 0x20, 0x41, 0xD6, 0xB2, 0x21, 0xD9,
+  0x2C, 0x85, 0x2C, 0xD9, 0x95, 0xD9, 0xAF, 0x2C,
+  0x2C, 0xAC, 0xAC, 0xAF, 0x85, 0x8D, 0xBC, 0x2A,
+  0xDA, 0xD9, 0xD6, 0xA1, 0xA1, 0x21, 0xD9, 0xD9,
+  0xD9, 0x95, 0x21, 0xA1, 0x21, 0xAC, 0x85, 0x85,
+  0xAC, 0xD9, 0xD9, 0xAF, 0x2C, 0x2C, 0xAF, 0xAC,
+  0xAF, 0x85, 0x8A, 0x2A, 0x2A, 0xDA, 0xD9, 0xA1,
+  0x48, 0xE9, 0x48, 0x21, 0x95, 0xAC, 0x20, 0x2A,
+  0xDB, 0x41, 0x74, 0xBC, 0x2B, 0x7B, 0x7B, 0x80,
+  0x73, 0x41, 0x20, 0x6B, 0x2B, 0xE8, 0x2D, 0x20,
+  0x20, 0x20, 0x20, 0x33, 0x21, 0xA1, 0x21, 0xAC,
+  0x85, 0x85, 0xAC, 0xD9, 0xD9, 0xAF, 0x2C, 0x2C,
+  0xAF, 0xAC, 0xAF, 0x85, 0x8A, 0xBC, 0x2A, 0xDA,
+  0xD9, 0xA1, 0x48, 0xE9, 0x48, 0x21, 0xD9, 0xD9,
+  0xA1, 0xB2, 0xB2, 0x48, 0xD6, 0xAC, 0x2C, 0x2C,
+  0xD9, 0x95, 0xAF, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C,
+  0x85, 0x8A, 0x8D, 0x8D, 0x85, 0x95, 0xA1, 0x6C,
+  0x6C, 0x48, 0xD6, 0xD9, 0x2C, 0x85, 0x20, 0x2C,
+  0x89, 0x20, 0x3C, 0xB9, 0xA7, 0x63, 0xD2, 0xB9,
+  0xC6, 0x9A, 0x20, 0x20, 0x43, 0x5C, 0xE6, 0x20,
+  0x20, 0x20, 0x20, 0x33, 0xB2, 0x48, 0xD6, 0xAC,
+  0x2C, 0x2C, 0xD9, 0x95, 0xAF, 0x2C, 0x2C, 0x2C,
+  0x2C, 0x2C, 0x85, 0x8A, 0x8D, 0x8D, 0x85, 0x95,
+  0xA1, 0x6C, 0x6C, 0x48, 0xD6, 0xD9, 0xAF, 0xAC,
+  0xA1, 0xD6, 0x7D, 0xB2, 0xD6, 0xAF, 0x85, 0x85,
+  0xD9, 0x95, 0x2C, 0x85, 0xDA, 0x85, 0x85, 0x2C,
+  0x85, 0x8A, 0x8D, 0xDA, 0xD9, 0x48, 0x81, 0x2D,
+  0x48, 0xD6, 0xD9, 0xAC, 0x2C, 0x85, 0x20, 0x2D,
+  0xEE, 0x93, 0xD1, 0xA7, 0x3E, 0x3E, 0x3A, 0x25,
+  0x56, 0xAB, 0xAA, 0xC5, 0xEE, 0xEE, 0x33, 0x20,
+  0x20, 0x20, 0x20, 0x41, 0xD9, 0xB2, 0xD6, 0xAF,
+  0x85, 0x85, 0xD9, 0x95, 0x2C, 0x85, 0xDA, 0x85,
+  0x85, 0x2C, 0x85, 0x8A, 0x8D, 0xDA, 0xD9, 0x48,
+  0x81, 0x2D, 0x48, 0xD6, 0xD9, 0xAF, 0x2C, 0x2C,
+  0xAC, 0xAF, 0xD9, 0x7D, 0xD6, 0x2C, 0x85, 0x2C,
+  0xD9, 0xD9, 0x2C, 0xDA, 0xDA, 0xDA, 0x2C, 0x2C,
+  0x85, 0x8D, 0x8D, 0x2C, 0x21, 0x2D, 0x2D, 0xE9,
+  0xD6, 0xD9, 0xAF, 0x2C, 0x85, 0xDA, 0x20, 0xE3,
+  0xB4, 0xBE, 0xF1, 0x3E, 0x9B, 0x22, 0x56, 0xF2,
+  0xBB, 0x7F, 0x56, 0xDC, 0x8F, 0x5A, 0x5F, 0x20,
+  0x20, 0x20, 0x20, 0x6B, 0x2C, 0x7D, 0xD6, 0x2C,
+  0x85, 0x2C, 0xD9, 0xD9, 0x2C, 0xDA, 0xDA, 0xDA,
+  0x2C, 0x2C, 0x85, 0x8D, 0x8A, 0x85, 0x21, 0x2D,
+  0x2D, 0xE9, 0xD6, 0xD9, 0xAF, 0x2C, 0x85, 0x85,
+  0x2A, 0x85, 0xAC, 0x95, 0x95, 0x2C, 0x85, 0x85,
+  0xAC, 0xAF, 0x85, 0xDA, 0xDA, 0x85, 0x2C, 0x2C,
+  0xDA, 0x8A, 0x8A, 0xAF, 0xA1, 0x2D, 0xE9, 0xD6,
+  0xD9, 0xAC, 0x85, 0x85, 0x85, 0xDA, 0x20, 0x52,
+  0x55, 0xED, 0x57, 0x3E, 0x22, 0x56, 0x37, 0xBB,
+  0xBB, 0x58, 0x7F, 0x7F, 0x56, 0x5E, 0xC5, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x2C, 0x95, 0x95, 0x2C,
+  0x85, 0x85, 0xAC, 0xAF, 0x85, 0xDA, 0xDA, 0x85,
+  0x2C, 0x2C, 0xDA, 0x8D, 0xDA, 0xAF, 0xA1, 0x2D,
+  0xE9, 0xD6, 0xD9, 0xAF, 0x2C, 0x85, 0x85, 0x85,
+  0xCD, 0xAF, 0xD9, 0x95, 0xD9, 0x2C, 0xDA, 0x85,
+  0xAF, 0xD9, 0x85, 0xDA, 0x85, 0x2C, 0xAC, 0xAF,
+  0x85, 0x8A, 0x85, 0xD9, 0x48, 0x48, 0xB2, 0x95,
+  0x95, 0xAC, 0x2C, 0x85, 0xDA, 0xDA, 0x6B, 0xB3,
+  0x46, 0x7C, 0x2E, 0x9B, 0x22, 0x56, 0xBB, 0x37,
+  0x58, 0x58, 0xF2, 0x3A, 0x46, 0x63, 0x64, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x2D, 0x95, 0xD9, 0x2C,
+  0xDA, 0x85, 0xAF, 0xD9, 0x85, 0xDA, 0x85, 0x2C,
+  0xAC, 0xAF, 0x85, 0xDA, 0x85, 0xD9, 0x48, 0x48,
+  0xB2, 0x95, 0x95, 0xD9, 0x85, 0xDA, 0x85, 0x85,
+  0xBC, 0xB2, 0xB2, 0x7D, 0xD9, 0x2C, 0xDA, 0x85,
+  0xAF, 0xD9, 0x85, 0xDA, 0x85, 0x85, 0xAF, 0x2C,
+  0x85, 0xDA, 0x2C, 0x7D, 0xA1, 0x48, 0xB2, 0x21,
+  0xD6, 0xD9, 0x85, 0xDA, 0x85, 0xDA, 0x41, 0x51,
+  0xB7, 0xEC, 0x2E, 0x22, 0x56, 0x37, 0xBB, 0xF2,
+  0x37, 0xEA, 0x2F, 0x2F, 0x77, 0xA7, 0x38, 0x20,
+  0x20, 0x6B, 0x20, 0x20, 0x5B, 0x2C, 0xD9, 0x2C,
+  0xDA, 0x85, 0xAF, 0xD9, 0x85, 0xDA, 0x85, 0x85,
+  0xAF, 0x2C, 0xDA, 0xDA, 0x2C, 0x7D, 0xA1, 0x48,
+  0xB2, 0x21, 0xD6, 0xD9, 0x2C, 0xDA, 0x85, 0xAF,
+  0x2C, 0x2D, 0x48, 0x7D, 0xAF, 0x2C, 0x85, 0x2C,
+  0xD9, 0xAC, 0xAF, 0x85, 0x85, 0x2C, 0x2C, 0x2C,
+  0x85, 0x2C, 0xD9, 0xD6, 0xA1, 0xA1, 0x48, 0xA1,
+  0x21, 0x2C, 0xDA, 0xDA, 0x2C, 0x85, 0x41, 0x98,
+  0xA2, 0xA7, 0x6F, 0xC9, 0x37, 0xF2, 0xF2, 0x9B,
+  0xB7, 0x66, 0x60, 0x4C, 0xED, 0x84, 0x3C, 0x20,
+  0x5B, 0x2D, 0x2B, 0x6B, 0x20, 0xAF, 0xAF, 0x2C,
+  0x85, 0x2C, 0xD9, 0xAC, 0xAF, 0x85, 0x85, 0x2C,
+  0x2C, 0x2C, 0x2C, 0x85, 0xD9, 0xD6, 0xA1, 0xA1,
+  0x48, 0xA1, 0xD6, 0xAF, 0xDA, 0x8A, 0x2C, 0xD9,
+  0xB2, 0x2D, 0x48, 0x95, 0x2C, 0x2C, 0x2C, 0x85,
+  0xAC, 0xAC, 0xAF, 0x85, 0xDA, 0x85, 0xAF, 0xAC,
+  0xAF, 0x2C, 0xD9, 0xD6, 0xD6, 0xD6, 0x21, 0xD6,
+  0xD9, 0xDA, 0x8D, 0xDA, 0xAF, 0x2C, 0x20, 0x88,
+  0x42, 0x51, 0x3F, 0x2F, 0x45, 0xB7, 0x66, 0x55,
+  0x46, 0x60, 0x5D, 0x36, 0xD8, 0x71, 0x43, 0x20,
+  0x20, 0x2D, 0xB2, 0x80, 0x20, 0x2D, 0x2C, 0x2C,
+  0x2C, 0x85, 0xAC, 0xAC, 0xAF, 0x85, 0xDA, 0x85,
+  0xAF, 0xAC, 0xAC, 0xAF, 0xD9, 0xD6, 0xD6, 0xD6,
+  0x21, 0xD6, 0xD9, 0xDA, 0x8D, 0x8A, 0x2C, 0xD9,
+  0xB2, 0x48, 0xD6, 0xAC, 0xAF, 0x2C, 0x2C, 0x85,
+  0x2C, 0xAC, 0x2C, 0xDA, 0xDA, 0x85, 0xAF, 0xD9,
+  0xD9, 0xAC, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xAC,
+  0x85, 0x8D, 0xBC, 0xDA, 0xD9, 0xDA, 0x20, 0xE3,
+  0xDA, 0x69, 0x96, 0xB5, 0xF1, 0x68, 0x5D, 0x82,
+  0xE1, 0xBE, 0x27, 0x8D, 0x4D, 0xD3, 0x7D, 0x20,
+  0x20, 0xDB, 0xA1, 0xCA, 0x20, 0x88, 0x85, 0x2C,
+  0x2C, 0x85, 0x2C, 0xAC, 0x2C, 0xDA, 0xDA, 0x85,
+  0xAF, 0xD9, 0xAC, 0xAF, 0xD9, 0xD9, 0xD9, 0xD9,
+  0xD9, 0xAC, 0xDA, 0x8D, 0xBC, 0xDA, 0xD9, 0x95,
+  0xD9, 0x95, 0xAC, 0x2C, 0x2C, 0x2C, 0x2C, 0x85,
+  0x85, 0xAF, 0xAF, 0x85, 0x85, 0x2C, 0x2C, 0xAC,
+  0xD9, 0xAC, 0xAF, 0x2C, 0x2C, 0x2C, 0x2C, 0x85,
+  0x8D, 0x2A, 0x2A, 0x85, 0xD9, 0x95, 0x20, 0xDB,
+  0x8D, 0x8D, 0x99, 0xB0, 0x35, 0xE5, 0x3F, 0x35,
+  0xB9, 0x50, 0x8A, 0x4D, 0x73, 0xE8, 0xA3, 0xCC,
+  0x20, 0x20, 0x33, 0x6B, 0x20, 0x20, 0xCC, 0x85,
+  0x2C, 0x85, 0x85, 0xAF, 0xAF, 0x85, 0x85, 0x85,
+  0x2C, 0xD9, 0xD9, 0xAC, 0xAF, 0x2C, 0x2C, 0x2C,
+  0x2C, 0x85, 0x8A, 0x2A, 0x8D, 0x2C, 0xD9, 0xD9,
+  0xAF, 0xAF, 0xAC, 0xAF, 0x2C, 0x2C, 0x2C, 0x85,
+  0x2C, 0xAF, 0xAF, 0xAF, 0x2C, 0x2C, 0x2C, 0xAC,
+  0xD9, 0xAC, 0xAF, 0x2C, 0x85, 0x85, 0xDA, 0xDA,
+  0x8A, 0x8A, 0x85, 0xD9, 0x2C, 0x2B, 0x20, 0xAE,
+  0xA3, 0xBC, 0x8D, 0xC8, 0xA9, 0xC7, 0x92, 0x47,
+  0x8D, 0x8D, 0x7E, 0xE4, 0xE8, 0xE8, 0x5C, 0x2C,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x6B, 0xAF,
+  0x2C, 0x85, 0x2C, 0xAF, 0xAF, 0xAF, 0x2C, 0x2C,
+  0x2C, 0xAF, 0xD9, 0xAC, 0x2C, 0x2C, 0x85, 0x85,
+  0x85, 0xDA, 0x8D, 0x8A, 0x85, 0xAC, 0x95, 0xD9,
+  0xAC, 0xAC, 0xAC, 0xAC, 0x2C, 0xAF, 0xAF, 0x2C,
+  0x2C, 0xAF, 0xAF, 0xAC, 0x2C, 0xAF, 0x2C, 0xAF,
+  0xD9, 0xAC, 0x2C, 0x2C, 0x85, 0x85, 0x85, 0x85,
+  0x85, 0x2C, 0xD9, 0xD9, 0x2D, 0x6B, 0x41, 0x2A,
+  0xE8, 0xA3, 0xC8, 0x8D, 0x8A, 0x8A, 0x8A, 0x8D,
+  0x4D, 0xA3, 0x3D, 0xE8, 0xE8, 0xE8, 0xE8, 0x5C,
+  0xAE, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0xDB,
+  0xDA, 0x2C, 0x2C, 0xAF, 0xAF, 0xAC, 0xAC, 0xAF,
+  0x2C, 0xAC, 0xD9, 0xAC, 0x2C, 0x2C, 0x85, 0x85,
+  0x85, 0x85, 0x85, 0x2C, 0xD9, 0x95, 0x7D, 0xD9,
+  0x7D, 0x7D, 0xD9, 0xAC, 0xAC, 0xAF, 0xAF, 0xAF,
+  0x2C, 0x2C, 0xAC, 0xAC, 0xD9, 0xAC, 0xAC, 0xD9,
+  0x95, 0xD9, 0xAC, 0xAF, 0xAF, 0xAC, 0xAF, 0xAC,
+  0xD9, 0x7D, 0x7D, 0x7D, 0x33, 0x41, 0x2D, 0xE8,
+  0xE8, 0x5C, 0xD3, 0x8D, 0x8D, 0x8D, 0x8D, 0x7E,
+  0x3D, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8,
+  0xDA, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x81, 0x2C, 0x2C, 0x2C, 0xAC, 0xAC, 0xAC, 0xAC,
+  0xAC, 0xD9, 0x95, 0x95, 0xAC, 0xAF, 0xAF, 0xAF,
+  0xAF, 0xAC, 0xD9, 0x95, 0x7D, 0xD6, 0xD6, 0x7D,
+  0x21, 0xD6, 0x95, 0xD9, 0xD9, 0xAC, 0xAF, 0xAF,
+  0x2C, 0xAF, 0xAC, 0xAC, 0xD9, 0xD9, 0xD9, 0xD9,
+  0x21, 0x21, 0x7D, 0x95, 0x95, 0x7D, 0xD6, 0x21,
+  0xB2, 0xA1, 0x2C, 0x88, 0x20, 0xE3, 0xA3, 0xE8,
+  0xE8, 0xE8, 0xE4, 0xEE, 0xD3, 0x7E, 0x73, 0x5C,
+  0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8,
+  0x5C, 0x2B, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x2C, 0xAF, 0xAF, 0xAC, 0xD9, 0xD9, 0xD9,
+  0xD9, 0xD9, 0xD6, 0x21, 0x7D, 0x95, 0x95, 0x7D,
+  0xD6, 0xB2, 0xA1, 0xA1, 0xB2, 0xD6, 0x21, 0x21,
+  0x21, 0xD9, 0xD9, 0xD9, 0xAC, 0xAF, 0xAC, 0xAF,
+  0x2C, 0x2C, 0xAC, 0xD9, 0xD9, 0xD9, 0xD9, 0x95,
+  0x7D, 0xB2, 0xD6, 0x95, 0xD9, 0x95, 0xD6, 0xA1,
+  0xA1, 0xAF, 0x5B, 0x20, 0x20, 0xD6, 0xE8, 0xE8,
+  0xE8, 0xE8, 0xE8, 0xE8, 0x5C, 0xE8, 0xE8, 0xE8,
+  0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8,
+  0xE8, 0x48, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0xE3, 0x8A, 0x2C, 0xAC, 0xAC, 0xD9, 0xD9,
+  0xD9, 0x95, 0xD6, 0xB2, 0xD6, 0x95, 0xD9, 0x95,
+  0x21, 0xB2, 0xA1, 0xB2, 0xD6, 0xD6, 0xD6, 0xA1,
+  0xD9, 0x2C, 0x2C, 0x2C, 0xAF, 0xAF, 0xAC, 0xAF,
+  0x2C, 0x2C, 0xAF, 0xAC, 0xD9, 0xAC, 0xD9, 0xD9,
+  0xD9, 0x95, 0xAC, 0x2C, 0x2C, 0xAC, 0x95, 0x7D,
+  0xD9, 0x91, 0x20, 0x20, 0xE3, 0xA3, 0xE8, 0xE8,
+  0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8,
+  0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8,
+  0xE8, 0x85, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x2B, 0x8A, 0xAF, 0xAC, 0xD9, 0xAC,
+  0xD9, 0xD9, 0xD9, 0x95, 0xAC, 0x2C, 0x2C, 0xAC,
+  0x95, 0x7D, 0x95, 0x95, 0xD9, 0x95, 0x7D, 0x21,
+  0x2C, 0xDA, 0xDA, 0x85, 0x2C, 0xAF, 0xAF, 0xAF,
+  0xAF, 0xAF, 0x2C, 0xAF, 0xAF, 0xAC, 0xAC, 0xAC,
+  0xD9, 0xAF, 0x85, 0x85, 0x2C, 0xAF, 0xD9, 0xAF,
+  0x48, 0x20, 0x20, 0x20, 0xE6, 0xA3, 0xE8, 0xE8,
+  0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8,
+  0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0x5C,
+  0xE4, 0x73, 0x41, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x2B, 0xDA, 0xAF, 0xAF, 0xAC,
+  0xAC, 0xAF, 0xD9, 0x2C, 0x85, 0x85, 0x2C, 0xAF,
+  0xD9, 0xD9, 0xAC, 0xAF, 0xAC, 0xD9, 0xD9, 0xD9,
+  0x85, 0xDA, 0xDA, 0x85, 0x2C, 0x2C, 0xAC, 0xAF,
+  0xAF, 0xAF, 0xAF, 0x2C, 0xAF, 0xAF, 0xAC, 0xAC,
+  0xAF, 0x2C, 0x2C, 0x2C, 0xAC, 0x95, 0x95, 0xA1,
+  0x20, 0x20, 0x20, 0x20, 0xE9, 0x8C, 0x5C, 0xE8,
+  0xE8, 0xE8, 0xE8, 0x3D, 0x73, 0x73, 0xE8, 0xE8,
+  0xE8, 0xE8, 0xE8, 0xE4, 0x73, 0x73, 0x73, 0xCD,
+  0x7E, 0xA3, 0x74, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x24, 0x85, 0xAF, 0xAF,
+  0xAC, 0xAC, 0xAC, 0xAF, 0x85, 0x2C, 0xAC, 0x95,
+  0x95, 0xD9, 0xAC, 0xAC, 0xAC, 0xD9, 0xAC, 0xAF,
+  0x8A, 0x8A, 0xDA, 0xDA, 0x85, 0x2C, 0x2C, 0x2C,
+  0x2C, 0x2C, 0x2C, 0xAF, 0xAF, 0xAC, 0xAF, 0xAC,
+  0xAC, 0xAF, 0xAF, 0xD9, 0xD6, 0xD6, 0x2C, 0x88,
+  0x20, 0x20, 0x20, 0x88, 0xB2, 0xDA, 0x7E, 0x73,
+  0xE8, 0xE8, 0xE8, 0x3D, 0x73, 0xE8, 0xE8, 0xE8,
+  0xE8, 0xE8, 0xE8, 0xA3, 0xCD, 0xD3, 0x2A, 0x2A,
+  0x2A, 0x8C, 0x8D, 0x88, 0x20, 0xE3, 0x6B, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x41, 0x85, 0xAF, 0xAC,
+  0xAC, 0xAC, 0xAC, 0xAF, 0xAC, 0xD9, 0x7D, 0xD6,
+  0x7D, 0x7D, 0xD9, 0x95, 0xD9, 0xAC, 0xAC, 0xAF,
+  0xD3, 0x8D, 0xDA, 0xDA, 0x85, 0x85, 0x2C, 0x2C,
+  0x2C, 0xAF, 0xAF, 0xAC, 0xD9, 0xD9, 0xD9, 0xD9,
+  0xAF, 0xAF, 0xAC, 0xD9, 0x95, 0x7D, 0xAC, 0x20,
+  0x20, 0x20, 0x20, 0xDB, 0x2C, 0xA3, 0x5C, 0xE8,
+  0xE8, 0xE8, 0xE8, 0x5C, 0x3D, 0x3D, 0xE8, 0xE8,
+  0xE8, 0xE4, 0xE8, 0xE8, 0xE8, 0xE4, 0x73, 0xEE,
+  0xD3, 0x2A, 0xEE, 0xAC, 0x20, 0x33, 0x2B, 0xE3,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x9F, 0xAF, 0xD9,
+  0xD9, 0xAC, 0xAF, 0xAF, 0xAC, 0xD9, 0x95, 0x7D,
+  0xD9, 0x95, 0x95, 0x95, 0x95, 0xD9, 0xAF, 0xAF,
+  0x7E, 0x85, 0x85, 0x2C, 0x85, 0x85, 0x85, 0x2C,
+  0x2C, 0x2C, 0xAF, 0xD9, 0xD9, 0x95, 0xD9, 0xAC,
+  0xAC, 0xAF, 0xAF, 0xAC, 0xAC, 0xAC, 0x91, 0x20,
+  0x33, 0xE3, 0x41, 0x48, 0x73, 0x5C, 0xE8, 0xE8,
+  0xE8, 0xE8, 0xE8, 0xA3, 0xD6, 0x6C, 0x85, 0xE8,
+  0xDA, 0xAE, 0xB2, 0xA3, 0x5C, 0xE8, 0xE8, 0xE8,
+  0x3D, 0xEE, 0x4D, 0xA3, 0x24, 0x20, 0x6B, 0xDB,
+  0x2B, 0x20, 0x20, 0x20, 0x20, 0x20, 0x85, 0x95,
+  0xD9, 0xD9, 0xAC, 0xAF, 0xAF, 0xAC, 0xD9, 0xAC,
+  0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xAC, 0xD9, 0xAC,
+  0x8A, 0xD9, 0xAC, 0xD9, 0xAC, 0xAC, 0x2C, 0x2C,
+  0xAF, 0xAF, 0xAF, 0xAC, 0xD9, 0xD9, 0xD9, 0xD9,
+  0xAF, 0xAF, 0xAF, 0xAC, 0xAC, 0x85, 0x33, 0x20,
+  0xCC, 0x20, 0xE3, 0xA3, 0xE8, 0xE8, 0xE8, 0xE8,
+  0xE8, 0xA3, 0xD9, 0x81, 0xAC, 0xDA, 0x2D, 0x5C,
+  0x48, 0x41, 0x88, 0x74, 0x21, 0xA3, 0xE8, 0xE8,
+  0xE8, 0xE8, 0x73, 0x8C, 0x8A, 0x20, 0x20, 0x20,
+  0xDB, 0x33, 0x20, 0x20, 0x20, 0x20, 0xE6, 0xD9,
+  0xD9, 0xAC, 0xAC, 0xAF, 0xAC, 0xAF, 0xAC, 0xAF,
+  0xAF, 0xAC, 0xD9, 0xAF, 0xD9, 0xAC, 0xAC, 0xAF,
+  0x85, 0xD9, 0x95, 0xD9, 0x95, 0xD9, 0xD9, 0xAC,
+  0xAF, 0xAC, 0xAF, 0xAF, 0x2C, 0xAF, 0x2C, 0x2C,
+  0xAF, 0xAF, 0xAF, 0xAC, 0xAC, 0x2C, 0x20, 0x5B,
+  0x33, 0x20, 0xD6, 0xE8, 0xE8, 0xE8, 0xE8, 0x73,
+  0xAF, 0x2D, 0xD9, 0xDA, 0xB2, 0x81, 0x81, 0xE4,
+  0xA1, 0x91, 0x2B, 0x88, 0x33, 0x80, 0xAF, 0x73,
+  0xE8, 0xE8, 0xE8, 0x5C, 0xA3, 0x80, 0x41, 0xCC,
+  0x2B, 0xCC, 0x20, 0x20, 0x20, 0x20, 0x88, 0xDA,
+  0x2C, 0x2C, 0x2C, 0xAF, 0xAF, 0xAC, 0xAC, 0xAF,
+  0xAF, 0xAF, 0xAF, 0xAC, 0xAF, 0xAF, 0xAF, 0x2C,
+  0x85, 0xD9, 0xD9, 0xD9, 0xD9, 0xAC, 0xAC, 0xD9,
+  0xD9, 0xD9, 0xAC, 0x2C, 0x2C, 0x2C, 0x85, 0x85,
+  0x85, 0x2C, 0x2C, 0xAF, 0x2C, 0x91, 0x20, 0xAE,
+  0x20, 0xDB, 0x3D, 0xE8, 0xE8, 0x5C, 0xB2, 0x80,
+  0xB2, 0xAF, 0x48, 0xB2, 0x48, 0x89, 0x89, 0x3D,
+  0x21, 0x48, 0x6C, 0x2D, 0x2B, 0x41, 0xE3, 0xAE,
+  0xD9, 0x5C, 0xE8, 0xE8, 0xE8, 0x95, 0x33, 0x80,
+  0xAE, 0x33, 0x2B, 0x20, 0x20, 0x20, 0x20, 0x95,
+  0x85, 0x2C, 0x85, 0x2C, 0x2C, 0xAF, 0x2C, 0x2C,
+  0x2C, 0xAF, 0xAC, 0xAF, 0xAF, 0x2C, 0x2C, 0x2C,
+  0xDA, 0xAF, 0xD9, 0xD9, 0xAF, 0x2C, 0x2C, 0x2C,
+  0xAC, 0xD9, 0xAC, 0xAF, 0x2C, 0x85, 0x2C, 0x85,
+  0x85, 0x2C, 0x2C, 0x2C, 0x8A, 0x41, 0xDB, 0x33,
+  0x20, 0x95, 0xE8, 0xE8, 0xE8, 0xA3, 0xDB, 0x88,
+  0xDB, 0x80, 0xD6, 0x7E, 0x85, 0x2D, 0xE6, 0x5C,
+  0x21, 0x48, 0xD9, 0x7E, 0xD6, 0x2B, 0xCC, 0xAC,
+  0x85, 0xBC, 0xE8, 0xE8, 0xE8, 0xCD, 0x88, 0x5B,
+  0x41, 0x20, 0xAE, 0x20, 0x20, 0x20, 0x20, 0x74,
+  0xDA, 0x85, 0x85, 0x85, 0x2C, 0x2C, 0x2C, 0x2C,
+  0xAF, 0xAC, 0xD9, 0xD9, 0xAC, 0xAC, 0xAC, 0xD9,
+  0x8A, 0xAF, 0xAC, 0xAC, 0x2C, 0x85, 0x2C, 0xAF,
+  0xD9, 0xD9, 0xAF, 0xAF, 0xAF, 0x2C, 0xAF, 0x2C,
+  0x2C, 0x2C, 0x2C, 0xAF, 0x95, 0x20, 0x74, 0x20,
+  0x33, 0xA3, 0xE8, 0xE8, 0xE8, 0xE4, 0x7D, 0xCC,
+  0x6B, 0x33, 0xAE, 0x2C, 0x85, 0x2D, 0x9F, 0x73,
+  0xA1, 0x2D, 0x2C, 0xDA, 0x89, 0x48, 0xD3, 0xD9,
+  0x21, 0xA3, 0xE8, 0xE8, 0xE8, 0xE8, 0xE3, 0x20,
+  0x20, 0x20, 0xDB, 0x41, 0x20, 0x20, 0x20, 0x20,
+  0xDA, 0x2C, 0x2C, 0x2C, 0x2C, 0xAF, 0xAC, 0xAC,
+  0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0x95, 0x95, 0xD9,
+  0x2C, 0xD9, 0xD9, 0xAC, 0x2C, 0x2C, 0x85, 0xAF,
+  0xAF, 0xAF, 0xAC, 0xAC, 0xD9, 0xAC, 0xAF, 0xAC,
+  0xAC, 0x95, 0xD6, 0x7D, 0xAE, 0x88, 0x2B, 0x20,
+  0x6C, 0xE8, 0xE8, 0xE8, 0x73, 0xEE, 0x73, 0x2C,
+  0x89, 0x2B, 0x41, 0x33, 0xCC, 0xCC, 0x80, 0x3D,
+  0x2D, 0x74, 0x80, 0x48, 0x8D, 0x95, 0x48, 0x95,
+  0xEE, 0x5C, 0x5C, 0xE8, 0xE8, 0xE8, 0x24, 0x20,
+  0x20, 0x20, 0x5B, 0xDB, 0x20, 0x20, 0x20, 0x20,
+  0xAF, 0xAC, 0xD9, 0x95, 0xD6, 0xD6, 0xD6, 0x7D,
+  0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0xD9, 0xAC,
+  0xAC, 0xD9, 0xD9, 0xAC, 0x2C, 0x2C, 0x2C, 0xAF,
+  0xAC, 0xAC, 0xAC, 0xAC, 0xD9, 0xAC, 0xAC, 0xD9,
+  0xD6, 0x48, 0xE9, 0x95, 0x20, 0x2B, 0x41, 0x6B,
+  0x8D, 0xE8, 0xE8, 0xCD, 0x2B, 0x2B, 0x2C, 0x73,
+  0xCD, 0x48, 0xCA, 0x5B, 0x41, 0x5B, 0x74, 0xDA,
+  0x80, 0xE6, 0xC8, 0x85, 0xA1, 0x7D, 0x8D, 0x3D,
+  0x7E, 0xE9, 0x7D, 0xEE, 0xE8, 0xE8, 0x81, 0x20,
+  0x20, 0x20, 0xE3, 0xE3, 0x20, 0x20, 0x20, 0x20,
+  0x2D, 0xD9, 0xD6, 0x48, 0x6C, 0xE9, 0xA1, 0xD6,
+  0xD9, 0xD9, 0xAC, 0xD9, 0xD9, 0x95, 0xAC, 0x2C,
+  0x2C, 0x2C, 0x2C, 0xD9, 0xAC, 0x2C, 0x2C, 0x2C,
+  0xAF, 0x2C, 0xAF, 0xD9, 0xAC, 0xAF, 0xAF, 0x95,
+  0xB2, 0xE9, 0x21, 0x2B, 0x41, 0x2B, 0x20, 0x5B,
+  0x3D, 0xE8, 0xE8, 0x8D, 0x2B, 0x88, 0x5B, 0xE6,
+  0xBC, 0x73, 0x85, 0x89, 0x80, 0x5B, 0xE3, 0xAE,
+  0x2C, 0x8A, 0xD6, 0xB2, 0x2C, 0xA3, 0xA3, 0xD9,
+  0xA1, 0x2C, 0x85, 0x8D, 0xE8, 0xE8, 0x48, 0x20,
+  0x20, 0x20, 0xE3, 0x88, 0x20, 0x20, 0x20, 0x20,
+  0xAE, 0xD9, 0xB2, 0xE9, 0x6C, 0x48, 0xD6, 0xD9,
+  0x2C, 0x85, 0x2C, 0xD9, 0x7D, 0xD9, 0x2C, 0x85,
+  0x8D, 0x85, 0x2C, 0xAC, 0xAF, 0x2C, 0x2C, 0x85,
+  0x2C, 0x2C, 0xAF, 0xAC, 0xAC, 0xAF, 0xAF, 0xD9,
+  0xB2, 0x48, 0xB2, 0x20, 0x20, 0xCC, 0x20, 0x9F,
+  0xE8, 0xE8, 0xE8, 0xCD, 0x48, 0x89, 0xDB, 0x88,
+  0x2B, 0xE9, 0xCD, 0x2A, 0x48, 0x80, 0xAE, 0xAE,
+  0x7D, 0x48, 0x21, 0xEE, 0x3D, 0x2C, 0x48, 0x85,
+  0x2C, 0x95, 0x7D, 0x8C, 0xE8, 0xE8, 0xB2, 0x20,
+  0x20, 0x20, 0xDB, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0xDB, 0x2C, 0xB2, 0x48, 0x48, 0x7D, 0xD9, 0xAF,
+  0x85, 0x8A, 0x85, 0x7D, 0xB2, 0x95, 0x85, 0xDA,
+  0xD3, 0x85, 0xAF, 0xAC, 0x2C, 0x85, 0x85, 0x2C,
+  0xAC, 0xAC, 0xAC, 0xD9, 0xD9, 0xAC, 0x2C, 0x2C,
+  0xD9, 0xAC, 0x5B, 0x20, 0x20, 0xAE, 0x20, 0x2D,
+  0xE8, 0xE8, 0xE8, 0x7E, 0xD6, 0x48, 0xE9, 0xAE,
+  0x88, 0x5B, 0x80, 0x6C, 0xAE, 0xCA, 0x91, 0xE9,
+  0x43, 0x9F, 0xE6, 0x2C, 0x48, 0x21, 0xBC, 0x95,
+  0x95, 0xD6, 0x21, 0x7E, 0xE8, 0xE8, 0x7D, 0x20,
+  0x20, 0x20, 0x2B, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x6B, 0xDA, 0xD9, 0x48, 0xB2, 0xD9, 0x2C, 0x85,
+  0xDA, 0xDA, 0x2C, 0xA1, 0x48, 0xAC, 0xDA, 0x8D,
+  0x2A, 0xAC, 0x7D, 0x95, 0xAF, 0x85, 0x2C, 0x2C,
+  0xAC, 0xD9, 0x95, 0x7D, 0x95, 0xAC, 0x2C, 0xAF,
+  0x7D, 0xD6, 0x20, 0x20, 0x88, 0x9F, 0x20, 0xA1,
+  0xE8, 0xE8, 0xE8, 0xA3, 0xD6, 0x6C, 0xB2, 0x2C,
+  0x89, 0xE3, 0x88, 0xDB, 0xCC, 0x24, 0x7D, 0xEE,
+  0xB2, 0xCC, 0xAE, 0x2D, 0xDA, 0x2C, 0xD6, 0x2C,
+  0xB2, 0x2D, 0xD6, 0xEE, 0xE8, 0xE8, 0x95, 0x20,
+  0x20, 0x20, 0xDB, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x6B, 0xDA, 0x95, 0xA1, 0xB2, 0xAC, 0x85, 0x85,
+  0xDA, 0x2C, 0x95, 0xA1, 0x21, 0x2C, 0x8A, 0x2A,
+  0xAF, 0xA1, 0x48, 0xD6, 0xAF, 0x2C, 0x2C, 0xAC,
+  0xD9, 0xD9, 0x95, 0x7D, 0x95, 0xAC, 0xD9, 0x7D,
+  0x48, 0xE6, 0x20, 0x20, 0x33, 0x89, 0x6B, 0x95,
+  0xE8, 0xE8, 0xE8, 0xA3, 0x21, 0x48, 0xAF, 0xAF,
+  0x9F, 0xE9, 0x43, 0x33, 0x33, 0x2D, 0xDA, 0xCD,
+  0xD6, 0xAE, 0x85, 0x2C, 0x7D, 0xD6, 0x91, 0xB8,
+  0xD4, 0x48, 0x7D, 0xA3, 0xE8, 0xE8, 0x95, 0x20,
+  0x20, 0x33, 0xE3, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x2C, 0x48, 0x6C, 0xB2, 0xAF, 0xDA, 0xDA,
+  0x85, 0xAF, 0xD9, 0x95, 0xAC, 0xDA, 0x8A, 0xDA,
+  0x7D, 0x48, 0x48, 0x7D, 0x2C, 0x85, 0x2C, 0xAF,
+  0xD9, 0xD9, 0x7D, 0x95, 0xD9, 0xD9, 0x95, 0xD6,
+  0x21, 0x24, 0x20, 0x20, 0x20, 0x5B, 0xDB, 0xAC,
+  0xE8, 0xE8, 0xE8, 0x3D, 0x7D, 0x48, 0xE6, 0x2D,
+  0x85, 0x81, 0x81, 0x48, 0xAE, 0xCA, 0x89, 0xCC,
+  0xAE, 0xDB, 0x2D, 0x95, 0x21, 0xCC, 0xDB, 0xAE,
+  0x91, 0xE9, 0x7D, 0x73, 0xE8, 0xE8, 0x48, 0x20,
+  0x6B, 0x74, 0x41, 0x88, 0x6B, 0x20, 0x20, 0x20,
+  0x6B, 0x95, 0xB2, 0xD6, 0xD9, 0x85, 0xDA, 0xDA,
+  0xDA, 0x2C, 0xAF, 0xAF, 0x2C, 0xDA, 0xDA, 0x85,
+  0xA1, 0xE9, 0x48, 0x95, 0x85, 0xDA, 0x85, 0xAC,
+  0xD9, 0xD9, 0x95, 0x95, 0xD9, 0xD9, 0xD9, 0x95,
+  0x95, 0x6C, 0x41, 0x93, 0x93, 0x41, 0xDB, 0x95,
+  0xE8, 0xE8, 0xE8, 0x3D, 0x95, 0xD4, 0x6C, 0x21,
+  0x2D, 0x95, 0xCD, 0x2C, 0xD6, 0xD9, 0x6C, 0x91,
+  0x89, 0x7D, 0xAC, 0x2A, 0x8D, 0xE6, 0xCC, 0x88,
+  0x74, 0x48, 0xD9, 0xE4, 0xE8, 0xE8, 0xE6, 0x88,
+  0x2B, 0x88, 0x20, 0x33, 0xDB, 0x2B, 0xDB, 0x20,
+  0x91, 0x7D, 0xD9, 0xD9, 0x85, 0x85, 0xDA, 0xDA,
+  0x85, 0xAF, 0xAC, 0xAF, 0x2C, 0x2C, 0x2C, 0x2C,
+  0xA1, 0xA1, 0xD6, 0xAF, 0x85, 0xDA, 0x85, 0x2C,
+  0xD9, 0xD9, 0x95, 0x95, 0xD9, 0xD9, 0xD9, 0xAC,
+  0x2C, 0x47, 0x87, 0x3E, 0x3E, 0xA4, 0x7B, 0x80,
+  0xA3, 0xE8, 0xE8, 0x5C, 0x7D, 0x48, 0xE6, 0xD9,
+  0xBC, 0xEE, 0x7D, 0x43, 0xD6, 0x21, 0x43, 0x6C,
+  0x43, 0x7D, 0x7D, 0xB2, 0x8A, 0xEE, 0x2C, 0xCA,
+  0xAE, 0x48, 0x2C, 0xE4, 0xE8, 0x5C, 0xCC, 0x88,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x41, 0x91, 0xE3,
+  0x21, 0xD9, 0x2C, 0x2C, 0xDA, 0xDA, 0xDA, 0x85,
+  0x2C, 0xAC, 0xD9, 0xD9, 0xAC, 0xAF, 0xAF, 0xAF,
+  0xD6, 0x7D, 0xD9, 0x2C, 0xDA, 0xDA, 0x85, 0xAC,
+  0xD9, 0x7D, 0x7D, 0xD9, 0xD9, 0xD9, 0x2C, 0x2C,
+  0xB8, 0x9C, 0xEC, 0x62, 0x6F, 0x62, 0x70, 0x3C,
+  0xAE, 0xCD, 0xE8, 0xE8, 0x8C, 0x7D, 0xC8, 0x3D,
+  0x8A, 0xE9, 0x2D, 0x9E, 0xA1, 0xD6, 0x48, 0x73,
+  0x81, 0xD6, 0xD6, 0xAE, 0x5B, 0x2D, 0xA3, 0xA3,
+  0x21, 0x21, 0xCD, 0xE8, 0xC0, 0x56, 0x31, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x33, 0xCC, 0xDB,
+  0x42, 0x85, 0x85, 0x85, 0x85, 0x85, 0x2C, 0x2C,
+  0xAC, 0xD9, 0xD9, 0xD9, 0xAC, 0xAF, 0xAF, 0xAF,
+  0xD9, 0x95, 0xAC, 0x2C, 0x85, 0x85, 0x2C, 0xD9,
+  0x7D, 0xD6, 0xD6, 0xD9, 0xAC, 0xAF, 0x8A, 0xBC,
+  0xC2, 0x68, 0x2E, 0x4B, 0xC9, 0x8B, 0x62, 0x87,
+  0x3C, 0x74, 0xBC, 0xE8, 0xE8, 0xE4, 0xEE, 0xA1,
+  0xE9, 0x21, 0xE6, 0x89, 0x48, 0x7D, 0xB2, 0x5C,
+  0x6C, 0x7D, 0x21, 0x80, 0xE3, 0x33, 0xCC, 0x2C,
+  0x3D, 0x3D, 0xE8, 0xE8, 0xEC, 0xCB, 0x5A, 0x6B,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x88, 0x41, 0x51,
+  0x49, 0x28, 0x85, 0x85, 0x85, 0x85, 0x2C, 0xAF,
+  0xAC, 0xAC, 0xAF, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C,
+  0xD9, 0x95, 0xD9, 0x2C, 0x85, 0x85, 0x2C, 0xD9,
+  0xB2, 0xB2, 0x2C, 0x2A, 0x79, 0x79, 0x97, 0x44,
+  0xED, 0x29, 0x32, 0x62, 0x4B, 0x62, 0x6F, 0x22,
+  0xF3, 0x6B, 0x33, 0x85, 0x73, 0xE4, 0x2D, 0x2B,
+  0xCC, 0x9F, 0xDA, 0xBC, 0x48, 0xD6, 0xA1, 0xE4,
+  0xE9, 0xD6, 0xD9, 0x2A, 0xB2, 0x2B, 0x2B, 0xA1,
+  0xB8, 0xE8, 0xE8, 0xE8, 0xEC, 0x3E, 0x30, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x6B, 0x54, 0xDC,
+  0xC9, 0x53, 0xBC, 0x2C, 0x2C, 0x2C, 0xAF, 0xAF,
+  0xAF, 0xAC, 0xAF, 0xAC, 0xAC, 0x2C, 0xAF, 0xAC,
+  0x2C, 0x7D, 0xD9, 0x2C, 0x85, 0xDA, 0xAF, 0x7D,
+  0xB2, 0xAC, 0xC6, 0xBA, 0x4C, 0xEF, 0xA7, 0xEF,
+  0xEC, 0x7A, 0x62, 0x4B, 0x62, 0x4B, 0x8B, 0x4B,
+  0x3A, 0x52, 0x20, 0x6B, 0x21, 0x73, 0xAC, 0x2B,
+  0x41, 0x33, 0x48, 0x67, 0xA1, 0xD6, 0xD6, 0x5C,
+  0xE9, 0xD6, 0x2C, 0xEE, 0xB2, 0x9F, 0x8A, 0x95,
+  0x4D, 0xE8, 0xE8, 0x3D, 0x7A, 0x57, 0xD1, 0x7B,
+  0x20, 0x20, 0x20, 0x20, 0x6B, 0xCF, 0xBA, 0x3E,
+  0x3E, 0xD0, 0xBC, 0xAC, 0xAC, 0x2C, 0x2C, 0xAC,
+  0xD9, 0xD9, 0x95, 0x95, 0x7D, 0x95, 0x95, 0xD9,
+  0x85, 0xD9, 0xAF, 0xDA, 0xDA, 0x85, 0xAC, 0x21,
+  0xB2, 0x2A, 0xBA, 0x57, 0x2E, 0x2E, 0x2E, 0x7A,
+  0x32, 0x62, 0x8B, 0x4B, 0x8B, 0x4B, 0x4B, 0x4B,
+  0xC9, 0x4A, 0x5F, 0x20, 0x20, 0x2D, 0xA3, 0xD9,
+  0xCA, 0x88, 0xDB, 0x24, 0x48, 0x7D, 0xB2, 0xE4,
+  0x2D, 0x7D, 0x7D, 0x81, 0xA1, 0xDA, 0x21, 0xDA,
+  0xE4, 0xE8, 0xEE, 0xF1, 0x2E, 0x57, 0x82, 0x76,
+  0x52, 0x4F, 0x4F, 0x98, 0xDE, 0xB5, 0xEC, 0x2E,
+  0x3E, 0x6D, 0x85, 0x2C, 0xAC, 0xAC, 0xD9, 0xD9,
+  0x95, 0xD6, 0x7D, 0x7D, 0x95, 0xD9, 0xD9, 0xD9,
+  0xDA, 0x2C, 0x85, 0xDA, 0xDA, 0x2C, 0x95, 0xB2,
+  0x21, 0xB8, 0xED, 0x2E, 0x3E, 0x4B, 0xC9, 0x4B,
+  0x8B, 0x62, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B,
+  0x22, 0x6F, 0xCE, 0x20, 0x20, 0x20, 0x80, 0xCD,
+  0xDA, 0x2D, 0x2B, 0xDB, 0xE9, 0xD6, 0x95, 0x5C,
+  0x2D, 0x7D, 0x7D, 0xAF, 0xAF, 0xAC, 0xEE, 0x5C,
+  0xE8, 0xE8, 0xEB, 0x25, 0x7A, 0x57, 0x39, 0xE1,
+  0x83, 0xA8, 0x55, 0x83, 0x82, 0x57, 0x32, 0x8B,
+  0x62, 0x6D, 0xEB, 0x95, 0xD9, 0xD9, 0xD9, 0xD9,
+  0xD9, 0xD9, 0xD9, 0xAF, 0x2C, 0x2C, 0x2C, 0x2C,
+  0xDA, 0x2C, 0x85, 0x85, 0x85, 0xAC, 0xD6, 0x21,
+  0x95, 0x6E, 0xED, 0x57, 0x62, 0x4B, 0x8B, 0x4B,
+  0x4B, 0x62, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x62,
+  0x62, 0x62, 0x25, 0x3C, 0x20, 0x20, 0x20, 0xE3,
+  0x2A, 0xBC, 0x7D, 0xCA, 0x6C, 0xD6, 0x95, 0x3D,
+  0x81, 0x7D, 0xD6, 0xD6, 0xDA, 0x73, 0xE8, 0xE8,
+  0xE8, 0x4D, 0x94, 0xED, 0x72, 0x3A, 0xF1, 0xA7,
+  0x39, 0xED, 0x39, 0xEF, 0x57, 0x32, 0x8B, 0x4B,
+  0x62, 0x62, 0xA6, 0x2A, 0xD9, 0xD9, 0xD9, 0xD9,
+  0x2C, 0x2C, 0x85, 0x85, 0x85, 0x85, 0x85, 0x85,
+  0x85, 0x2C, 0x2C, 0xAF, 0xAC, 0x95, 0x21, 0x7D,
+  0xAC, 0x8C, 0x46, 0xC4, 0x62, 0x8B, 0x4B, 0x4B,
+  0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B,
+  0x4B, 0x62, 0xC9, 0x30, 0x7B, 0x20, 0x20, 0x20,
+  0x41, 0x4D, 0x3D, 0x85, 0x48, 0x21, 0xDA, 0x3D,
+  0xE9, 0xD6, 0xD9, 0xCD, 0x5C, 0xE8, 0xE8, 0xE8,
+  0xE8, 0x4D, 0x71, 0x46, 0xEC, 0x2E, 0x72, 0xEC,
+  0x29, 0x29, 0x7C, 0x29, 0x2E, 0x4B, 0x4B, 0x62,
+  0x62, 0x4B, 0x3A, 0xAD, 0xE2, 0xAF, 0xD9, 0xD9,
+  0x2C, 0xDA, 0xDA, 0xDA, 0xDA, 0x85, 0x2C, 0x2C,
+  0x2C, 0xAF, 0xAC, 0xD9, 0x95, 0xD6, 0xD6, 0xD9,
+  0x2C, 0x8C, 0xBA, 0x7C, 0x2E, 0x4B, 0x4B, 0x4B,
+  0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B,
+  0x4B, 0x62, 0xC9, 0xDC, 0x34, 0x20, 0x20, 0x20,
+  0x20, 0xAC, 0xE8, 0x5C, 0x8C, 0xBC, 0xE4, 0xE8,
+  0xEE, 0x2A, 0xA3, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8,
+  0xE4, 0x7E, 0x65, 0x46, 0x29, 0x62, 0x62, 0x2E,
+  0x2E, 0x72, 0x2E, 0x2E, 0x32, 0x4B, 0x4B, 0x62,
+  0x4B, 0x4B, 0x4B, 0x32, 0x61, 0x9D, 0x2C, 0xD9,
+  0x2C, 0x85, 0xDA, 0x85, 0x2C, 0xAF, 0xAF, 0xAF,
+  0x2C, 0xAC, 0xD9, 0x95, 0xD6, 0x7D, 0x95, 0xAC,
+  0x2C, 0xDA, 0x40, 0x7C, 0x2E, 0x4B, 0x4B, 0x4B,
+  0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B,
+  0x4B, 0x62, 0x62, 0x22, 0xB7, 0xCE, 0x20, 0x20,
+  0x20, 0x95, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8,
+  0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0x5C,
+  0x3D, 0xE9, 0x9A, 0x46, 0x7C, 0x32, 0x8B, 0x62,
+  0x4B, 0x8B, 0x8B, 0x4B, 0x4B, 0x4B, 0x4B, 0x62,
+  0x4B, 0x4B, 0x4B, 0x4B, 0x62, 0x61, 0x4E, 0xDA,
+  0x85, 0x85, 0x85, 0x2C, 0xD9, 0xD9, 0xD9, 0xD9,
+  0x85, 0xD9, 0x7D, 0x21, 0x21, 0xD6, 0xAC, 0x2C,
+  0x2C, 0xDA, 0xDD, 0x77, 0x8B, 0x62, 0x4B, 0x4B,
+  0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B,
+  0x3E, 0x8B, 0x32, 0xC9, 0x22, 0x68, 0x88, 0x33,
+  0xA1, 0x73, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8,
+  0xE8, 0xE8, 0xE8, 0x5C, 0x5C, 0x5C, 0x5C, 0x3D,
+  0x89, 0x20, 0x54, 0x23, 0x29, 0x2E, 0x4B, 0x62,
+  0x4B, 0x3E, 0x4B, 0x62, 0x4B, 0x4B, 0x4B, 0x8B,
+  0x8B, 0xC9, 0x6F, 0x4B, 0x8B, 0x4B, 0x78, 0xE2,
+  0x8A, 0x8A, 0x85, 0xAC, 0xD9, 0x7D, 0xD9, 0xAC,
+  0x2C, 0xD9, 0xD6, 0xB2, 0x21, 0x7D, 0xAF, 0x85,
+  0x2C, 0xDA, 0x40, 0xEF, 0x62, 0x62, 0x4B, 0x4B,
+  0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B,
+  0x4B, 0x4B, 0x8B, 0x4B, 0xC9, 0x63, 0xB4, 0x5C,
+  0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8,
+  0xE8, 0xE8, 0xE8, 0xE8, 0x5C, 0x5C, 0xCD, 0xAE,
+  0x20, 0x20, 0xCE, 0xE1, 0x57, 0x32, 0x4B, 0x4B,
+  0x8B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B,
+  0x8B, 0x4B, 0x62, 0x4B, 0x62, 0x2E, 0x61, 0x28,
+  0x8D, 0xDA, 0xAF, 0xD9, 0x95, 0x95, 0xD9, 0xAF,
+  0xAF, 0xD9, 0xD6, 0xB2, 0x21, 0xD9, 0x2C, 0x85,
+  0xAF, 0xEB, 0xE1, 0x57, 0x2E, 0x62, 0x4B, 0x4B,
+  0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B,
+  0x4B, 0x4B, 0x4B, 0x4B, 0x3E, 0x9B, 0x31, 0x6E,
+  0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8,
+  0x5C, 0xE8, 0xE8, 0xE8, 0x3D, 0x7D, 0x33, 0x6B,
+  0x20, 0x20, 0x34, 0x23, 0x29, 0x3E, 0x4B, 0x4B,
+  0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B,
+  0x4B, 0x3E, 0x62, 0x62, 0x2E, 0xC4, 0x49, 0xD5,
+  0xDA, 0xD9, 0xD6, 0xA1, 0xA1, 0x21, 0xD9, 0xD9,
+  0xD9, 0x95, 0x21, 0x48, 0xD6, 0xAC, 0x85, 0x85,
+  0xAF, 0xB6, 0x5D, 0x2E, 0x32, 0x4B, 0x4B, 0x4B,
+  0x4B, 0x4B, 0x62, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B,
+  0x4B, 0x4B, 0x4B, 0x4B, 0x62, 0x2E, 0x45, 0xDE,
+  0xDA, 0x5C, 0xE8, 0x5C, 0xE8, 0xE8, 0x5C, 0xE8,
+  0x5C, 0x5C, 0xA3, 0xAC, 0x2B, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x34, 0x23, 0x29, 0x62, 0x4B, 0x4B,
+  0x4B, 0x4B, 0x4B, 0x4B, 0x62, 0x4B, 0x4B, 0x4B,
+  0x4B, 0x3E, 0x3E, 0x63, 0x40, 0x97, 0x28, 0xDA,
+  0xD9, 0xA1, 0x48, 0xE9, 0x48, 0x21, 0xD9, 0xD9,
+  0xA1, 0xB2, 0xB2, 0xA1, 0x21, 0xAC, 0x85, 0x2C,
+  0xDA, 0x36, 0x77, 0x72, 0x62, 0x8B, 0x62, 0x4B,
+  0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B,
+  0x4B, 0x4B, 0x4B, 0x4B, 0x3E, 0xEC, 0x2F, 0x51,
+  0xE3, 0xAE, 0x48, 0x2C, 0xDA, 0xDA, 0x85, 0xAC,
+  0x48, 0x9E, 0x88, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x41, 0xA0, 0x23, 0x72, 0x2E, 0x4B, 0x4B,
+  0x4B, 0x62, 0x62, 0x4B, 0x4B, 0x4B, 0x2E, 0x8B,
+  0xF0, 0x4C, 0x40, 0xC2, 0x90, 0x8D, 0x85, 0xD9,
+  0xA1, 0x6C, 0x6C, 0x48, 0xD6, 0xD9, 0xAF, 0xAC,
+  0xA1, 0xD6, 0xD6, 0xB2, 0xD6, 0xAC, 0x85, 0x85,
+  0x4D, 0xBE, 0x39, 0x4C, 0x57, 0x2E, 0x2E, 0x2E,
+  0x3E, 0x3E, 0x62, 0x3E, 0x4B, 0x4B, 0x4B, 0x4B,
+  0x4B, 0x4B, 0x4B, 0x8B, 0x8B, 0x57, 0x60, 0x76,
+  0x52, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x3C, 0xA0, 0x23, 0x7C, 0x2E, 0x4B, 0x4B,
+  0x8B, 0x62, 0x4B, 0x4B, 0x3E, 0x7A, 0xF0, 0x29,
+  0x36, 0x97, 0xBC, 0x8A, 0x8D, 0xDA, 0xD9, 0x48,
+  0x81, 0x2D, 0x48, 0xD6, 0xD9, 0xAF, 0x2C, 0x2C,
+  0xAC, 0xAF, 0xD9, 0x7D, 0x7D, 0x2C, 0x85, 0x85,
+  0x85, 0xB4, 0x66, 0x23, 0x46, 0x2F, 0x60, 0x68,
+  0x77, 0x29, 0x29, 0xF0, 0x2E, 0x2E, 0x62, 0x4B,
+  0x4B, 0x4B, 0x4B, 0x4B, 0x32, 0x7C, 0x83, 0xB3,
+  0x54, 0x6B, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x6B, 0x7B, 0xC3, 0xE7, 0x39, 0x72, 0x62, 0x62,
+  0x62, 0x62, 0x62, 0x2E, 0x29, 0x77, 0xA7, 0x36,
+  0xB8, 0x85, 0x85, 0x8D, 0x8D, 0x85, 0xB2, 0x2D,
+  0x2D, 0xE9, 0xD6, 0xD9, 0xAF, 0x2C, 0x85, 0x85,
+  0x2A, 0x85, 0xAC, 0x95, 0x95, 0xAF, 0x85, 0x85,
+  0xAF, 0x8C, 0xDF, 0xC6, 0xB1, 0xD1, 0xE5, 0xE7,
+  0x83, 0x23, 0x5D, 0x60, 0x39, 0x77, 0xEC, 0x2E,
+  0x2E, 0x32, 0x32, 0x2E, 0x7C, 0x5D, 0x35, 0xA2,
+  0x54, 0x6B, 0x6B, 0x20, 0x6B, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x6B, 0x88, 0xC1, 0x35, 0xE1, 0x77, 0x57, 0x2E,
+  0x2E, 0x72, 0x29, 0x77, 0x60, 0xB5, 0x44, 0xE2,
+  0x2C, 0x2C, 0xDA, 0x8A, 0xDA, 0xAF, 0xA1, 0x2D,
+  0xE9, 0xD6, 0xD9, 0xAF, 0x2C, 0x85, 0x85, 0x85,
+  0xEE, 0xAF, 0xD9, 0x7D, 0xD9, 0x2C, 0xDA, 0x85,
+  0xAC, 0xAF, 0x85, 0xDA, 0x8A, 0x2A, 0xE2, 0x50,
+  0x86, 0xD7, 0x75, 0x35, 0xA8, 0xE7, 0xE1, 0x5D,
+  0x68, 0x7C, 0xF1, 0x68, 0xE1, 0xBF, 0xA2, 0xC1,
+  0x52, 0x2B, 0x7D, 0xAC, 0xAF, 0x2C, 0x2C, 0x2C,
+  0x2C, 0x85, 0x85, 0x85, 0x2C, 0x2C, 0x2C, 0x95,
+  0xE9, 0x74, 0xCE, 0xE0, 0xE7, 0x60, 0x77, 0x77,
+  0x7C, 0xEF, 0x5D, 0x23, 0x3F, 0xB6, 0x8A, 0x2C,
+  0xAC, 0xAF, 0x85, 0x8A, 0x85, 0xD9, 0x48, 0x48,
+  0xB2, 0x95, 0x95, 0xD9, 0x85, 0xDA, 0x85, 0x85,
+  0xD3, 0xB2, 0x21, 0x7D, 0xAC, 0x2C, 0xDA, 0x85,
+  0xAC, 0xAC, 0x85, 0x85, 0x85, 0x2C, 0xAF, 0x2C,
+  0xDA, 0x8C, 0x79, 0xC7, 0xB0, 0x51, 0xB3, 0x35,
+  0xBF, 0xE5, 0xE7, 0xA8, 0xE0, 0xA2, 0xC1, 0x34,
+  0x7D, 0x85, 0xAC, 0xD9, 0xAC, 0xAF, 0xAC, 0xAC,
+  0xAF, 0x2C, 0x2C, 0x2C, 0x2C, 0xAF, 0xAF, 0x85,
+  0xC8, 0xCD, 0x6A, 0x26, 0x35, 0x3F, 0x83, 0x23,
+  0x23, 0xE7, 0xBF, 0x96, 0xEB, 0xDA, 0xDA, 0x2C,
+  0x2C, 0x2C, 0x85, 0xDA, 0x2C, 0x7D, 0xA1, 0x48,
+  0xB2, 0x21, 0xD6, 0xD9, 0x2C, 0xDA, 0x85, 0xAF,
+  0xAF, 0x2D, 0xE9, 0x7D, 0xAC, 0x2C, 0x85, 0x2C,
+  0xD9, 0xD9, 0xAF, 0x85, 0x85, 0x85, 0x2C, 0x2C,
+  0x2C, 0x85, 0xD9, 0x21, 0xAC, 0x2C, 0xBD, 0xA5,
+  0xC3, 0xA2, 0xA2, 0xA2, 0x26, 0xC1, 0xCE, 0x2A,
+  0xAF, 0x95, 0xD9, 0x2C, 0x2C, 0x85, 0x2C, 0xAF,
+  0xAC, 0x2C, 0x85, 0x2C, 0xAF, 0x2C, 0x85, 0xDA,
+  0x8D, 0x2A, 0x85, 0x34, 0xC1, 0xB3, 0x76, 0x35,
+  0xE0, 0x30, 0xA5, 0xB6, 0x2C, 0x85, 0x85, 0x85,
+  0xAF, 0x2C, 0x85, 0x85, 0xD9, 0xD6, 0xA1, 0xA1,
+  0x48, 0xA1, 0xD6, 0xAF, 0xDA, 0x8A, 0x2C, 0xD9,
+  0xB2, 0x2D, 0x48, 0xD9, 0xAF, 0x2C, 0x2C, 0x85,
+  0xAF, 0xAC, 0x2C, 0x85, 0x85, 0x85, 0xAF, 0xAC,
+  0xAC, 0x2C, 0xD9, 0xD6, 0xD6, 0x21, 0xB2, 0x2C,
+  0xC8, 0x3B, 0x65, 0xC5, 0xCE, 0x8E, 0xC8, 0x2C,
+  0xD9, 0x95, 0xAC, 0x2C, 0x2C, 0x2C, 0xAF, 0xAC,
+  0xAC, 0xAF, 0x2C, 0x85, 0x2C, 0x2C, 0x2C, 0x85,
+  0xDA, 0x2C, 0xD6, 0xAF, 0x59, 0x65, 0xDE, 0xF3,
+  0xF3, 0x59, 0xBC, 0xAC, 0xAF, 0x85, 0x85, 0x85,
+  0xAF, 0xD9, 0xAF, 0x2C, 0xD9, 0xD6, 0xD6, 0xD6,
+  0x21, 0xD6, 0xD9, 0xDA, 0x8D, 0x8A, 0x2C, 0xD9,
+  0xB2, 0xA1, 0xD6, 0xAC, 0x2C, 0x2C, 0x2C, 0x85,
+  0x2C, 0xAC, 0x2C, 0xDA, 0xDA, 0x85, 0xAF, 0xD9,
+  0xD9, 0xAC, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xAC,
+  0x85, 0x2A, 0x4D, 0xBC, 0x85, 0xAC, 0xAF, 0xAF,
+  0xAC, 0xD9, 0xAF, 0x2C, 0xAF, 0xD9, 0xD9, 0xAC,
+  0xAC, 0xAF, 0x85, 0x2C, 0x85, 0x2C, 0x2C, 0x2C,
+  0x2C, 0xD9, 0xB2, 0xD4, 0xD6, 0x2C, 0x8A, 0xDA,
+  0xC8, 0x85, 0x2C, 0xAC, 0x2C, 0xDA, 0xDA, 0x85,
+  0xAF, 0xAC, 0xD9, 0xAC, 0xD9, 0xD9, 0xD9, 0xD9,
+  0xD9, 0xAC, 0xDA, 0x8D, 0xBC, 0xDA, 0xD9, 0x95,
+  0x95, 0xD9, 0xD9, 0xAF, 0x2C, 0x2C, 0x2C, 0x85,
+  0x2C, 0xAF, 0xAF, 0x85, 0x85, 0x85, 0x2C, 0xAC,
+  0xD9, 0xAF, 0xAF, 0xAF, 0x2C, 0x2C, 0x2C, 0x85,
+  0x8A, 0x2A, 0x8D, 0x2C, 0xD9, 0x95, 0xAC, 0xAC,
+  0xD9, 0xD9, 0xD9, 0xD9, 0x95, 0x95, 0xD9, 0xAF,
+  0xAF, 0x2C, 0x85, 0x85, 0x85, 0x85, 0x85, 0x2C,
+  0x85, 0x2C, 0xD9, 0xD9, 0xD9, 0x2C, 0x2C, 0x2C,
+  0x2C, 0x85, 0x85, 0xAF, 0xAF, 0x85, 0x85, 0x85,
+  0xAF, 0xD9, 0xD9, 0xAC, 0xAF, 0x2C, 0x2C, 0x2C,
+  0x2C, 0x85, 0x8A, 0x2A, 0x8D, 0x2C, 0xD9, 0xD9,
+  0x2C, 0xAC, 0xAF, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C,
+  0x85, 0xAF, 0xAC, 0x2C, 0x2C, 0x2C, 0x2C, 0xAC,
+  0xD9, 0xD9, 0xAF, 0x85, 0x85, 0x85, 0xDA, 0xDA,
+  0x8A, 0x8A, 0x85, 0xAC, 0xD9, 0xD9, 0xAC, 0xD9,
+  0xD6, 0xD6, 0x7D, 0x95, 0x7D, 0xD9, 0xAF, 0xAF,
+  0xAF, 0x2C, 0x85, 0x85, 0xDA, 0x85, 0x2C, 0x85,
+  0x85, 0x2C, 0xAF, 0xAC, 0xAF, 0xAF, 0x2C, 0x2C,
+  0x2C, 0x2C, 0x2C, 0xAF, 0xAC, 0x2C, 0x2C, 0x2C,
+  0x2C, 0xAF, 0xD9, 0xAC, 0xAF, 0x2C, 0x85, 0x85,
+  0x85, 0xDA, 0x8D, 0x8A, 0x85, 0xAC, 0x95, 0xD9
+};
+
+#define INCLUDE_LINUX_LOGOBW
+#define INCLUDE_LINUX_LOGO16
+#include <linux/linux_logo.h>
+
+#else
+
+/* prototypes only */
+extern unsigned char linux_logo_red[];
+extern unsigned char linux_logo_green[];
+extern unsigned char linux_logo_blue[];
+extern unsigned char linux_logo[];
+extern unsigned char linux_logo_bw[];
+extern unsigned char linux_logo16_red[];
+extern unsigned char linux_logo16_green[];
+extern unsigned char linux_logo16_blue[];
+extern unsigned char linux_logo16[];
+
+#endif
diff -ruN linux-mips/include/asm-mips/linux_logo_vr.h linux-vr/include/asm-mips/linux_logo_vr.h
--- linux-mips/include/asm-mips/linux_logo_vr.h	Wed Dec 31 16:00:00 1969
+++ linux-vr/include/asm-mips/linux_logo_vr.h	Tue Feb 15 05:38:58 2000
@@ -0,0 +1,644 @@
+#if LINUX_LOGO_COLORS == 214
+
+unsigned char linux_logo_red[] __initdata = {
+  0xc6, 0x9e, 0x8a, 0x8e, 0xae, 0xa6, 0x96, 0x76, 0x7e, 0xb6, 0x86, 0xbe, 0xc2, 0xce, 0x6e, 0x6a, 
+  0x56, 0x0e, 0x02, 0x06, 0x36, 0x3e, 0x12, 0x0a, 0x5e, 0x2a, 0x4e, 0x26, 0x1e, 0x16, 0x66, 0xe6, 
+  0xee, 0xfa, 0x2e, 0xf6, 0x1e, 0xfe, 0x52, 0x2e, 0x1e, 0x46, 0x1e, 0xaa, 0xca, 0xd2, 0xca, 0xa6, 
+  0xd6, 0x3a, 0xda, 0x4e, 0xaa, 0xce, 0xea, 0xda, 0xee, 0xc2, 0x72, 0x5a, 0xe6, 0xc6, 0xba, 0xde, 
+  0xee, 0xde, 0xea, 0xee, 0xf6, 0xf6, 0xda, 0xce, 0x96, 0x16, 0x3a, 0xae, 0xca, 0xe6, 0xf6, 0xf2, 
+  0xd6, 0x0e, 0x86, 0xbe, 0xee, 0xf6, 0xba, 0xde, 0x52, 0xca, 0x8a, 0xba, 0xde, 0xea, 0xee, 0xc6, 
+  0xd2, 0x3e, 0x82, 0xb2, 0xce, 0xb2, 0x9e, 0xa2, 0xb6, 0xce, 0xc2, 0xd2, 0xca, 0xc6, 0xba, 0x96, 
+  0xd6, 0xc6, 0xc6, 0xc6, 0xba, 0xa6, 0xaa, 0xc6, 0xb6, 0xaa, 0xaa, 0xb6, 0x46, 0xd2, 0xaa, 0x72, 
+  0xe2, 0x3a, 0xfa, 0x1a, 0x1e, 0xba, 0xa2, 0xf6, 0xaa, 0xce, 0xee, 0xf6, 0xf2, 0x9e, 0xda, 0xea, 
+  0xfa, 0xe6, 0xf6, 0x0a, 0x7e, 0xce, 0xd2, 0xe6, 0xce, 0xe2, 0x4a, 0xc2, 0xce, 0x36, 0xce, 0xf2, 
+  0xaa, 0x92, 0x26, 0x6a, 0xd6, 0x5e, 0xbe, 0xb6, 0xb6, 0xc2, 0xd6, 0xca, 0x66, 0x7a, 0xde, 0xea, 
+  0xea, 0xe6, 0xe6, 0xe2, 0xe6, 0xda, 0xda, 0xee, 0xce, 0xde, 0x52, 0x42, 0xbe, 0x6e, 0xbe, 0xd6, 
+  0x6e, 0xba, 0x96, 0x7e, 0xe6, 0xd2, 0xc2, 0xaa, 0xae, 0xca, 0xc2, 0xba, 0x92, 0x9e, 0x96, 0x9e, 
+  0x96, 0x62, 0x8a, 0x76, 0x7a, 0x82, 0x72, 0x72, 0x96, 0xe6, 0xe6, 0xde, 0x00, 0x00, 0x00, 0x00
+};
+
+unsigned char linux_logo_green[] __initdata = {
+  0xc6, 0x9e, 0x8a, 0x8e, 0xae, 0xa6, 0x96, 0x76, 0x7e, 0xb6, 0x86, 0xbe, 0xc2, 0xce, 0x6e, 0x6a, 
+  0x56, 0x0e, 0x02, 0x06, 0x36, 0x3e, 0x12, 0x0a, 0x5e, 0x2a, 0x4e, 0x26, 0x1e, 0x16, 0x66, 0xe6, 
+  0xee, 0xfa, 0x2e, 0xf6, 0x1e, 0xfe, 0x5a, 0x1e, 0x12, 0x3e, 0x0e, 0x8a, 0xa2, 0xaa, 0xa6, 0x86, 
+  0xba, 0x2e, 0xda, 0x3e, 0x7e, 0x9a, 0xbe, 0xb2, 0xca, 0xaa, 0x5a, 0x46, 0xde, 0xaa, 0x8a, 0xa2, 
+  0xb6, 0xbe, 0xc6, 0xd6, 0xda, 0xd6, 0xbe, 0xb6, 0x7a, 0x0e, 0x26, 0x7a, 0x92, 0xae, 0xda, 0xbe, 
+  0xd6, 0x06, 0x62, 0x8e, 0xb6, 0xd6, 0x8e, 0xa6, 0x46, 0xca, 0x5e, 0x92, 0xaa, 0xbe, 0xc6, 0x96, 
+  0xa2, 0x36, 0x56, 0x82, 0x92, 0x82, 0x92, 0x72, 0x7a, 0x8e, 0x96, 0xba, 0xba, 0xca, 0xa2, 0x6e, 
+  0x9a, 0x86, 0xbe, 0xbe, 0xaa, 0x6e, 0x7a, 0xb6, 0x9e, 0x92, 0x9a, 0xaa, 0x46, 0xd2, 0xaa, 0x72, 
+  0xe2, 0x3a, 0xf6, 0x1a, 0x1a, 0xb2, 0x7e, 0xbe, 0x8e, 0xaa, 0xae, 0xbe, 0xe2, 0x8a, 0xc2, 0xae, 
+  0xba, 0xaa, 0xca, 0x06, 0x66, 0xc6, 0xc2, 0xd2, 0xae, 0xa6, 0x32, 0x92, 0x9e, 0x1a, 0xc6, 0xb6, 
+  0x8e, 0x62, 0x12, 0x46, 0xce, 0x42, 0x82, 0x76, 0x86, 0x8e, 0xca, 0xbe, 0x46, 0x6a, 0xc2, 0xe6, 
+  0xda, 0xc2, 0xb6, 0xca, 0xba, 0xbe, 0xd2, 0xde, 0xa6, 0x9e, 0x3a, 0x26, 0x9a, 0x4e, 0x9e, 0x96, 
+  0x4e, 0x92, 0x62, 0x4a, 0xd6, 0xbe, 0x9e, 0x76, 0x6e, 0xb2, 0xb2, 0x96, 0x6e, 0x62, 0x72, 0x6a, 
+  0x86, 0x4e, 0x6e, 0x56, 0x62, 0x76, 0x5e, 0x56, 0x82, 0xc6, 0xde, 0xca, 0x00, 0x00, 0x00, 0x00
+};
+
+unsigned char linux_logo_blue[] __initdata = {
+  0xc4, 0x9c, 0x8c, 0x8c, 0xac, 0xa4, 0x94, 0x74, 0x7c, 0xb4, 0x84, 0xbc, 0xc4, 0xc4, 0x6c, 0x6c, 
+  0x54, 0x0c, 0x04, 0x04, 0x34, 0x3c, 0x14, 0x0c, 0x5c, 0x2c, 0x4c, 0x24, 0x1c, 0x14, 0x64, 0xe4, 
+  0xec, 0xfc, 0x2c, 0xf4, 0x0c, 0xfc, 0x5c, 0x0c, 0x04, 0x3c, 0x04, 0x3c, 0x14, 0x1c, 0x2c, 0x24, 
+  0x7c, 0x14, 0xdc, 0x14, 0x24, 0x0c, 0x0c, 0x14, 0x14, 0x2c, 0x1c, 0x1c, 0xdc, 0x74, 0x24, 0x0c, 
+  0x14, 0x0c, 0x14, 0x24, 0x34, 0x14, 0x24, 0x3c, 0x2c, 0x0c, 0x0c, 0x14, 0x1c, 0x0c, 0x14, 0x34, 
+  0xd4, 0x0c, 0x14, 0x0c, 0x0c, 0x24, 0x14, 0x1c, 0x14, 0xcc, 0x0c, 0x14, 0x14, 0x14, 0x0c, 0x0c, 
+  0x0c, 0x0c, 0x04, 0x04, 0x0c, 0x3c, 0x7c, 0x0c, 0x0c, 0x0c, 0x44, 0x8c, 0xac, 0xc4, 0x7c, 0x24, 
+  0x0c, 0x0c, 0xb4, 0xac, 0x7c, 0x0c, 0x0c, 0x94, 0x7c, 0x64, 0x74, 0x94, 0x44, 0xd4, 0xac, 0x74, 
+  0xe4, 0x3c, 0xfc, 0x1c, 0x1c, 0x9c, 0x1c, 0x14, 0x34, 0x4c, 0x14, 0x0c, 0xb4, 0x2c, 0x84, 0x0c, 
+  0x0c, 0x14, 0x14, 0x0c, 0x14, 0xa4, 0x94, 0x94, 0x5c, 0x0c, 0x0c, 0x2c, 0x1c, 0x04, 0xb4, 0x0c, 
+  0x14, 0x14, 0x04, 0x04, 0xbc, 0x14, 0x0c, 0x0c, 0x1c, 0x14, 0xbc, 0x8c, 0x0c, 0x4c, 0x54, 0xc4, 
+  0x6c, 0x44, 0x44, 0x6c, 0x2c, 0x4c, 0xbc, 0x9c, 0x44, 0x0c, 0x0c, 0x0c, 0x0c, 0x1c, 0x4c, 0x0c, 
+  0x0c, 0x2c, 0x0c, 0x04, 0xb4, 0x94, 0x5c, 0x0c, 0x04, 0x74, 0x8c, 0x54, 0x14, 0x04, 0x2c, 0x04, 
+  0x74, 0x24, 0x3c, 0x0c, 0x3c, 0x5c, 0x3c, 0x24, 0x5c, 0x2c, 0xbc, 0x94, 0x00, 0x00, 0x00, 0x00
+};
+
+unsigned char linux_logo[] __initdata = {
+  0x20, 0x21, 0x22, 0x23, 0x21, 0x24, 0x25, 0x25, 0x21, 0x26, 0x23, 0x22, 0x23, 0x21, 0x25, 0x21, 
+  0x23, 0x27, 0x28, 0x21, 0x24, 0x29, 0x29, 0x25, 0x22, 0x27, 0x2a, 0x25, 0x2b, 0x2c, 0x2b, 0x29, 
+  0x24, 0x25, 0x26, 0x21, 0x25, 0x25, 0x26, 0x26, 0x21, 0x24, 0x24, 0x24, 0x2b, 0x20, 0x2c, 0x2c, 
+  0x20, 0x2d, 0x20, 0x21, 0x22, 0x23, 0x21, 0x24, 0x25, 0x25, 0x21, 0x26, 0x23, 0x22, 0x23, 0x21, 
+  0x25, 0x21, 0x23, 0x27, 0x28, 0x21, 0x24, 0x29, 0x29, 0x25, 0x22, 0x27, 0x2a, 0x25, 0x2b, 0x2c, 
+  0x21, 0x27, 0x27, 0x22, 0x25, 0x25, 0x25, 0x21, 0x26, 0x26, 0x23, 0x22, 0x23, 0x26, 0x26, 0x23, 
+  0x27, 0x2e, 0x2a, 0x21, 0x29, 0x29, 0x24, 0x25, 0x26, 0x26, 0x21, 0x29, 0x2b, 0x29, 0x24, 0x25, 
+  0x25, 0x21, 0x26, 0x21, 0x21, 0x21, 0x25, 0x25, 0x24, 0x24, 0x25, 0x25, 0x24, 0x29, 0x29, 0x29, 
+  0x29, 0x29, 0x21, 0x27, 0x27, 0x22, 0x25, 0x25, 0x25, 0x21, 0x26, 0x26, 0x23, 0x22, 0x23, 0x26, 
+  0x26, 0x23, 0x27, 0x2e, 0x2a, 0x21, 0x29, 0x29, 0x24, 0x25, 0x26, 0x26, 0x21, 0x29, 0x2b, 0x29, 
+  0x22, 0x27, 0x27, 0x2a, 0x25, 0x24, 0x25, 0x21, 0x26, 0x26, 0x22, 0x23, 0x26, 0x26, 0x26, 0x2a, 
+  0x28, 0x2a, 0x21, 0x24, 0x29, 0x29, 0x24, 0x25, 0x21, 0x21, 0x25, 0x24, 0x29, 0x24, 0x25, 0x25, 
+  0x21, 0x26, 0x23, 0x21, 0x29, 0x24, 0x25, 0x21, 0x24, 0x29, 0x29, 0x24, 0x24, 0x29, 0x24, 0x24, 
+  0x24, 0x25, 0x22, 0x27, 0x27, 0x2a, 0x25, 0x24, 0x25, 0x21, 0x26, 0x26, 0x22, 0x23, 0x26, 0x26, 
+  0x26, 0x2a, 0x28, 0x2a, 0x21, 0x24, 0x29, 0x29, 0x24, 0x25, 0x21, 0x21, 0x25, 0x29, 0x29, 0x24, 
+  0x28, 0x2f, 0x27, 0x26, 0x25, 0x29, 0x24, 0x21, 0x26, 0x26, 0x23, 0x23, 0x26, 0x26, 0x23, 0x23, 
+  0x26, 0x21, 0x25, 0x24, 0x29, 0x29, 0x24, 0x25, 0x21, 0x21, 0x25, 0x25, 0x25, 0x25, 0x25, 0x21, 
+  0x26, 0x26, 0x25, 0x30, 0x31, 0x32, 0x33, 0x33, 0x33, 0x32, 0x33, 0x34, 0x25, 0x24, 0x25, 0x25, 
+  0x21, 0x23, 0x28, 0x2f, 0x27, 0x26, 0x25, 0x29, 0x24, 0x21, 0x26, 0x26, 0x23, 0x23, 0x26, 0x26, 
+  0x23, 0x23, 0x26, 0x21, 0x25, 0x24, 0x29, 0x29, 0x24, 0x25, 0x21, 0x21, 0x25, 0x25, 0x25, 0x25, 
+  0x28, 0x28, 0x2a, 0x25, 0x24, 0x29, 0x24, 0x25, 0x26, 0x26, 0x23, 0x26, 0x26, 0x26, 0x26, 0x26, 
+  0x21, 0x25, 0x29, 0x29, 0x29, 0x24, 0x25, 0x21, 0x26, 0x26, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, 
+  0x25, 0x28, 0x31, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x33, 0x35, 0x24, 0x21, 
+  0x26, 0x22, 0x28, 0x28, 0x2a, 0x25, 0x24, 0x29, 0x24, 0x25, 0x26, 0x26, 0x23, 0x26, 0x26, 0x26, 
+  0x26, 0x26, 0x21, 0x25, 0x29, 0x29, 0x29, 0x24, 0x25, 0x21, 0x26, 0x26, 0x26, 0x21, 0x21, 0x21, 
+  0x2a, 0x2a, 0x26, 0x25, 0x29, 0x29, 0x24, 0x21, 0x26, 0x22, 0x23, 0x23, 0x26, 0x26, 0x25, 0x25, 
+  0x24, 0x29, 0x24, 0x24, 0x25, 0x25, 0x21, 0x26, 0x26, 0x26, 0x21, 0x21, 0x25, 0x21, 0x21, 0x29, 
+  0x34, 0x33, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x31, 0x36, 0x33, 0x37, 0x27, 
+  0x21, 0x23, 0x2a, 0x2a, 0x26, 0x25, 0x29, 0x29, 0x24, 0x21, 0x26, 0x22, 0x23, 0x23, 0x26, 0x26, 
+  0x25, 0x25, 0x24, 0x29, 0x24, 0x24, 0x24, 0x25, 0x26, 0x26, 0x26, 0x26, 0x25, 0x21, 0x25, 0x25, 
+  0x26, 0x26, 0x21, 0x25, 0x24, 0x24, 0x25, 0x26, 0x22, 0x2a, 0x22, 0x26, 0x21, 0x21, 0x24, 0x24, 
+  0x24, 0x24, 0x24, 0x24, 0x25, 0x21, 0x21, 0x21, 0x21, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25, 0x38, 
+  0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x33, 0x39, 0x30, 0x34, 0x31, 0x32, 
+  0x3a, 0x25, 0x26, 0x26, 0x21, 0x25, 0x24, 0x24, 0x25, 0x26, 0x22, 0x2a, 0x22, 0x26, 0x21, 0x21, 
+  0x24, 0x24, 0x24, 0x24, 0x24, 0x25, 0x25, 0x25, 0x21, 0x26, 0x21, 0x21, 0x25, 0x25, 0x25, 0x25, 
+  0x21, 0x22, 0x26, 0x25, 0x24, 0x24, 0x21, 0x23, 0x2a, 0x28, 0x22, 0x26, 0x21, 0x24, 0x24, 0x24, 
+  0x25, 0x25, 0x25, 0x25, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, 0x24, 0x33, 
+  0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x34, 0x27, 0x38, 0x39, 0x37, 
+  0x32, 0x2a, 0x21, 0x22, 0x26, 0x25, 0x24, 0x24, 0x21, 0x23, 0x2a, 0x28, 0x22, 0x26, 0x21, 0x24, 
+  0x24, 0x24, 0x25, 0x21, 0x25, 0x25, 0x21, 0x21, 0x21, 0x21, 0x21, 0x25, 0x21, 0x21, 0x21, 0x21, 
+  0x21, 0x22, 0x26, 0x25, 0x29, 0x29, 0x25, 0x22, 0x28, 0x2a, 0x26, 0x21, 0x25, 0x29, 0x29, 0x24, 
+  0x21, 0x21, 0x21, 0x25, 0x25, 0x21, 0x26, 0x26, 0x23, 0x23, 0x23, 0x26, 0x23, 0x26, 0x27, 0x32, 
+  0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x33, 0x34, 0x30, 0x35, 0x3b, 0x31, 
+  0x32, 0x31, 0x29, 0x2a, 0x26, 0x25, 0x29, 0x29, 0x25, 0x22, 0x28, 0x2a, 0x26, 0x21, 0x25, 0x29, 
+  0x29, 0x24, 0x25, 0x21, 0x21, 0x25, 0x25, 0x21, 0x21, 0x26, 0x22, 0x23, 0x23, 0x23, 0x23, 0x26, 
+  0x29, 0x26, 0x21, 0x24, 0x29, 0x24, 0x26, 0x2a, 0x28, 0x26, 0x21, 0x24, 0x24, 0x24, 0x24, 0x21, 
+  0x26, 0x26, 0x26, 0x21, 0x26, 0x26, 0x23, 0x22, 0x2a, 0x22, 0x23, 0x26, 0x26, 0x24, 0x3c, 0x32, 
+  0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x33, 0x3c, 0x3d, 0x33, 0x32, 0x32, 
+  0x33, 0x33, 0x2e, 0x26, 0x25, 0x24, 0x29, 0x24, 0x26, 0x2a, 0x28, 0x26, 0x21, 0x24, 0x24, 0x24, 
+  0x24, 0x21, 0x26, 0x26, 0x21, 0x21, 0x26, 0x26, 0x22, 0x22, 0x22, 0x22, 0x23, 0x26, 0x26, 0x26, 
+  0x29, 0x25, 0x24, 0x29, 0x29, 0x24, 0x23, 0x2a, 0x2a, 0x21, 0x25, 0x24, 0x24, 0x25, 0x25, 0x26, 
+  0x23, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x21, 0x25, 0x21, 0x25, 0x29, 0x32, 0x32, 
+  0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 
+  0x32, 0x32, 0x31, 0x29, 0x24, 0x29, 0x29, 0x24, 0x23, 0x2a, 0x2a, 0x21, 0x25, 0x24, 0x24, 0x25, 
+  0x25, 0x26, 0x23, 0x23, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x21, 0x25, 0x25, 0x25, 0x25, 
+  0x29, 0x24, 0x24, 0x24, 0x24, 0x26, 0x2a, 0x28, 0x23, 0x21, 0x24, 0x24, 0x25, 0x21, 0x23, 0x26, 
+  0x22, 0x23, 0x26, 0x26, 0x26, 0x26, 0x21, 0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x21, 0x32, 0x32, 
+  0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x33, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 
+  0x32, 0x32, 0x33, 0x21, 0x24, 0x24, 0x24, 0x26, 0x2a, 0x28, 0x23, 0x21, 0x24, 0x24, 0x25, 0x21, 
+  0x23, 0x23, 0x22, 0x23, 0x26, 0x26, 0x26, 0x26, 0x21, 0x25, 0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 
+  0x25, 0x25, 0x25, 0x21, 0x21, 0x23, 0x2a, 0x2a, 0x21, 0x25, 0x25, 0x21, 0x23, 0x2a, 0x22, 0x23, 
+  0x23, 0x26, 0x26, 0x23, 0x26, 0x26, 0x25, 0x29, 0x29, 0x29, 0x29, 0x24, 0x25, 0x2a, 0x32, 0x32, 
+  0x33, 0x37, 0x3c, 0x37, 0x32, 0x32, 0x32, 0x32, 0x32, 0x33, 0x33, 0x37, 0x3b, 0x3c, 0x32, 0x32, 
+  0x32, 0x32, 0x32, 0x30, 0x25, 0x21, 0x21, 0x23, 0x2a, 0x2a, 0x21, 0x25, 0x25, 0x21, 0x23, 0x22, 
+  0x22, 0x23, 0x26, 0x23, 0x26, 0x23, 0x26, 0x21, 0x25, 0x29, 0x29, 0x29, 0x29, 0x24, 0x25, 0x25, 
+  0x24, 0x21, 0x21, 0x26, 0x23, 0x2a, 0x22, 0x26, 0x25, 0x25, 0x25, 0x26, 0x2a, 0x2a, 0x26, 0x21, 
+  0x21, 0x23, 0x22, 0x22, 0x22, 0x21, 0x25, 0x24, 0x29, 0x29, 0x25, 0x25, 0x21, 0x2a, 0x32, 0x32, 
+  0x31, 0x3b, 0x36, 0x3b, 0x33, 0x32, 0x32, 0x32, 0x33, 0x34, 0x3e, 0x3e, 0x3b, 0x39, 0x31, 0x32, 
+  0x32, 0x32, 0x32, 0x35, 0x21, 0x26, 0x23, 0x2a, 0x22, 0x26, 0x25, 0x25, 0x25, 0x26, 0x2a, 0x2a, 
+  0x26, 0x21, 0x26, 0x26, 0x22, 0x22, 0x22, 0x26, 0x25, 0x24, 0x29, 0x24, 0x25, 0x25, 0x21, 0x21, 
+  0x24, 0x21, 0x26, 0x23, 0x22, 0x2a, 0x23, 0x21, 0x24, 0x21, 0x21, 0x23, 0x22, 0x23, 0x21, 0x25, 
+  0x21, 0x2a, 0x2a, 0x22, 0x26, 0x25, 0x24, 0x24, 0x25, 0x25, 0x26, 0x23, 0x26, 0x22, 0x32, 0x36, 
+  0x22, 0x2b, 0x2a, 0x3c, 0x37, 0x32, 0x32, 0x33, 0x30, 0x26, 0x24, 0x2c, 0x29, 0x39, 0x37, 0x32, 
+  0x32, 0x32, 0x33, 0x39, 0x26, 0x23, 0x22, 0x2a, 0x23, 0x21, 0x24, 0x21, 0x21, 0x23, 0x2a, 0x23, 
+  0x21, 0x24, 0x21, 0x2a, 0x2a, 0x23, 0x26, 0x25, 0x24, 0x24, 0x24, 0x21, 0x26, 0x26, 0x26, 0x21, 
+  0x25, 0x26, 0x22, 0x2a, 0x28, 0x22, 0x21, 0x25, 0x25, 0x21, 0x23, 0x22, 0x26, 0x21, 0x24, 0x24, 
+  0x21, 0x22, 0x22, 0x21, 0x24, 0x29, 0x29, 0x2b, 0x24, 0x21, 0x26, 0x23, 0x26, 0x23, 0x32, 0x3a, 
+  0x20, 0x3f, 0x3f, 0x22, 0x32, 0x32, 0x32, 0x35, 0x2d, 0x40, 0x40, 0x40, 0x3f, 0x2a, 0x33, 0x32, 
+  0x32, 0x32, 0x32, 0x3b, 0x22, 0x2a, 0x28, 0x22, 0x21, 0x25, 0x25, 0x21, 0x23, 0x22, 0x26, 0x21, 
+  0x24, 0x25, 0x26, 0x22, 0x22, 0x21, 0x24, 0x29, 0x29, 0x2b, 0x24, 0x21, 0x26, 0x23, 0x26, 0x26, 
+  0x25, 0x26, 0x2a, 0x2a, 0x28, 0x22, 0x21, 0x25, 0x25, 0x26, 0x23, 0x23, 0x21, 0x25, 0x25, 0x25, 
+  0x26, 0x26, 0x21, 0x24, 0x2b, 0x20, 0x2b, 0x29, 0x21, 0x26, 0x22, 0x23, 0x26, 0x21, 0x33, 0x21, 
+  0x25, 0x30, 0x2b, 0x40, 0x36, 0x32, 0x32, 0x27, 0x41, 0x29, 0x3d, 0x30, 0x2c, 0x40, 0x3b, 0x32, 
+  0x32, 0x32, 0x32, 0x37, 0x2a, 0x2a, 0x28, 0x22, 0x21, 0x25, 0x25, 0x26, 0x26, 0x26, 0x21, 0x25, 
+  0x24, 0x25, 0x26, 0x23, 0x21, 0x24, 0x2b, 0x20, 0x2b, 0x29, 0x25, 0x26, 0x22, 0x23, 0x21, 0x21, 
+  0x21, 0x26, 0x2a, 0x28, 0x2a, 0x26, 0x25, 0x24, 0x25, 0x26, 0x23, 0x26, 0x25, 0x21, 0x25, 0x21, 
+  0x21, 0x21, 0x24, 0x2b, 0x20, 0x2c, 0x29, 0x21, 0x2a, 0x28, 0x28, 0x2a, 0x26, 0x26, 0x32, 0x20, 
+  0x42, 0x34, 0x3a, 0x43, 0x34, 0x44, 0x39, 0x28, 0x41, 0x34, 0x33, 0x3a, 0x38, 0x45, 0x46, 0x32, 
+  0x32, 0x32, 0x32, 0x37, 0x2a, 0x28, 0x2a, 0x26, 0x25, 0x24, 0x25, 0x26, 0x22, 0x26, 0x25, 0x21, 
+  0x25, 0x21, 0x21, 0x25, 0x24, 0x2b, 0x20, 0x20, 0x29, 0x26, 0x2a, 0x28, 0x28, 0x2a, 0x23, 0x26, 
+  0x26, 0x23, 0x2a, 0x28, 0x2a, 0x21, 0x24, 0x24, 0x21, 0x26, 0x26, 0x21, 0x25, 0x21, 0x21, 0x21, 
+  0x21, 0x24, 0x2b, 0x2c, 0x2c, 0x29, 0x26, 0x28, 0x2e, 0x2e, 0x27, 0x2a, 0x26, 0x21, 0x32, 0x2c, 
+  0x3c, 0x37, 0x42, 0x2d, 0x47, 0x48, 0x36, 0x49, 0x40, 0x37, 0x32, 0x33, 0x3b, 0x41, 0x2f, 0x32, 
+  0x32, 0x32, 0x32, 0x3d, 0x2a, 0x28, 0x2a, 0x21, 0x24, 0x24, 0x21, 0x26, 0x26, 0x21, 0x25, 0x21, 
+  0x21, 0x21, 0x21, 0x24, 0x2b, 0x20, 0x2c, 0x29, 0x26, 0x28, 0x2e, 0x2e, 0x27, 0x2a, 0x26, 0x26, 
+  0x28, 0x2a, 0x28, 0x27, 0x2a, 0x21, 0x25, 0x25, 0x21, 0x23, 0x21, 0x25, 0x25, 0x24, 0x25, 0x25, 
+  0x24, 0x29, 0x2b, 0x2b, 0x24, 0x23, 0x27, 0x3e, 0x2e, 0x27, 0x2a, 0x26, 0x21, 0x24, 0x32, 0x25, 
+  0x46, 0x33, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 0x50, 0x51, 0x32, 0x33, 0x3a, 0x41, 0x30, 0x32, 
+  0x32, 0x32, 0x32, 0x36, 0x28, 0x27, 0x2a, 0x21, 0x24, 0x25, 0x26, 0x23, 0x21, 0x25, 0x25, 0x24, 
+  0x25, 0x25, 0x24, 0x29, 0x2b, 0x2b, 0x24, 0x23, 0x28, 0x3e, 0x2f, 0x27, 0x2a, 0x26, 0x21, 0x21, 
+  0x27, 0x2a, 0x22, 0x28, 0x2a, 0x21, 0x24, 0x25, 0x26, 0x26, 0x25, 0x24, 0x24, 0x24, 0x24, 0x25, 
+  0x24, 0x2b, 0x2c, 0x29, 0x26, 0x27, 0x3e, 0x3e, 0x27, 0x2a, 0x26, 0x21, 0x25, 0x24, 0x32, 0x3e, 
+  0x52, 0x53, 0x54, 0x55, 0x56, 0x56, 0x57, 0x4c, 0x58, 0x59, 0x5a, 0x5b, 0x52, 0x5c, 0x36, 0x32, 
+  0x32, 0x32, 0x32, 0x37, 0x26, 0x28, 0x2a, 0x21, 0x24, 0x24, 0x26, 0x23, 0x25, 0x24, 0x24, 0x24, 
+  0x24, 0x25, 0x24, 0x2b, 0x2b, 0x29, 0x26, 0x27, 0x3e, 0x3e, 0x27, 0x2a, 0x26, 0x21, 0x25, 0x25, 
+  0x21, 0x21, 0x26, 0x22, 0x23, 0x25, 0x24, 0x24, 0x26, 0x26, 0x25, 0x29, 0x29, 0x24, 0x24, 0x25, 
+  0x29, 0x2b, 0x2b, 0x24, 0x2a, 0x3e, 0x38, 0x2e, 0x2a, 0x26, 0x21, 0x25, 0x24, 0x29, 0x32, 0x3d, 
+  0x5d, 0x5e, 0x5f, 0x60, 0x61, 0x62, 0x58, 0x63, 0x64, 0x65, 0x58, 0x66, 0x67, 0x68, 0x69, 0x33, 
+  0x32, 0x32, 0x32, 0x33, 0x25, 0x22, 0x22, 0x21, 0x24, 0x25, 0x26, 0x26, 0x25, 0x29, 0x29, 0x29, 
+  0x25, 0x25, 0x29, 0x2c, 0x2b, 0x25, 0x2a, 0x3e, 0x38, 0x2e, 0x2a, 0x26, 0x21, 0x24, 0x25, 0x24, 
+  0x20, 0x24, 0x21, 0x23, 0x23, 0x25, 0x24, 0x24, 0x21, 0x21, 0x24, 0x29, 0x29, 0x24, 0x25, 0x21, 
+  0x29, 0x2b, 0x29, 0x21, 0x28, 0x3e, 0x2e, 0x2a, 0x26, 0x21, 0x24, 0x24, 0x24, 0x29, 0x32, 0x6a, 
+  0x6b, 0x6c, 0x6d, 0x56, 0x62, 0x58, 0x63, 0x64, 0x64, 0x6e, 0x6e, 0x65, 0x58, 0x6f, 0x5b, 0x32, 
+  0x32, 0x32, 0x32, 0x33, 0x25, 0x23, 0x26, 0x25, 0x24, 0x24, 0x21, 0x21, 0x24, 0x29, 0x29, 0x24, 
+  0x25, 0x21, 0x24, 0x2b, 0x2b, 0x21, 0x27, 0x2f, 0x2e, 0x2a, 0x26, 0x21, 0x25, 0x24, 0x24, 0x24, 
+  0x70, 0x21, 0x26, 0x22, 0x26, 0x25, 0x29, 0x24, 0x21, 0x21, 0x24, 0x29, 0x29, 0x25, 0x21, 0x25, 
+  0x24, 0x2b, 0x24, 0x26, 0x28, 0x27, 0x28, 0x23, 0x26, 0x21, 0x25, 0x24, 0x29, 0x29, 0x71, 0x72, 
+  0x73, 0x5f, 0x74, 0x56, 0x62, 0x58, 0x64, 0x63, 0x6e, 0x6e, 0x75, 0x57, 0x76, 0x77, 0x78, 0x32, 
+  0x32, 0x32, 0x32, 0x32, 0x3e, 0x23, 0x26, 0x25, 0x29, 0x24, 0x21, 0x21, 0x24, 0x29, 0x24, 0x25, 
+  0x21, 0x25, 0x29, 0x2b, 0x24, 0x26, 0x28, 0x2e, 0x2a, 0x23, 0x26, 0x21, 0x24, 0x29, 0x29, 0x24, 
+  0x79, 0x28, 0x28, 0x22, 0x26, 0x25, 0x24, 0x24, 0x26, 0x21, 0x24, 0x24, 0x24, 0x25, 0x21, 0x25, 
+  0x24, 0x29, 0x25, 0x2a, 0x28, 0x28, 0x28, 0x28, 0x2a, 0x26, 0x24, 0x29, 0x24, 0x29, 0x33, 0x7a, 
+  0x7b, 0x7c, 0x56, 0x7d, 0x58, 0x63, 0x64, 0x75, 0x63, 0x7e, 0x7f, 0x7f, 0x80, 0x55, 0x81, 0x32, 
+  0x32, 0x33, 0x32, 0x32, 0x3c, 0x25, 0x26, 0x25, 0x29, 0x24, 0x21, 0x21, 0x25, 0x29, 0x24, 0x25, 
+  0x21, 0x25, 0x24, 0x29, 0x25, 0x22, 0x28, 0x27, 0x28, 0x28, 0x2a, 0x26, 0x25, 0x29, 0x24, 0x21, 
+  0x21, 0x3e, 0x27, 0x22, 0x21, 0x25, 0x24, 0x25, 0x21, 0x26, 0x21, 0x24, 0x29, 0x24, 0x25, 0x25, 
+  0x24, 0x24, 0x26, 0x2a, 0x28, 0x27, 0x28, 0x28, 0x2a, 0x25, 0x29, 0x29, 0x25, 0x24, 0x37, 0x47, 
+  0x82, 0x55, 0x56, 0x62, 0x63, 0x75, 0x75, 0x61, 0x76, 0x83, 0x84, 0x80, 0x6c, 0x85, 0x69, 0x32, 
+  0x3c, 0x3e, 0x3b, 0x33, 0x32, 0x21, 0x21, 0x25, 0x24, 0x25, 0x26, 0x26, 0x25, 0x24, 0x29, 0x24, 
+  0x25, 0x21, 0x24, 0x25, 0x26, 0x2a, 0x28, 0x28, 0x28, 0x28, 0x2a, 0x21, 0x29, 0x29, 0x25, 0x21, 
+  0x2a, 0x3e, 0x27, 0x26, 0x21, 0x25, 0x25, 0x25, 0x21, 0x21, 0x21, 0x24, 0x24, 0x24, 0x21, 0x26, 
+  0x21, 0x21, 0x26, 0x2a, 0x2a, 0x2a, 0x28, 0x2a, 0x26, 0x29, 0x2b, 0x29, 0x21, 0x25, 0x32, 0x37, 
+  0x86, 0x72, 0x87, 0x7f, 0x7f, 0x7b, 0x83, 0x88, 0x73, 0x84, 0x89, 0x8a, 0x8b, 0x8c, 0x30, 0x32, 
+  0x33, 0x38, 0x2a, 0x34, 0x33, 0x2f, 0x21, 0x25, 0x25, 0x24, 0x21, 0x26, 0x21, 0x24, 0x24, 0x24, 
+  0x25, 0x26, 0x21, 0x25, 0x26, 0x2a, 0x2a, 0x2a, 0x28, 0x2a, 0x26, 0x29, 0x2b, 0x2b, 0x21, 0x26, 
+  0x28, 0x27, 0x2a, 0x21, 0x25, 0x25, 0x25, 0x24, 0x25, 0x21, 0x25, 0x24, 0x29, 0x24, 0x25, 0x26, 
+  0x26, 0x21, 0x21, 0x26, 0x26, 0x26, 0x26, 0x21, 0x24, 0x2b, 0x8d, 0x29, 0x26, 0x29, 0x32, 0x3c, 
+  0x29, 0x8e, 0x8f, 0x76, 0x77, 0x90, 0x89, 0x89, 0x91, 0x5e, 0x8e, 0x92, 0x8d, 0x20, 0x22, 0x33, 
+  0x33, 0x3b, 0x27, 0x3a, 0x32, 0x37, 0x29, 0x25, 0x25, 0x24, 0x25, 0x21, 0x25, 0x24, 0x29, 0x24, 
+  0x21, 0x21, 0x26, 0x21, 0x26, 0x26, 0x26, 0x26, 0x26, 0x21, 0x29, 0x2b, 0x20, 0x29, 0x26, 0x23, 
+  0x26, 0x26, 0x26, 0x25, 0x25, 0x25, 0x25, 0x24, 0x25, 0x25, 0x25, 0x24, 0x24, 0x25, 0x25, 0x21, 
+  0x26, 0x21, 0x21, 0x25, 0x25, 0x25, 0x25, 0x24, 0x2b, 0x2c, 0x2c, 0x24, 0x26, 0x26, 0x32, 0x3c, 
+  0x2b, 0x93, 0x94, 0x68, 0x95, 0x96, 0x87, 0x87, 0x4b, 0x97, 0x2b, 0x79, 0x40, 0x45, 0x3f, 0x39, 
+  0x32, 0x33, 0x31, 0x33, 0x32, 0x32, 0x42, 0x24, 0x25, 0x24, 0x24, 0x25, 0x25, 0x24, 0x24, 0x24, 
+  0x21, 0x21, 0x26, 0x21, 0x21, 0x25, 0x25, 0x25, 0x25, 0x24, 0x2b, 0x20, 0x2b, 0x24, 0x26, 0x26, 
+  0x21, 0x21, 0x21, 0x21, 0x25, 0x25, 0x25, 0x24, 0x24, 0x21, 0x21, 0x25, 0x25, 0x25, 0x25, 0x21, 
+  0x26, 0x26, 0x25, 0x25, 0x24, 0x24, 0x29, 0x29, 0x2b, 0x2b, 0x24, 0x26, 0x25, 0x3c, 0x32, 0x34, 
+  0x3f, 0x8d, 0x2b, 0x8c, 0x98, 0x99, 0x9a, 0x9b, 0x2b, 0x2c, 0x2d, 0x43, 0x45, 0x45, 0x41, 0x25, 
+  0x32, 0x32, 0x33, 0x32, 0x32, 0x32, 0x33, 0x21, 0x25, 0x24, 0x25, 0x21, 0x21, 0x25, 0x25, 0x25, 
+  0x25, 0x21, 0x26, 0x26, 0x25, 0x25, 0x24, 0x24, 0x29, 0x29, 0x2b, 0x2b, 0x24, 0x26, 0x23, 0x26, 
+  0x21, 0x26, 0x21, 0x21, 0x25, 0x25, 0x21, 0x25, 0x25, 0x21, 0x21, 0x21, 0x21, 0x21, 0x25, 0x21, 
+  0x26, 0x21, 0x25, 0x25, 0x24, 0x24, 0x29, 0x24, 0x24, 0x25, 0x26, 0x26, 0x3e, 0x33, 0x37, 0x2c, 
+  0x45, 0x3f, 0x2b, 0x2b, 0x2b, 0x2b, 0x2b, 0x2b, 0x20, 0x3f, 0x43, 0x45, 0x45, 0x45, 0x45, 0x41, 
+  0x34, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x3c, 0x29, 0x25, 0x25, 0x21, 0x21, 0x21, 0x21, 0x25, 
+  0x21, 0x21, 0x26, 0x21, 0x25, 0x25, 0x24, 0x24, 0x24, 0x24, 0x24, 0x25, 0x21, 0x22, 0x22, 0x26, 
+  0x22, 0x23, 0x26, 0x21, 0x21, 0x21, 0x21, 0x21, 0x25, 0x25, 0x21, 0x26, 0x21, 0x21, 0x21, 0x26, 
+  0x26, 0x23, 0x26, 0x25, 0x21, 0x21, 0x21, 0x21, 0x26, 0x22, 0x22, 0x22, 0x3d, 0x37, 0x3e, 0x45, 
+  0x45, 0x41, 0x79, 0x2b, 0x2b, 0x2b, 0x2c, 0x70, 0x43, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 
+  0x29, 0x32, 0x32, 0x32, 0x32, 0x32, 0x33, 0x33, 0x38, 0x25, 0x25, 0x25, 0x21, 0x26, 0x21, 0x21, 
+  0x21, 0x26, 0x26, 0x23, 0x26, 0x21, 0x25, 0x21, 0x21, 0x21, 0x26, 0x22, 0x2a, 0x2a, 0x2a, 0x22, 
+  0x2a, 0x2a, 0x23, 0x26, 0x26, 0x21, 0x21, 0x21, 0x25, 0x21, 0x21, 0x26, 0x26, 0x26, 0x26, 0x23, 
+  0x2a, 0x2a, 0x2a, 0x23, 0x22, 0x22, 0x2a, 0x28, 0x28, 0x28, 0x25, 0x31, 0x32, 0x3d, 0x3f, 0x45, 
+  0x45, 0x45, 0x43, 0x52, 0x79, 0x2d, 0x3f, 0x41, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 
+  0x41, 0x39, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x33, 0x25, 0x21, 0x21, 0x21, 0x26, 0x26, 0x26, 
+  0x26, 0x23, 0x2a, 0x2a, 0x22, 0x22, 0x22, 0x22, 0x2a, 0x28, 0x28, 0x28, 0x2a, 0x2a, 0x2a, 0x2a, 
+  0x2a, 0x26, 0x26, 0x26, 0x21, 0x21, 0x21, 0x21, 0x25, 0x25, 0x21, 0x26, 0x26, 0x26, 0x26, 0x26, 
+  0x22, 0x2a, 0x22, 0x26, 0x26, 0x23, 0x2a, 0x28, 0x28, 0x21, 0x3c, 0x32, 0x33, 0x2a, 0x45, 0x45, 
+  0x45, 0x45, 0x45, 0x45, 0x41, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 
+  0x45, 0x27, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x3d, 0x2b, 0x25, 0x21, 0x26, 0x26, 0x26, 
+  0x26, 0x26, 0x22, 0x2a, 0x2a, 0x26, 0x26, 0x23, 0x2a, 0x28, 0x28, 0x28, 0x2a, 0x22, 0x2a, 0x28, 
+  0x26, 0x25, 0x25, 0x25, 0x21, 0x25, 0x21, 0x21, 0x25, 0x25, 0x25, 0x26, 0x26, 0x26, 0x26, 0x26, 
+  0x23, 0x23, 0x21, 0x25, 0x25, 0x21, 0x26, 0x22, 0x26, 0x3a, 0x32, 0x32, 0x3d, 0x3f, 0x45, 0x45, 
+  0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 
+  0x45, 0x29, 0x33, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x3b, 0x2b, 0x21, 0x21, 0x26, 0x26, 
+  0x26, 0x26, 0x23, 0x26, 0x21, 0x25, 0x25, 0x21, 0x26, 0x22, 0x23, 0x23, 0x23, 0x23, 0x22, 0x2a, 
+  0x25, 0x29, 0x29, 0x25, 0x25, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, 0x25, 0x21, 0x21, 0x21, 0x21, 
+  0x21, 0x21, 0x25, 0x24, 0x25, 0x21, 0x26, 0x21, 0x2e, 0x33, 0x32, 0x32, 0x30, 0x3f, 0x45, 0x45, 
+  0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 
+  0x43, 0x3f, 0x33, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x33, 0x3b, 0x29, 0x21, 0x21, 0x21, 
+  0x21, 0x21, 0x21, 0x21, 0x25, 0x24, 0x25, 0x21, 0x26, 0x26, 0x21, 0x21, 0x21, 0x26, 0x26, 0x26, 
+  0x24, 0x29, 0x29, 0x24, 0x25, 0x25, 0x21, 0x25, 0x25, 0x25, 0x21, 0x25, 0x21, 0x21, 0x26, 0x21, 
+  0x21, 0x25, 0x25, 0x25, 0x21, 0x23, 0x23, 0x28, 0x32, 0x32, 0x32, 0x32, 0x2e, 0x2d, 0x41, 0x45, 
+  0x45, 0x45, 0x45, 0x43, 0x40, 0x40, 0x45, 0x45, 0x45, 0x45, 0x45, 0x43, 0x40, 0x40, 0x3f, 0x70, 
+  0x70, 0x40, 0x42, 0x32, 0x32, 0x33, 0x32, 0x32, 0x32, 0x32, 0x32, 0x33, 0x9c, 0x24, 0x21, 0x21, 
+  0x21, 0x26, 0x21, 0x25, 0x24, 0x25, 0x21, 0x23, 0x23, 0x26, 0x21, 0x21, 0x21, 0x26, 0x26, 0x21, 
+  0x2b, 0x2b, 0x2b, 0x29, 0x24, 0x25, 0x25, 0x21, 0x25, 0x21, 0x25, 0x21, 0x21, 0x21, 0x21, 0x21, 
+  0x21, 0x21, 0x21, 0x26, 0x2a, 0x2a, 0x25, 0x31, 0x33, 0x32, 0x32, 0x31, 0x28, 0x29, 0x9d, 0x40, 
+  0x45, 0x45, 0x45, 0x43, 0x40, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x3f, 0x70, 0x79, 0x20, 0x2c, 
+  0x2c, 0x79, 0x2b, 0x36, 0x32, 0x3d, 0x33, 0x32, 0x32, 0x32, 0x32, 0x32, 0x33, 0x24, 0x21, 0x21, 
+  0x21, 0x21, 0x21, 0x21, 0x21, 0x26, 0x2a, 0x2a, 0x2a, 0x22, 0x23, 0x23, 0x23, 0x21, 0x21, 0x25, 
+  0x79, 0x2b, 0x29, 0x29, 0x24, 0x24, 0x24, 0x25, 0x25, 0x25, 0x25, 0x21, 0x26, 0x26, 0x26, 0x21, 
+  0x21, 0x25, 0x21, 0x26, 0x23, 0x23, 0x21, 0x33, 0x32, 0x32, 0x33, 0x3c, 0x25, 0x5c, 0x45, 0x45, 
+  0x45, 0x45, 0x45, 0x41, 0x41, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x43, 0x40, 0x52, 
+  0x20, 0x2c, 0x52, 0x21, 0x32, 0x36, 0x3b, 0x3d, 0x32, 0x32, 0x32, 0x32, 0x32, 0x3a, 0x21, 0x26, 
+  0x26, 0x26, 0x21, 0x21, 0x21, 0x26, 0x23, 0x23, 0x26, 0x26, 0x23, 0x23, 0x23, 0x26, 0x21, 0x21, 
+  0x9d, 0x24, 0x24, 0x24, 0x24, 0x24, 0x25, 0x25, 0x24, 0x21, 0x21, 0x21, 0x26, 0x23, 0x23, 0x26, 
+  0x21, 0x21, 0x21, 0x21, 0x21, 0x26, 0x3a, 0x32, 0x3d, 0x3d, 0x37, 0x27, 0x40, 0x45, 0x45, 0x45, 
+  0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 
+  0x43, 0x52, 0x20, 0x3f, 0x9c, 0x32, 0x33, 0x3c, 0x3b, 0x32, 0x32, 0x32, 0x33, 0x33, 0x25, 0x23, 
+  0x23, 0x21, 0x21, 0x25, 0x21, 0x21, 0x26, 0x21, 0x26, 0x26, 0x26, 0x26, 0x26, 0x21, 0x26, 0x21, 
+  0x2b, 0x26, 0x26, 0x26, 0x21, 0x21, 0x25, 0x21, 0x25, 0x21, 0x21, 0x26, 0x26, 0x26, 0x26, 0x21, 
+  0x21, 0x21, 0x21, 0x21, 0x21, 0x24, 0x36, 0x32, 0x42, 0x32, 0x3d, 0x3f, 0x45, 0x45, 0x45, 0x45, 
+  0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 
+  0x45, 0x45, 0x3f, 0x2d, 0x2b, 0x32, 0x33, 0x33, 0x3b, 0x36, 0x32, 0x32, 0x32, 0x33, 0x38, 0x26, 
+  0x26, 0x26, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, 0x26, 0x26, 0x21, 0x21, 
+  0x25, 0x26, 0x23, 0x26, 0x23, 0x26, 0x26, 0x21, 0x21, 0x21, 0x21, 0x25, 0x25, 0x25, 0x25, 0x25, 
+  0x25, 0x21, 0x21, 0x26, 0x21, 0x25, 0x32, 0x3c, 0x3d, 0x32, 0x2a, 0x45, 0x45, 0x45, 0x45, 0x45, 
+  0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 
+  0x45, 0x45, 0x45, 0x41, 0x3f, 0x35, 0x37, 0x39, 0x3c, 0x42, 0x33, 0x32, 0x32, 0x32, 0x37, 0x29, 
+  0x25, 0x25, 0x21, 0x21, 0x21, 0x26, 0x21, 0x25, 0x21, 0x21, 0x21, 0x21, 0x21, 0x25, 0x21, 0x25, 
+  0x24, 0x26, 0x26, 0x26, 0x26, 0x21, 0x21, 0x26, 0x26, 0x26, 0x21, 0x21, 0x25, 0x25, 0x24, 0x25, 
+  0x24, 0x25, 0x25, 0x21, 0x25, 0x3a, 0x33, 0x34, 0x32, 0x3c, 0x43, 0x45, 0x45, 0x45, 0x45, 0x45, 
+  0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 
+  0x45, 0x45, 0x45, 0x45, 0x45, 0x23, 0x36, 0x9c, 0x42, 0x36, 0x3b, 0x32, 0x32, 0x32, 0x32, 0x22, 
+  0x24, 0x24, 0x24, 0x25, 0x25, 0x21, 0x21, 0x25, 0x25, 0x21, 0x21, 0x21, 0x21, 0x25, 0x25, 0x25, 
+  0x29, 0x25, 0x26, 0x26, 0x21, 0x25, 0x25, 0x25, 0x26, 0x23, 0x26, 0x25, 0x25, 0x24, 0x25, 0x24, 
+  0x24, 0x24, 0x25, 0x25, 0x2b, 0x37, 0x3c, 0x31, 0x33, 0x23, 0x45, 0x9e, 0x32, 0x32, 0x32, 0x32, 
+  0x30, 0x45, 0x45, 0x45, 0x30, 0x32, 0x32, 0x32, 0x30, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 
+  0x3c, 0x9f, 0xa0, 0x45, 0x45, 0x9d, 0x31, 0x3d, 0x31, 0x32, 0x34, 0x32, 0x32, 0x32, 0x32, 0x42, 
+  0x29, 0x24, 0x24, 0x24, 0x25, 0x24, 0x25, 0x25, 0x25, 0x26, 0x26, 0x26, 0x21, 0x21, 0x21, 0x26, 
+  0x29, 0x21, 0x21, 0x21, 0x25, 0x24, 0x25, 0x25, 0x21, 0x21, 0x21, 0x21, 0x21, 0x25, 0x21, 0x25, 
+  0x25, 0x25, 0x25, 0x21, 0x23, 0x32, 0x42, 0x32, 0x3d, 0x3f, 0x45, 0x45, 0x45, 0x32, 0x32, 0x23, 
+  0x45, 0x45, 0x45, 0x43, 0x45, 0x23, 0x32, 0x20, 0x45, 0x45, 0x30, 0x32, 0x32, 0x45, 0x45, 0x23, 
+  0x32, 0x32, 0xa1, 0x45, 0x45, 0x45, 0x3c, 0x32, 0x32, 0x32, 0x3b, 0x37, 0x32, 0x32, 0x32, 0x33, 
+  0x29, 0x25, 0x25, 0x25, 0x21, 0x21, 0x21, 0x26, 0x21, 0x26, 0x26, 0x23, 0x26, 0x23, 0x23, 0x26, 
+  0x25, 0x26, 0x26, 0x21, 0x25, 0x25, 0x24, 0x21, 0x26, 0x21, 0x26, 0x21, 0x21, 0x21, 0x21, 0x21, 
+  0x26, 0x23, 0x2a, 0x23, 0x42, 0x31, 0x3b, 0x32, 0x2f, 0x45, 0x45, 0x45, 0x45, 0xa1, 0x32, 0x30, 
+  0x45, 0x45, 0x45, 0x43, 0x45, 0x3c, 0xa1, 0x45, 0x45, 0x45, 0x30, 0x32, 0xa1, 0x45, 0x45, 0x45, 
+  0xa1, 0x32, 0x32, 0x45, 0x45, 0x45, 0x35, 0x32, 0x32, 0x32, 0x3d, 0x3c, 0x32, 0x32, 0x32, 0x32, 
+  0x21, 0x21, 0x26, 0x23, 0x22, 0x22, 0x2a, 0x22, 0x22, 0x22, 0x23, 0x23, 0x23, 0x23, 0x26, 0x21, 
+  0x21, 0x26, 0x26, 0x21, 0x21, 0x25, 0x25, 0x25, 0x21, 0x21, 0x26, 0x26, 0x26, 0x21, 0x21, 0x26, 
+  0x22, 0x27, 0x2f, 0x26, 0x32, 0x3b, 0x37, 0x33, 0x2b, 0x45, 0x45, 0x45, 0x45, 0x30, 0x32, 0xa1, 
+  0x45, 0x45, 0x45, 0x40, 0x23, 0x32, 0x20, 0x45, 0x45, 0x45, 0x32, 0x32, 0x30, 0x45, 0x45, 0x45, 
+  0x30, 0x32, 0x32, 0x45, 0x45, 0x45, 0x3e, 0x32, 0x32, 0x32, 0x3d, 0x3d, 0x32, 0x32, 0x32, 0x32, 
+  0x3e, 0x26, 0x22, 0x27, 0x2f, 0x27, 0x28, 0x2a, 0x26, 0x21, 0x21, 0x26, 0x23, 0x26, 0x26, 0x25, 
+  0x25, 0x25, 0x21, 0x21, 0x21, 0x25, 0x25, 0x25, 0x21, 0x25, 0x21, 0x21, 0x21, 0x21, 0x21, 0x26, 
+  0x28, 0x2e, 0x2a, 0x3b, 0x33, 0x3b, 0x33, 0x3d, 0x41, 0x45, 0x45, 0x45, 0x45, 0x9f, 0x32, 0x32, 
+  0x45, 0x45, 0x45, 0x40, 0x3c, 0x9f, 0x45, 0x45, 0x45, 0xa0, 0x32, 0x32, 0x9e, 0x45, 0x45, 0x45, 
+  0x3c, 0x32, 0x9f, 0x45, 0x45, 0x45, 0x27, 0x32, 0x32, 0x32, 0x3d, 0x36, 0x32, 0x32, 0x32, 0x32, 
+  0x34, 0x21, 0x28, 0x2e, 0x2f, 0x27, 0x2a, 0x26, 0x25, 0x24, 0x25, 0x26, 0x22, 0x23, 0x25, 0x29, 
+  0x2b, 0x24, 0x25, 0x21, 0x21, 0x24, 0x25, 0x24, 0x25, 0x25, 0x21, 0x21, 0x21, 0x21, 0x21, 0x26, 
+  0x2a, 0x2e, 0x2a, 0x32, 0x32, 0x39, 0x32, 0x9c, 0x45, 0x45, 0x45, 0x45, 0x45, 0x9e, 0x32, 0x32, 
+  0x45, 0x45, 0x41, 0x28, 0x32, 0xa0, 0x45, 0x45, 0x45, 0x9e, 0x32, 0x32, 0x20, 0x45, 0xa0, 0x30, 
+  0x32, 0xa1, 0xa0, 0x45, 0x45, 0x45, 0x28, 0x32, 0x32, 0x32, 0x3c, 0x33, 0x32, 0x32, 0x32, 0x32, 
+  0x3c, 0x25, 0x28, 0x27, 0x27, 0x22, 0x21, 0x21, 0x24, 0x2b, 0x24, 0x22, 0x28, 0x26, 0x25, 0x29, 
+  0x79, 0x24, 0x21, 0x21, 0x25, 0x25, 0x24, 0x25, 0x21, 0x21, 0x26, 0x26, 0x26, 0x21, 0x25, 0x25, 
+  0x23, 0x21, 0x3c, 0x32, 0x32, 0x34, 0x33, 0x3e, 0x45, 0x45, 0x45, 0x45, 0x45, 0x20, 0x32, 0x32, 
+  0x9e, 0x45, 0xa2, 0xa3, 0x9f, 0x45, 0x45, 0x45, 0x45, 0x9f, 0x32, 0x32, 0x30, 0x30, 0x32, 0x30, 
+  0x9e, 0x45, 0x45, 0x45, 0x45, 0x45, 0x23, 0x32, 0x32, 0x32, 0x3b, 0x32, 0x32, 0x32, 0x32, 0x32, 
+  0x33, 0x29, 0x26, 0x27, 0x28, 0x26, 0x25, 0x24, 0x24, 0x29, 0x21, 0x28, 0x28, 0x26, 0x29, 0x2b, 
+  0x20, 0x21, 0x22, 0x23, 0x25, 0x25, 0x25, 0x25, 0x26, 0x21, 0x23, 0x22, 0x22, 0x21, 0x25, 0x21, 
+  0x22, 0x2a, 0x32, 0x32, 0x36, 0x9c, 0x32, 0x28, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x32, 0x32, 
+  0x9e, 0x45, 0x22, 0x32, 0xa0, 0x45, 0x45, 0x45, 0x45, 0x30, 0x32, 0xa1, 0x9e, 0xa1, 0x32, 0x3c, 
+  0x20, 0x45, 0x45, 0x45, 0x45, 0x45, 0x23, 0x32, 0x32, 0x33, 0x3b, 0x32, 0x32, 0x32, 0x32, 0x32, 
+  0x33, 0x29, 0x23, 0x27, 0x28, 0x26, 0x24, 0x29, 0x29, 0x25, 0x23, 0x27, 0x2a, 0x24, 0x2b, 0x2c, 
+  0x21, 0x27, 0x27, 0x2a, 0x21, 0x24, 0x25, 0x21, 0x26, 0x26, 0x22, 0x22, 0x26, 0x26, 0x26, 0x22, 
+  0x27, 0x38, 0x32, 0x32, 0x31, 0x38, 0x37, 0x23, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x3c, 0x32, 
+  0x30, 0xa0, 0x32, 0x2f, 0x45, 0x45, 0x45, 0x45, 0x45, 0x3c, 0x32, 0x30, 0x45, 0x45, 0xa1, 0x32, 
+  0x3c, 0x45, 0x45, 0x45, 0x45, 0x45, 0x23, 0x32, 0x32, 0x31, 0x36, 0x32, 0x32, 0x32, 0x33, 0x32, 
+  0x32, 0x25, 0x27, 0x2e, 0x2a, 0x25, 0x29, 0x29, 0x24, 0x25, 0x26, 0x23, 0x21, 0x24, 0x2b, 0x29, 
+  0x22, 0x27, 0x27, 0x22, 0x25, 0x24, 0x25, 0x21, 0x26, 0x26, 0x22, 0x22, 0x26, 0x26, 0x26, 0x2a, 
+  0x28, 0x9c, 0x32, 0x33, 0x33, 0x3d, 0x3c, 0x21, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x30, 0x32, 
+  0x30, 0x9f, 0xa4, 0x43, 0x45, 0x45, 0x45, 0x45, 0x45, 0x32, 0x32, 0x23, 0x45, 0x45, 0x9e, 0x32, 
+  0x32, 0x20, 0x45, 0x45, 0x45, 0x45, 0x27, 0x32, 0x37, 0x39, 0x37, 0x31, 0x33, 0x32, 0x32, 0x32, 
+  0x33, 0x23, 0x28, 0x2a, 0x26, 0x24, 0x29, 0x29, 0x24, 0x25, 0x25, 0x21, 0x24, 0x24, 0x29, 0x24, 
+  0x28, 0x2e, 0x27, 0x26, 0x25, 0x29, 0x24, 0x21, 0x26, 0x26, 0x23, 0x23, 0x26, 0x26, 0x23, 0x23, 
+  0x26, 0x2f, 0x37, 0x53, 0x53, 0x37, 0x3c, 0x23, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x9f, 0x32, 
+  0x32, 0x32, 0x22, 0x40, 0x45, 0x45, 0x45, 0x45, 0x9e, 0x32, 0x32, 0x9e, 0x45, 0x45, 0xa0, 0x32, 
+  0x32, 0x9f, 0x45, 0x45, 0x45, 0x45, 0x30, 0x31, 0x3c, 0x31, 0x33, 0x36, 0x3c, 0x3b, 0x3c, 0x32, 
+  0x3a, 0x22, 0x26, 0x21, 0x25, 0x24, 0x29, 0x29, 0x24, 0x21, 0x21, 0x21, 0x25, 0x25, 0x25, 0x25, 
+  0x28, 0x28, 0x2a, 0x25, 0x24, 0x29, 0x24, 0x25, 0x26, 0x26, 0x23, 0x26, 0x26, 0x26, 0x26, 0x26, 
+  0x21, 0xa5, 0xa6, 0x56, 0xa7, 0xa8, 0x48, 0x35, 0x3f, 0x45, 0x45, 0x45, 0x45, 0x45, 0x9e, 0x32, 
+  0x32, 0x3c, 0x41, 0x43, 0x45, 0x45, 0x45, 0x45, 0x23, 0x32, 0x32, 0x45, 0x45, 0x45, 0x45, 0xa1, 
+  0x32, 0x3c, 0x45, 0x45, 0x45, 0x41, 0x51, 0x36, 0x32, 0x32, 0x32, 0x32, 0x32, 0x37, 0x3a, 0x3d, 
+  0x2a, 0x26, 0x21, 0x24, 0x29, 0x29, 0x29, 0x24, 0x25, 0x21, 0x26, 0x26, 0x21, 0x21, 0x21, 0x21, 
+  0x2a, 0x2a, 0x26, 0x25, 0x29, 0x29, 0x24, 0x21, 0x26, 0x22, 0x23, 0x23, 0x26, 0x26, 0x25, 0x25, 
+  0x9d, 0xa9, 0xaa, 0xa7, 0x7d, 0xab, 0x5e, 0x4a, 0x34, 0x52, 0x45, 0x45, 0x45, 0x45, 0x20, 0x32, 
+  0x32, 0x23, 0x43, 0x40, 0x45, 0x45, 0x45, 0x30, 0x3c, 0x32, 0x32, 0x30, 0x23, 0x45, 0x45, 0x20, 
+  0x32, 0x32, 0x3c, 0x30, 0xac, 0x58, 0xad, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x36, 0x42, 0x3c, 
+  0x86, 0x24, 0x24, 0x24, 0x24, 0x24, 0x25, 0x25, 0x21, 0x26, 0x26, 0x26, 0x21, 0x21, 0x25, 0x25, 
+  0x26, 0x23, 0x21, 0x25, 0x24, 0x24, 0x25, 0x26, 0x22, 0x2a, 0x22, 0x26, 0x21, 0x21, 0x2b, 0x79, 
+  0xae, 0x55, 0xaf, 0xab, 0x7d, 0xb0, 0xa7, 0x4f, 0x71, 0x39, 0x20, 0x45, 0x45, 0x45, 0x45, 0x9e, 
+  0x9e, 0x45, 0x41, 0x40, 0x45, 0x45, 0x45, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x20, 0x45, 0x45, 0x45, 
+  0xa0, 0x9e, 0x9e, 0x9e, 0xb1, 0xb2, 0x68, 0xb3, 0x32, 0x32, 0x32, 0x32, 0x32, 0x36, 0x37, 0xb4, 
+  0xce, 0xcf, 0x24, 0x24, 0x24, 0x24, 0x25, 0x21, 0x21, 0x26, 0x21, 0x25, 0x25, 0x25, 0x25, 0x25, 
+  0x21, 0x22, 0x26, 0x25, 0x24, 0x24, 0x21, 0x26, 0x28, 0x28, 0x25, 0x2c, 0xb5, 0xb6, 0xb7, 0xb8, 
+  0x6c, 0xb9, 0xa7, 0xab, 0x7e, 0xa7, 0x56, 0x7d, 0x5a, 0xb3, 0x36, 0x24, 0x45, 0x45, 0x45, 0x45, 
+  0x45, 0x45, 0x41, 0x43, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 
+  0x45, 0x45, 0x45, 0x45, 0xb1, 0x56, 0xb4, 0xb3, 0x32, 0x32, 0x32, 0x32, 0x32, 0xb3, 0xba, 0x60, 
+  0x7e, 0xd0, 0x20, 0x25, 0x21, 0x25, 0x25, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, 
+  0x25, 0x2a, 0x26, 0x25, 0x29, 0x29, 0x25, 0x23, 0x2a, 0x26, 0x50, 0xbb, 0x80, 0x55, 0xbc, 0x80, 
+  0xb9, 0x60, 0xa7, 0xb0, 0xab, 0xab, 0xab, 0xab, 0x57, 0x6a, 0x33, 0x33, 0x2a, 0x45, 0x45, 0x45, 
+  0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 
+  0x45, 0x45, 0x45, 0x43, 0x60, 0x6d, 0x54, 0x48, 0x32, 0x32, 0x32, 0x32, 0xb3, 0xbd, 0x8a, 0x61, 
+  0x56, 0xd1, 0x20, 0x21, 0x21, 0x21, 0x25, 0x21, 0x21, 0x26, 0x23, 0x23, 0x23, 0x23, 0x23, 0x26, 
+  0x24, 0x26, 0x21, 0x24, 0x29, 0x24, 0x26, 0x28, 0x28, 0xbe, 0xbb, 0x7c, 0x56, 0x74, 0x74, 0x74, 
+  0xbf, 0xa7, 0xb0, 0xab, 0xab, 0xab, 0xab, 0xab, 0x7e, 0xc0, 0x71, 0x32, 0x32, 0x3e, 0x45, 0x45, 
+  0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 
+  0x45, 0x45, 0x52, 0x80, 0x74, 0x6d, 0x89, 0xc1, 0x6a, 0xc2, 0x4a, 0x6a, 0xc3, 0x76, 0x6d, 0x74, 
+  0xa7, 0xd2, 0x24, 0x25, 0x21, 0x21, 0x26, 0x26, 0x22, 0x22, 0x2a, 0x22, 0x23, 0x26, 0x26, 0x26, 
+  0x2b, 0x25, 0x24, 0x29, 0x29, 0x24, 0x26, 0x28, 0x2a, 0xc4, 0x84, 0x6d, 0x56, 0xab, 0xab, 0xab, 
+  0xa7, 0xb0, 0xab, 0xab, 0xb0, 0xab, 0xab, 0xab, 0x7e, 0x7d, 0xc5, 0x32, 0x32, 0x32, 0x9c, 0x43, 
+  0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 
+  0x45, 0x45, 0x2d, 0x80, 0x57, 0x6d, 0x90, 0x91, 0xc6, 0xc7, 0xc7, 0xc8, 0xc9, 0xb9, 0xbf, 0xa7, 
+  0xa7, 0x60, 0xbe, 0x23, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x21, 0x21, 0x25, 0x25, 0x25, 0x25, 
+  0x29, 0x24, 0x24, 0x24, 0x24, 0x26, 0x2a, 0x2a, 0x23, 0xca, 0x84, 0x6d, 0xb0, 0xab, 0xab, 0xab, 
+  0xa7, 0xab, 0xab, 0xa7, 0xab, 0xab, 0xa7, 0xb0, 0x7d, 0xa7, 0x4c, 0x4a, 0x32, 0x32, 0x32, 0x3d, 
+  0x2c, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 
+  0x45, 0x8d, 0xcb, 0x6c, 0x6d, 0x60, 0x5f, 0x55, 0x84, 0x6c, 0x84, 0x90, 0x7c, 0xbf, 0xb0, 0xab, 
+  0xa7, 0xa7, 0xd3, 0x92, 0x26, 0x26, 0x26, 0x26, 0x25, 0x25, 0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 
+  0x25, 0x25, 0x25, 0x21, 0x21, 0x23, 0x2a, 0x2a, 0x21, 0x2d, 0xc9, 0xb1, 0x74, 0xab, 0xab, 0xab, 
+  0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xa7, 0xab, 0x62, 0xb4, 0x48, 0x32, 0x32, 0x32, 
+  0x31, 0x70, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 
+  0x41, 0x79, 0x97, 0xc9, 0xb9, 0x74, 0x74, 0xb1, 0xb9, 0xb9, 0x5f, 0x6d, 0x74, 0xb0, 0xab, 0xab, 
+  0x56, 0xab, 0xd4, 0xd5, 0xd6, 0x21, 0x26, 0x26, 0x25, 0x24, 0x29, 0x29, 0x29, 0x24, 0x25, 0x25, 
+  0x24, 0x21, 0x21, 0x26, 0x23, 0x2a, 0x2a, 0x26, 0x25, 0x2d, 0xbb, 0x5f, 0xa7, 0xab, 0xab, 0xab, 
+  0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xa7, 0x7e, 0x66, 0xcc, 0x32, 0x32, 0x32, 
+  0x32, 0x21, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 
+  0xa2, 0x9d, 0xcd, 0x73, 0xb9, 0x74, 0xbf, 0x74, 0x74, 0x74, 0xaf, 0x74, 0xbf, 0xa7, 0xab, 0xb0, 
+  0xab, 0xab, 0xb0, 0x60, 0xd4, 0xd7, 0x25, 0x26, 0x25, 0x24, 0x29, 0x24, 0x25, 0x25, 0x21, 0x21, 
+  0x25, 0x21, 0x26, 0x23, 0x22, 0x22, 0x23, 0x21, 0x25, 0x2b, 0xd8, 0xd9, 0x56, 0xab, 0xab, 0xab, 
+  0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xb0, 0x56, 0x58, 0x7b, 0xda, 0x32, 0x32, 
+  0x32, 0x26, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x41, 
+  0x43, 0x2f, 0xdb, 0x73, 0xb9, 0x74, 0xb0, 0xa7, 0xa7, 0xb0, 0xb0, 0xab, 0xab, 0xab, 0xab, 0xab, 
+  0xab, 0x56, 0xab, 0xab, 0xab, 0xd4, 0xb7, 0x29, 0x24, 0x24, 0x24, 0x21, 0x26, 0x26, 0x26, 0x21, 
+  0x24, 0x26, 0x22, 0x2a, 0x28, 0x2a, 0x21, 0x25, 0x25, 0x29, 0xb8, 0xd9, 0xbf, 0xab, 0xab, 0xab, 
+  0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xa7, 0xa7, 0xb0, 0x7d, 0x62, 0x90, 0x31, 0x36, 
+  0x28, 0x40, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x41, 0x45, 0x41, 0x40, 
+  0x38, 0x33, 0xba, 0x73, 0xb9, 0xa7, 0xa7, 0xa7, 0xa7, 0xa7, 0xa7, 0xa7, 0xab, 0xab, 0xab, 0xb0, 
+  0xab, 0xab, 0x7e, 0xab, 0xb0, 0xab, 0xf9, 0xd6, 0x2b, 0x2b, 0x24, 0x21, 0x26, 0x23, 0x26, 0x26, 
+  0x25, 0x26, 0x2a, 0x2a, 0x2a, 0x22, 0x21, 0x24, 0x25, 0x24, 0xd8, 0x5f, 0xa7, 0xa7, 0xab, 0xab, 
+  0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xa7, 0xb0, 0xa7, 0x7e, 0x4d, 0x94, 0x41, 
+  0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x41, 0x41, 0x52, 0x34, 
+  0x32, 0x32, 0xda, 0x91, 0xb9, 0xbf, 0xab, 0xa7, 0xab, 0xb0, 0xab, 0xab, 0xab, 0xab, 0xab, 0xb0, 
+  0xab, 0xb0, 0xa7, 0xa7, 0xa7, 0x74, 0xd4, 0xfa, 0x2b, 0x29, 0x25, 0x26, 0x22, 0x23, 0x21, 0x21, 
+  0x21, 0x26, 0x2a, 0x28, 0x2a, 0x26, 0x25, 0x24, 0x21, 0xbe, 0xc9, 0x5f, 0xbf, 0xa7, 0xab, 0xab, 
+  0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0x56, 0x61, 0x4f, 0xca, 
+  0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x41, 0x45, 0x41, 0x45, 0x40, 0x22, 0x31, 0x32, 
+  0x32, 0x32, 0xc5, 0xc6, 0x6d, 0x56, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 
+  0x7d, 0x7d, 0xab, 0xa7, 0x74, 0x7c, 0xce, 0x3f, 0x29, 0x26, 0x2a, 0x28, 0x28, 0x2a, 0x23, 0x26, 
+  0x26, 0x23, 0x2a, 0x27, 0x2a, 0x21, 0x24, 0x24, 0x21, 0x8b, 0x84, 0x74, 0xbf, 0xab, 0xab, 0xab, 
+  0xab, 0xab, 0xa7, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xa7, 0x74, 0xdc, 0xdd, 
+  0x29, 0x41, 0x45, 0x41, 0x45, 0x45, 0x41, 0x45, 0x41, 0x41, 0x40, 0x21, 0x3b, 0x33, 0x32, 0x32, 
+  0x32, 0x32, 0xcc, 0xc6, 0xb9, 0xbf, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 
+  0xab, 0x56, 0x56, 0x4d, 0xd8, 0xfb, 0xcf, 0x29, 0x26, 0x28, 0x2e, 0x2e, 0x27, 0x2a, 0x26, 0x26, 
+  0x28, 0x2a, 0x28, 0x28, 0x2a, 0x26, 0x24, 0x25, 0x2b, 0xde, 0xdf, 0xaf, 0xa7, 0xa7, 0xab, 0xab, 
+  0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0x56, 0xb1, 0x7f, 0x7a, 
+  0x3d, 0x42, 0x28, 0x25, 0x29, 0x29, 0x24, 0x26, 0x27, 0x49, 0x37, 0x32, 0x32, 0x32, 0x32, 0x32, 
+  0x32, 0x31, 0xe0, 0xc6, 0xaf, 0x74, 0xab, 0xab, 0xab, 0xa7, 0xa7, 0xab, 0xab, 0xa7, 0xa7, 0xb0, 
+  0xaa, 0x80, 0xd8, 0xae, 0xfa, 0x92, 0x24, 0x26, 0x28, 0x3e, 0x2f, 0x27, 0x2a, 0x26, 0x21, 0x21, 
+  0x27, 0x2a, 0x2a, 0x28, 0x22, 0x21, 0x24, 0x25, 0xbe, 0xe1, 0xdf, 0x5f, 0x6d, 0x6d, 0x74, 0x74, 
+  0x56, 0x56, 0xa7, 0x56, 0xa7, 0xa7, 0xab, 0xb0, 0xab, 0xab, 0xab, 0xb0, 0xb0, 0x6d, 0x84, 0xe2, 
+  0x6a, 0x32, 0x33, 0x33, 0x32, 0x32, 0x33, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 
+  0x32, 0x48, 0xe0, 0xc6, 0x5f, 0xbf, 0xab, 0xab, 0xa7, 0xb0, 0xab, 0xab, 0x56, 0xaf, 0xb1, 0xb9, 
+  0x6c, 0xfb, 0x20, 0x2b, 0x2b, 0x29, 0x26, 0x27, 0x3e, 0x3e, 0x27, 0x2a, 0x26, 0x21, 0x25, 0x25, 
+  0x21, 0x21, 0x26, 0x22, 0x22, 0x21, 0x24, 0x24, 0x29, 0x5d, 0x83, 0xc6, 0xc9, 0x7f, 0x55, 0xd9, 
+  0xd9, 0xb9, 0xb9, 0xaf, 0x74, 0x74, 0xa7, 0xab, 0xab, 0xab, 0xab, 0xab, 0x74, 0x5f, 0x88, 0x7a, 
+  0xba, 0xb3, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 
+  0x32, 0x48, 0xe3, 0xc7, 0xdf, 0x6d, 0xa7, 0xa7, 0xa7, 0xa7, 0x56, 0x74, 0xb9, 0x5f, 0xbc, 0x8a, 
+  0xc4, 0x24, 0x24, 0x2b, 0x2b, 0x25, 0x28, 0x3e, 0x38, 0x2e, 0x2a, 0x26, 0x21, 0x24, 0x25, 0x24, 
+  0x20, 0x24, 0x21, 0x23, 0x26, 0x21, 0x24, 0x25, 0x21, 0x2d, 0xe4, 0xe5, 0xe6, 0x54, 0xe7, 0x88, 
+  0xc6, 0xc6, 0x89, 0x89, 0xdf, 0xd9, 0xb1, 0x74, 0x74, 0xbf, 0xbf, 0xbf, 0x5f, 0x7f, 0x95, 0x82, 
+  0xba, 0xb3, 0x32, 0x32, 0xb3, 0x32, 0x33, 0x32, 0x32, 0x32, 0x33, 0x32, 0x32, 0x32, 0x32, 0x32, 
+  0x33, 0x36, 0xcc, 0xe8, 0x91, 0xd9, 0x6d, 0x74, 0x74, 0xaf, 0xb9, 0xd9, 0x89, 0x5e, 0xe9, 0x70, 
+  0x25, 0x25, 0x29, 0x2b, 0x2b, 0x25, 0x27, 0x2f, 0x2e, 0x2a, 0x26, 0x21, 0x25, 0x24, 0x24, 0x24, 
+  0x70, 0x21, 0x26, 0x23, 0x26, 0x25, 0x29, 0x24, 0x21, 0x21, 0x24, 0x29, 0x2b, 0x2b, 0xd6, 0xea, 
+  0xeb, 0x87, 0xec, 0x87, 0xe8, 0xc7, 0x91, 0x89, 0x90, 0x80, 0xb9, 0x90, 0x91, 0xe8, 0x82, 0xc3, 
+  0x6a, 0x3b, 0x22, 0x21, 0x25, 0x25, 0x25, 0x25, 0x24, 0x24, 0x24, 0x24, 0x25, 0x25, 0x25, 0x23, 
+  0x2e, 0x39, 0xda, 0xed, 0xc7, 0x84, 0xd9, 0xd9, 0x5f, 0xd9, 0x89, 0xc6, 0x96, 0x8b, 0x2b, 0x25, 
+  0x21, 0x21, 0x24, 0x2b, 0x24, 0x26, 0x28, 0x2e, 0x2a, 0x23, 0x26, 0x21, 0x24, 0x29, 0x29, 0x24, 
+  0x79, 0x28, 0x28, 0x22, 0x21, 0x25, 0x29, 0x24, 0x21, 0x26, 0x25, 0x24, 0x29, 0x24, 0x21, 0x25, 
+  0x29, 0xca, 0x93, 0x99, 0xee, 0x7a, 0x7a, 0xef, 0xe7, 0x96, 0x88, 0xe7, 0xed, 0x82, 0xc3, 0x5b, 
+  0xf0, 0x29, 0x26, 0x26, 0x21, 0x21, 0x21, 0x26, 0x21, 0x25, 0x25, 0x24, 0x21, 0x21, 0x25, 0x24, 
+  0x2b, 0x70, 0xf1, 0x82, 0xef, 0xe7, 0x88, 0xc6, 0xc6, 0x88, 0x87, 0x8f, 0xbe, 0x29, 0x29, 0x25, 
+  0x25, 0x25, 0x24, 0x29, 0x21, 0x22, 0x28, 0x27, 0x28, 0x28, 0x2a, 0x26, 0x25, 0x29, 0x24, 0x21, 
+  0x21, 0x3e, 0x27, 0x22, 0x21, 0x25, 0x24, 0x25, 0x26, 0x21, 0x25, 0x24, 0x24, 0x25, 0x25, 0x25, 
+  0x25, 0x24, 0x26, 0x2a, 0x21, 0x25, 0x9b, 0xf2, 0xf3, 0xf3, 0x82, 0x82, 0xe3, 0xc3, 0xda, 0x2c, 
+  0x21, 0x22, 0x26, 0x21, 0x25, 0x24, 0x25, 0x21, 0x21, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25, 0x29, 
+  0x2b, 0x2c, 0x9b, 0xc5, 0xc3, 0xc1, 0xe2, 0xef, 0xed, 0x72, 0xf2, 0x92, 0x25, 0x24, 0x24, 0x24, 
+  0x21, 0x25, 0x24, 0x25, 0x21, 0x2a, 0x28, 0x28, 0x28, 0x28, 0x2a, 0x21, 0x29, 0x29, 0x25, 0x21, 
+  0x28, 0x3e, 0x27, 0x23, 0x21, 0x25, 0x24, 0x24, 0x21, 0x26, 0x25, 0x24, 0x29, 0x24, 0x21, 0x21, 
+  0x21, 0x25, 0x26, 0x2a, 0x2a, 0x2a, 0x28, 0x25, 0x97, 0x86, 0xf4, 0x5b, 0xda, 0xf5, 0x2b, 0x25, 
+  0x26, 0x26, 0x21, 0x25, 0x25, 0x25, 0x21, 0x21, 0x21, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25, 0x24, 
+  0x29, 0x25, 0x2a, 0x21, 0xf0, 0xf6, 0xdd, 0xf7, 0xf7, 0xf8, 0xbe, 0x21, 0x21, 0x24, 0x29, 0x24, 
+  0x21, 0x26, 0x25, 0x21, 0x26, 0x2a, 0x2a, 0x2a, 0x28, 0x2a, 0x26, 0x29, 0x2b, 0x2b, 0x21, 0x26, 
+  0x2a, 0x27, 0x2a, 0x21, 0x25, 0x25, 0x25, 0x24, 0x25, 0x21, 0x25, 0x24, 0x29, 0x24, 0x21, 0x26, 
+  0x26, 0x21, 0x26, 0x26, 0x26, 0x26, 0x26, 0x21, 0x24, 0x92, 0x20, 0x20, 0x24, 0x21, 0x21, 0x21, 
+  0x21, 0x26, 0x25, 0x25, 0x21, 0x26, 0x26, 0x21, 0x21, 0x21, 0x24, 0x24, 0x24, 0x24, 0x25, 0x24, 
+  0x25, 0x26, 0x2a, 0x28, 0x22, 0x25, 0x2b, 0x2b, 0x2b, 0x24, 0x25, 0x21, 0x25, 0x24, 0x29, 0x24, 
+  0x25, 0x26, 0x26, 0x21, 0x26, 0x26, 0x26, 0x26, 0x26, 0x21, 0x29, 0x2b, 0x20, 0x29, 0x26, 0x23, 
+  0x26, 0x26, 0x26, 0x25, 0x25, 0x25, 0x25, 0x24, 0x24, 0x21, 0x25, 0x24, 0x24, 0x24, 0x25, 0x21, 
+  0x26, 0x21, 0x21, 0x25, 0x25, 0x25, 0x25, 0x24, 0x2b, 0x20, 0x2b, 0x25, 0x26, 0x26, 0x21, 0x21, 
+  0x23, 0x23, 0x26, 0x26, 0x23, 0x26, 0x26, 0x21, 0x21, 0x25, 0x25, 0x24, 0x24, 0x24, 0x25, 0x25, 
+  0x24, 0x21, 0x23, 0x23, 0x21, 0x21, 0x25, 0x25, 0x25, 0x24, 0x25, 0x25, 0x25, 0x24, 0x24, 0x25, 
+  0x25, 0x21, 0x26, 0x21, 0x21, 0x25, 0x25, 0x25, 0x25, 0x24, 0x2b, 0x20, 0x2b, 0x24, 0x26, 0x26, 
+  0x21, 0x21, 0x21, 0x21, 0x25, 0x25, 0x25, 0x25, 0x25, 0x21, 0x21, 0x21, 0x25, 0x25, 0x25, 0x21, 
+  0x26, 0x21, 0x25, 0x25, 0x24, 0x24, 0x29, 0x29, 0x2b, 0x2b, 0x24, 0x21, 0x23, 0x26, 0x21, 0x26, 
+  0x22, 0x2a, 0x23, 0x23, 0x22, 0x23, 0x21, 0x21, 0x25, 0x25, 0x24, 0x29, 0x24, 0x24, 0x24, 0x24, 
+  0x24, 0x24, 0x25, 0x21, 0x21, 0x25, 0x25, 0x25, 0x25, 0x24, 0x25, 0x21, 0x21, 0x21, 0x25, 0x25, 
+  0x25, 0x21, 0x26, 0x26, 0x25, 0x25, 0x24, 0x24, 0x29, 0x29, 0x2b, 0x2b, 0x24, 0x26, 0x23, 0x26
+};
+
+#endif
+
+#ifdef INCLUDE_LINUX_LOGO16
+
+unsigned char linux_logo16_red[] __initdata = {
+0x06, 0xab, 0xef, 0xcc, 0x56, 0xe1, 0x77, 0xfc, 0xc8, 0x34, 0xcd, 0xa6, 0x79, 0xad, 0x96, 0xf3
+};
+
+unsigned char linux_logo16_green[] __initdata = {
+0x06, 0x87, 0xce, 0xa8, 0x52, 0xa8, 0x76, 0xfc, 0x92, 0x30, 0xcb, 0x72, 0x53, 0xad, 0x96, 0xbc
+};
+
+unsigned char linux_logo16_blue[] __initdata = {
+0x07, 0x23, 0x20, 0x39, 0x49, 0x0e, 0x72, 0xfa, 0x15, 0x28, 0xc4, 0x10, 0x0e, 0xab, 0x94, 0x10
+};
+
+unsigned char linux_logo16[] __initdata = {
+0xae, 0xee, 0xed, 0xdd, 0xee, 0xee, 0xee, 0xde, 0xe6, 0x6d, 0xdd, 0xdd, 0xe6, 0x6d, 0xaa, 0xdd, 0xdd, 0xee, 0xdd, 0xee, 0xed, 0xdd, 0xaa, 0xaa, 0xaa, 0xae, 0xee, 0xed, 0xdd, 0xee, 0xee, 0xee, 0xde, 0xe6, 0x6d, 0xdd, 0xdd, 0xe6, 0x6d, 0xaa,
+0xe6, 0x66, 0xdd, 0xde, 0xee, 0xe6, 0xee, 0xee, 0x66, 0x6e, 0xad, 0xdd, 0xee, 0xed, 0xad, 0xdd, 0xde, 0xee, 0xee, 0xdd, 0xdd, 0xde, 0xdd, 0xdd, 0xdd, 0xe6, 0x66, 0xdd, 0xde, 0xee, 0xe6, 0xee, 0xee, 0x66, 0x6e, 0xad, 0xdd, 0xee, 0xdd, 0xdd,
+0xe6, 0x6e, 0xed, 0xde, 0xee, 0xee, 0xee, 0xe6, 0x6e, 0xed, 0xdd, 0xdd, 0xed, 0xdd, 0xdd, 0xdd, 0xee, 0xed, 0xdd, 0xde, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xe6, 0x6e, 0xed, 0xde, 0xee, 0xee, 0xee, 0xe6, 0x6e, 0xed, 0xdd, 0xdd, 0xee, 0xdd, 0xad,
+0x66, 0x6e, 0xdd, 0xde, 0xee, 0x6e, 0xee, 0xee, 0xee, 0xdd, 0xad, 0xdd, 0xee, 0xed, 0xdd, 0xde, 0xee, 0xd4, 0x00, 0x00, 0x00, 0x09, 0xdd, 0xdd, 0xee, 0x66, 0x6e, 0xdd, 0xde, 0xee, 0x6e, 0xee, 0xee, 0xee, 0xdd, 0xad, 0xdd, 0xde, 0xde, 0xdd,
+0x66, 0x6d, 0xdd, 0xdd, 0xee, 0xee, 0xee, 0xee, 0xed, 0xdd, 0xdd, 0xde, 0xee, 0xde, 0xee, 0xed, 0xd6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0xde, 0xee, 0x66, 0x6d, 0xdd, 0xdd, 0xee, 0xee, 0xee, 0xee, 0xed, 0xdd, 0xdd, 0xde, 0xee, 0xee, 0xee,
+0x6e, 0xed, 0xad, 0xde, 0xee, 0x6e, 0xee, 0xdd, 0xda, 0xdd, 0xdd, 0xee, 0xee, 0xee, 0xdd, 0xed, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x90, 0x06, 0xee, 0x6e, 0xed, 0xad, 0xde, 0xee, 0x6e, 0xee, 0xdd, 0xda, 0xdd, 0xdd, 0xee, 0xee, 0xde, 0xdd,
+0xee, 0xed, 0xdd, 0xde, 0xe6, 0xee, 0xee, 0xdd, 0xdd, 0xdd, 0xde, 0xde, 0xdd, 0xdd, 0xed, 0xd4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x49, 0x00, 0x4d, 0xee, 0xed, 0xdd, 0xde, 0xe6, 0xee, 0xee, 0xdd, 0xdd, 0xdd, 0xde, 0xee, 0xed, 0xdd, 0xde,
+0xd6, 0xed, 0xdd, 0xee, 0x66, 0xee, 0xed, 0xdd, 0xed, 0xdd, 0xed, 0xee, 0xee, 0xee, 0xde, 0xd0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x64, 0x90, 0x06, 0xd6, 0xed, 0xdd, 0xee, 0x66, 0xee, 0xed, 0xdd, 0xde, 0xde, 0xde, 0xde, 0xed, 0xee, 0xed,
+0xee, 0xed, 0xdd, 0xde, 0x6e, 0xee, 0xdd, 0xdd, 0xde, 0xed, 0xde, 0xee, 0xee, 0xee, 0xee, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x44, 0x90, 0x00, 0xde, 0xee, 0xdd, 0xde, 0x6e, 0xee, 0xdd, 0xdd, 0xde, 0xed, 0xde, 0xde, 0xee, 0xee, 0xee,
+0xde, 0xed, 0xdd, 0xe6, 0x6e, 0xed, 0xdd, 0xde, 0xee, 0xee, 0xee, 0xee, 0xe6, 0xee, 0xed, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x6e, 0xdd, 0xad, 0xe6, 0x6e, 0xed, 0xdd, 0xde, 0xee, 0xee, 0xee, 0xe6, 0x6e, 0x6e, 0xee,
+0xdd, 0xda, 0xdd, 0xee, 0x6d, 0xdd, 0xdd, 0xde, 0xee, 0xee, 0xee, 0xee, 0xee, 0xde, 0xed, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0xdd, 0xdd, 0xee, 0x6d, 0xdd, 0xdd, 0xde, 0xee, 0xee, 0xee, 0xee, 0xee, 0xdd, 0xed,
+0xdd, 0xdd, 0xde, 0x66, 0xee, 0xdd, 0xde, 0xee, 0x6e, 0xee, 0xee, 0xed, 0xdd, 0xdd, 0xde, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0xdd, 0xde, 0x66, 0xee, 0xdd, 0xde, 0xee, 0x6e, 0xee, 0xee, 0xed, 0xdd, 0xdd, 0xdd,
+0xdd, 0xde, 0xde, 0xe6, 0xdd, 0xde, 0xe6, 0xee, 0xee, 0xee, 0xee, 0xdd, 0xda, 0xdd, 0xd6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x90, 0x00, 0x00, 0x04, 0xde, 0xde, 0xe6, 0xdd, 0xde, 0xee, 0x6e, 0xee, 0xee, 0xee, 0xdd, 0xdd, 0xad, 0xdd,
+0xde, 0xee, 0xe6, 0xee, 0xde, 0xde, 0xe6, 0xee, 0xd6, 0xe6, 0xee, 0xdd, 0xdd, 0xdd, 0xd6, 0x00, 0x09, 0x09, 0x00, 0x00, 0x09, 0x64, 0x99, 0x00, 0x00, 0x04, 0xee, 0xe6, 0xee, 0xde, 0xde, 0x6e, 0xee, 0xee, 0xe6, 0xee, 0xdd, 0xdd, 0xed, 0xee,
+0xdd, 0xee, 0x6e, 0x6e, 0xde, 0xd6, 0xee, 0xed, 0xe6, 0xee, 0xee, 0xdd, 0xdd, 0xee, 0xee, 0x00, 0xea, 0x69, 0x00, 0x00, 0x4e, 0xda, 0xd9, 0x00, 0x00, 0x09, 0xee, 0x6e, 0x6e, 0xde, 0xee, 0x6e, 0xed, 0xe6, 0xee, 0xed, 0xdd, 0xdd, 0xee, 0xee,
+0xde, 0x6e, 0x6e, 0xdd, 0xde, 0xee, 0xee, 0xdd, 0xee, 0x6e, 0xda, 0xda, 0xde, 0xee, 0xee, 0x04, 0xaa, 0x76, 0x00, 0x09, 0xa7, 0xa7, 0x76, 0x00, 0x00, 0x09, 0xe6, 0x6e, 0xdd, 0xde, 0xee, 0xee, 0xdd, 0xee, 0x6e, 0xdd, 0xda, 0xde, 0xee, 0xee,
+0xde, 0x6e, 0x66, 0xed, 0xde, 0xe6, 0xdd, 0xdd, 0xee, 0xdd, 0xaa, 0xdd, 0xee, 0x6e, 0xee, 0x0e, 0xd4, 0xa7, 0x00, 0x06, 0x7d, 0x04, 0xa7, 0x90, 0x00, 0x00, 0x6e, 0x66, 0xed, 0xde, 0xee, 0xed, 0xdd, 0xee, 0xdd, 0xaa, 0xad, 0xde, 0xee, 0xee,
+0xde, 0x66, 0xee, 0xdd, 0xee, 0xee, 0xde, 0xde, 0xee, 0xdd, 0xaa, 0xae, 0xe6, 0x66, 0xee, 0x0a, 0x99, 0x47, 0x90, 0x96, 0x79, 0x04, 0x47, 0x40, 0x00, 0x00, 0xe6, 0xee, 0xdd, 0xde, 0xee, 0xde, 0xde, 0xed, 0xdd, 0xaa, 0xde, 0x66, 0x66, 0xee,
+0xee, 0xe6, 0x6e, 0xdd, 0xee, 0xee, 0xde, 0xed, 0xed, 0xaa, 0xdd, 0xe6, 0x66, 0x6e, 0xee, 0x0a, 0x00, 0x9a, 0x90, 0x99, 0x70, 0x00, 0x97, 0x40, 0x00, 0x00, 0xe6, 0x6d, 0xdd, 0xee, 0xee, 0xde, 0xde, 0xed, 0xaa, 0xad, 0xe6, 0x66, 0x6e, 0xee,
+0x66, 0x66, 0xee, 0xdd, 0xee, 0xed, 0xdd, 0xdd, 0xdd, 0xda, 0xde, 0x66, 0x66, 0x6e, 0xed, 0x0d, 0x40, 0x01, 0x53, 0x31, 0xa9, 0x00, 0x47, 0x40, 0x00, 0x00, 0x66, 0x6e, 0xdd, 0xee, 0xed, 0xdd, 0xdd, 0xdd, 0xad, 0xde, 0x66, 0x66, 0x6e, 0xde,
+0x6e, 0xe6, 0xee, 0xdd, 0xee, 0xdd, 0xdd, 0xdd, 0xda, 0xad, 0xe6, 0x44, 0x6e, 0xed, 0xdd, 0x06, 0xa4, 0x18, 0xff, 0x58, 0x23, 0xc4, 0xaa, 0x00, 0x00, 0x00, 0xee, 0x6d, 0xdd, 0xee, 0xed, 0xdd, 0xdd, 0xdd, 0xad, 0xe6, 0x64, 0x66, 0xee, 0xdd,
+0xee, 0xe6, 0xed, 0xdd, 0xee, 0xdd, 0xdd, 0xdd, 0xdd, 0xad, 0x66, 0x46, 0x6e, 0xee, 0xdd, 0x00, 0x31, 0x5f, 0xf2, 0x22, 0x22, 0x2f, 0x21, 0x00, 0x00, 0x00, 0xd6, 0xee, 0xde, 0xee, 0xdd, 0xdd, 0xde, 0xad, 0xad, 0x66, 0x46, 0xee, 0xed, 0xdd,
+0xad, 0xde, 0xee, 0xdd, 0xee, 0xdd, 0xdd, 0xde, 0xda, 0xde, 0x66, 0x6e, 0xee, 0xdd, 0xdd, 0x09, 0xb8, 0x5f, 0x22, 0x22, 0x22, 0x22, 0x2f, 0x40, 0x00, 0x00, 0xde, 0xed, 0xdd, 0xee, 0xda, 0xdd, 0xde, 0xda, 0xde, 0x66, 0x66, 0xed, 0xdd, 0xdd,
+0xae, 0xe6, 0xed, 0xdd, 0xed, 0xda, 0xdd, 0xed, 0xda, 0xde, 0x66, 0x6e, 0xed, 0xdd, 0xad, 0x0c, 0x85, 0xff, 0x22, 0x22, 0x22, 0x23, 0x15, 0x40, 0x00, 0x00, 0x4e, 0xed, 0xdd, 0xed, 0xdd, 0xdd, 0xed, 0xda, 0xde, 0x66, 0x6e, 0xee, 0xdd, 0xdd,
+0xa6, 0x6e, 0xed, 0xdd, 0xee, 0xdd, 0xdd, 0xed, 0xdd, 0xde, 0x66, 0x66, 0x6e, 0xdd, 0xdd, 0x0b, 0x15, 0xff, 0x22, 0x22, 0x22, 0x58, 0x58, 0x90, 0x00, 0x00, 0x9e, 0xed, 0xdd, 0xde, 0xdd, 0xdd, 0xed, 0xdd, 0xde, 0x66, 0x66, 0xee, 0xdd, 0xdd,
+0xe6, 0x6e, 0xed, 0xdd, 0xde, 0xed, 0xdd, 0xdd, 0xdd, 0xe6, 0xe6, 0x66, 0xee, 0xad, 0xdd, 0x09, 0xc8, 0xf2, 0x22, 0x22, 0x81, 0x85, 0x81, 0x00, 0x94, 0x90, 0x0e, 0xed, 0xdd, 0xee, 0xdd, 0xdd, 0xde, 0xdd, 0xe6, 0x6e, 0x66, 0x6d, 0xdd, 0xde,
+0xe4, 0x6e, 0xed, 0xde, 0xed, 0xed, 0xdd, 0xee, 0xed, 0xe6, 0xe6, 0xe6, 0xed, 0xad, 0xdd, 0x00, 0xec, 0xb8, 0x33, 0x11, 0x88, 0x88, 0xda, 0x40, 0x04, 0x69, 0x06, 0xed, 0xdd, 0xee, 0xed, 0xdd, 0xde, 0xed, 0xee, 0x6e, 0x6e, 0xed, 0xaa, 0xee,
+0x66, 0xee, 0xed, 0xdd, 0xde, 0xdd, 0xdd, 0xde, 0xee, 0xee, 0xee, 0xed, 0xda, 0xad, 0xed, 0x09, 0xdd, 0xb1, 0x58, 0x88, 0x18, 0xea, 0xaa, 0xe0, 0x09, 0x64, 0x00, 0xde, 0xdd, 0xdd, 0xdd, 0xdd, 0xee, 0xee, 0xee, 0xee, 0xee, 0xad, 0xad, 0xee,
+0xee, 0xed, 0xde, 0xdd, 0xdd, 0xdd, 0xdd, 0xde, 0xed, 0xed, 0xdd, 0xed, 0xda, 0xad, 0xee, 0x00, 0xaa, 0xdb, 0xbb, 0xbb, 0x13, 0xaa, 0x77, 0xa9, 0x00, 0x00, 0x00, 0x9d, 0xdd, 0xde, 0xdd, 0xdd, 0xde, 0xee, 0xed, 0xdd, 0xdd, 0xda, 0xad, 0xee,
+0xde, 0xee, 0xed, 0xdd, 0xde, 0xed, 0xed, 0xde, 0xee, 0xdd, 0xdd, 0xad, 0xad, 0xde, 0xe9, 0x09, 0xaa, 0xad, 0xd8, 0xed, 0xad, 0xa7, 0x77, 0x7d, 0x00, 0x00, 0x00, 0x0e, 0xdd, 0xdd, 0xed, 0xdd, 0xdd, 0xee, 0xde, 0xdd, 0xda, 0xda, 0xde, 0xee,
+0xee, 0xdd, 0xde, 0xed, 0xde, 0xde, 0xee, 0xde, 0xee, 0xde, 0xdd, 0xdd, 0xdd, 0xee, 0x60, 0x0a, 0x77, 0xda, 0xda, 0xad, 0xa7, 0x77, 0x77, 0x77, 0x90, 0x00, 0x00, 0x00, 0xdd, 0xee, 0xee, 0xed, 0xee, 0xee, 0xdd, 0xdd, 0xdd, 0xde, 0xee, 0x6e,
+0xee, 0xee, 0xed, 0xee, 0xed, 0xde, 0xed, 0xee, 0xee, 0xed, 0xde, 0xee, 0xee, 0x6e, 0x00, 0x67, 0x77, 0xad, 0xad, 0xaa, 0x77, 0x77, 0x77, 0x77, 0xd0, 0x00, 0x00, 0x00, 0x4d, 0xdd, 0xde, 0xee, 0xde, 0xee, 0xee, 0xde, 0xee, 0xee, 0x6e, 0x6e,
+0x66, 0xee, 0xee, 0xdd, 0xde, 0xee, 0xee, 0xee, 0x66, 0xe6, 0xee, 0xe6, 0x66, 0xd0, 0x00, 0x77, 0x77, 0x7a, 0xaa, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x00, 0x00, 0x00, 0x0d, 0xee, 0xee, 0xee, 0xee, 0x6e, 0x6e, 0xee, 0xe6, 0x66, 0xe6, 0xe6,
+0xee, 0xee, 0xde, 0xee, 0xed, 0xde, 0xee, 0xee, 0xe6, 0xee, 0xee, 0x6e, 0x6e, 0x90, 0x06, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x76, 0x00, 0x00, 0x00, 0x00, 0xad, 0xde, 0xee, 0xee, 0x6e, 0x6e, 0xe6, 0xe6, 0xe6, 0x6e, 0xe6,
+0xed, 0xde, 0xed, 0xde, 0xdd, 0xee, 0xee, 0xee, 0xee, 0xee, 0xde, 0xee, 0xe4, 0x00, 0x07, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x7d, 0x00, 0x00, 0x00, 0x00, 0x9d, 0xed, 0xee, 0xee, 0xee, 0xed, 0xde, 0xee, 0xee, 0xe6, 0xe6,
+0xdd, 0xdd, 0xde, 0xde, 0xed, 0xed, 0xed, 0xee, 0xee, 0xdd, 0xde, 0xee, 0x60, 0x00, 0x4a, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x00, 0x00, 0x00, 0x00, 0x09, 0xde, 0xee, 0xed, 0xee, 0xdd, 0xde, 0xee, 0xed, 0xee, 0xee,
+0xdd, 0xad, 0xde, 0xdd, 0xed, 0xed, 0xee, 0xed, 0xed, 0xde, 0xde, 0xe6, 0x00, 0x00, 0x6a, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0xaa, 0xa7, 0x90, 0x00, 0x00, 0x00, 0x00, 0x4d, 0xdd, 0xee, 0xed, 0xde, 0xde, 0x6e, 0xee, 0xde, 0xee,
+0xad, 0xad, 0xde, 0xde, 0xde, 0xdd, 0xed, 0xed, 0xee, 0xee, 0x66, 0xd0, 0x00, 0x00, 0x6d, 0xa7, 0x77, 0x77, 0xa7, 0x77, 0x77, 0x7a, 0xaa, 0xaa, 0xad, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x0d, 0xee, 0xde, 0xde, 0xee, 0x6e, 0x6e, 0xee, 0xed, 0xed,
+0xaa, 0xdd, 0xdd, 0xdd, 0xde, 0xde, 0xee, 0xee, 0xdd, 0xee, 0xee, 0xe0, 0x00, 0x09, 0xd7, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x7a, 0xaa, 0xae, 0x00, 0x90, 0x00, 0x00, 0x04, 0xee, 0xee, 0xed, 0xee, 0xee, 0xee, 0x6e, 0x6e, 0xed,
+0xad, 0xdd, 0xdd, 0xed, 0xdd, 0xee, 0xee, 0xee, 0xee, 0xde, 0xee, 0x40, 0x00, 0x06, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x7a, 0xa7, 0x40, 0x00, 0x90, 0x00, 0x00, 0xde, 0xee, 0xed, 0xde, 0xee, 0xee, 0xee, 0xee, 0xee,
+0xae, 0xee, 0xde, 0xde, 0xde, 0xde, 0xee, 0xee, 0xde, 0xde, 0xdd, 0x00, 0x90, 0x0a, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x7a, 0xd0, 0x00, 0x90, 0x00, 0x00, 0x4e, 0xee, 0xee, 0xee, 0xde, 0xde, 0xde, 0xee, 0xde,
+0xde, 0xee, 0xee, 0xee, 0xee, 0xed, 0xde, 0xdd, 0xde, 0xee, 0xed, 0x09, 0x00, 0xe7, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x09, 0x09, 0x00, 0x00, 0x0d, 0xdd, 0xde, 0xde, 0xed, 0xee, 0xed, 0xed, 0xed,
+0xde, 0xee, 0xee, 0xde, 0xee, 0xee, 0xdd, 0xde, 0xdd, 0xde, 0xd4, 0x09, 0x09, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x7e, 0x04, 0x90, 0x90, 0x00, 0x0e, 0xdd, 0xdd, 0xde, 0xed, 0xdd, 0xee, 0xed, 0xdd,
+0xdd, 0xee, 0xed, 0xdd, 0xee, 0xed, 0xed, 0xdd, 0xdd, 0xdd, 0xd0, 0x90, 0x0e, 0x7d, 0x00, 0x00, 0x47, 0x77, 0x40, 0x00, 0x40, 0x00, 0x00, 0x00, 0x96, 0xa7, 0x7a, 0x00, 0x00, 0x90, 0x00, 0x09, 0xdd, 0xdd, 0xdd, 0xde, 0xde, 0xee, 0xde, 0xee,
+0xde, 0xed, 0xdd, 0xed, 0xed, 0xee, 0xdd, 0xed, 0xde, 0xde, 0xe0, 0x90, 0x07, 0x77, 0x70, 0x0e, 0x77, 0x77, 0x7e, 0x0a, 0x77, 0x40, 0x07, 0x7e, 0x00, 0x97, 0x77, 0x90, 0x00, 0x90, 0x00, 0x00, 0xdd, 0xde, 0xee, 0xde, 0xee, 0xee, 0xee, 0xee,
+0xde, 0xee, 0xdd, 0xde, 0xee, 0xee, 0xee, 0xee, 0xee, 0x6e, 0x90, 0x90, 0x47, 0x77, 0x79, 0x04, 0x77, 0x77, 0x79, 0x97, 0x77, 0x40, 0x97, 0x77, 0x90, 0x07, 0x77, 0x90, 0x00, 0x00, 0x00, 0x00, 0xee, 0xee, 0xe6, 0xe6, 0xee, 0x6e, 0xe6, 0xee,
+0xee, 0xee, 0xed, 0xdd, 0xed, 0xee, 0xed, 0xee, 0xe6, 0x6e, 0x09, 0x00, 0xa7, 0x77, 0x74, 0x09, 0x77, 0x77, 0x60, 0xa7, 0x77, 0x00, 0x47, 0x77, 0x40, 0x07, 0x77, 0x60, 0x00, 0x90, 0x00, 0x00, 0x6e, 0xe6, 0x66, 0x6e, 0xee, 0xde, 0xee, 0xed,
+0xdd, 0xed, 0xee, 0xdd, 0xed, 0xed, 0xed, 0xee, 0x66, 0x69, 0x09, 0x00, 0x77, 0x77, 0x76, 0x00, 0x77, 0x77, 0x96, 0x77, 0x7a, 0x00, 0xd7, 0x77, 0x90, 0x67, 0x77, 0x60, 0x00, 0x00, 0x00, 0x00, 0x9e, 0x66, 0x66, 0x6e, 0xdd, 0xde, 0x6e, 0xdd,
+0xdd, 0xde, 0xdd, 0xdd, 0xdd, 0xee, 0xed, 0xee, 0x66, 0x60, 0x09, 0x04, 0x77, 0x77, 0x7d, 0x00, 0x77, 0x76, 0x0a, 0x77, 0x7d, 0x00, 0xa7, 0xa4, 0x09, 0xa7, 0x77, 0x60, 0x00, 0x90, 0x00, 0x00, 0x9e, 0x66, 0x6e, 0xee, 0xdd, 0xde, 0x6e, 0xdd,
+0xad, 0xee, 0xde, 0xdd, 0xee, 0xee, 0xee, 0xdd, 0xee, 0x90, 0x09, 0x06, 0x77, 0x77, 0x7a, 0x00, 0xd7, 0x70, 0x67, 0x77, 0x76, 0x00, 0x44, 0x04, 0xd7, 0x77, 0x77, 0xe0, 0x00, 0x90, 0x00, 0x00, 0x0d, 0xe6, 0x6e, 0xdd, 0xdd, 0xd6, 0x6e, 0xda,
+0xae, 0xee, 0xdd, 0xed, 0xed, 0xee, 0xee, 0xde, 0xe6, 0x00, 0x04, 0x06, 0x77, 0x77, 0x77, 0x00, 0xd7, 0xe0, 0x77, 0x77, 0x74, 0x09, 0xd4, 0x09, 0xa7, 0x77, 0x77, 0xe0, 0x00, 0x90, 0x00, 0x00, 0x0d, 0xe6, 0x6e, 0xdd, 0xad, 0xe6, 0xed, 0xad,
+0xe6, 0x66, 0xed, 0xde, 0xee, 0xe6, 0xee, 0xee, 0x64, 0x00, 0x04, 0x0e, 0x77, 0x77, 0x77, 0x00, 0x4a, 0x04, 0x77, 0x77, 0x79, 0x04, 0x77, 0x90, 0x97, 0x77, 0x77, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x66, 0xed, 0xdd, 0xde, 0xee, 0xed, 0xad,
+0xe6, 0x6e, 0xdd, 0xde, 0xee, 0x6e, 0xee, 0xe6, 0x64, 0x00, 0x00, 0x9e, 0x77, 0x77, 0x77, 0x40, 0x46, 0x97, 0x77, 0x77, 0x70, 0x0e, 0x77, 0xd0, 0x0a, 0x77, 0x77, 0x60, 0x09, 0x00, 0x00, 0x00, 0x0e, 0x66, 0xed, 0xad, 0xdd, 0xee, 0xdd, 0xdd,
+0x66, 0x6e, 0xdd, 0xde, 0xee, 0xee, 0xee, 0xee, 0xe6, 0x09, 0x40, 0x0e, 0x77, 0x77, 0x77, 0x60, 0x00, 0x67, 0x77, 0x77, 0xd0, 0x0d, 0x77, 0xa0, 0x06, 0x77, 0x77, 0x40, 0x90, 0x00, 0x09, 0x00, 0x4e, 0xee, 0xdd, 0xdd, 0xde, 0xde, 0xdd, 0xdd,
+0x66, 0x6d, 0xdd, 0xdd, 0xee, 0xee, 0xee, 0xee, 0xed, 0x1f, 0xf8, 0x04, 0x77, 0x77, 0x77, 0xd0, 0x09, 0x77, 0x77, 0x77, 0xe0, 0x07, 0x77, 0x79, 0x09, 0x77, 0x77, 0x90, 0x00, 0x00, 0x00, 0x40, 0x6e, 0xed, 0xdd, 0xad, 0xde, 0xee, 0xee, 0xee,
+0x6e, 0xed, 0xda, 0xde, 0xe6, 0xe6, 0xee, 0xdd, 0xa3, 0x5f, 0xf2, 0x10, 0x9a, 0x77, 0x77, 0xa0, 0x06, 0x77, 0x77, 0x74, 0x00, 0x04, 0xe7, 0x7a, 0x00, 0x94, 0xa2, 0x10, 0x00, 0x00, 0x00, 0x99, 0xed, 0xdd, 0xdd, 0xdd, 0xee, 0xee, 0xde, 0xdd,
+0xee, 0xed, 0xdd, 0xde, 0xe6, 0xee, 0xee, 0xda, 0xa5, 0x5f, 0xff, 0xf1, 0x09, 0xa7, 0x77, 0x7d, 0xd7, 0x77, 0x77, 0x7d, 0xdd, 0xdd, 0xa7, 0x77, 0xad, 0xdd, 0xf2, 0xb0, 0x00, 0x00, 0x00, 0x06, 0xf7, 0xdd, 0xdd, 0xde, 0xde, 0xed, 0xdd, 0xed,
+0xd6, 0xed, 0xdd, 0xee, 0x66, 0xda, 0xaa, 0xa3, 0x85, 0xff, 0x2f, 0xf2, 0xc0, 0x0d, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x52, 0xc0, 0x00, 0x00, 0x00, 0x95, 0x22, 0xad, 0xed, 0xde, 0xed, 0xee, 0xee, 0xde,
+0xd6, 0xed, 0xdd, 0xde, 0xee, 0xd8, 0x58, 0x55, 0x5f, 0xff, 0xff, 0xff, 0xf9, 0x00, 0xe7, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0xf5, 0x10, 0x00, 0x00, 0x09, 0x8f, 0xf2, 0xae, 0xee, 0xde, 0xde, 0xee, 0xee, 0xee,
+0xde, 0xed, 0xdd, 0xe6, 0x6a, 0x85, 0xff, 0xf5, 0xff, 0xff, 0xff, 0xff, 0x21, 0x00, 0x06, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0xa8, 0xf5, 0x8b, 0x90, 0x09, 0xc1, 0x5f, 0xf3, 0xdd, 0xde, 0xee, 0x6e, 0x6e, 0x6e, 0xee,
+0xad, 0xda, 0xdd, 0xe6, 0xea, 0x85, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x2f, 0x40, 0x00, 0x47, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0xa5, 0x55, 0x88, 0xbb, 0xb1, 0x85, 0xff, 0xff, 0xae, 0xee, 0xee, 0xee, 0xed, 0xed, 0xdd,
+0xdd, 0xdd, 0xde, 0xe6, 0xea, 0x85, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x50, 0x00, 0x00, 0xa7, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x7a, 0xa8, 0xf5, 0x55, 0x88, 0x88, 0x5f, 0xff, 0xff, 0x2d, 0xee, 0xee, 0xdd, 0xdd, 0xdd, 0xdd,
+0xdd, 0xde, 0xde, 0x6e, 0xea, 0x85, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc, 0x00, 0x00, 0x0a, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x7a, 0xd8, 0x5f, 0x55, 0x55, 0x55, 0xff, 0xff, 0xff, 0xfa, 0xad, 0xee, 0xdd, 0xdd, 0xdd, 0xdd,
+0xde, 0xee, 0x6e, 0x6e, 0xda, 0x85, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x2f, 0xc0, 0x00, 0x0d, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x7a, 0x68, 0x5f, 0xff, 0xff, 0x55, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xde, 0xed, 0xad, 0xdd, 0xee,
+0xde, 0xee, 0xee, 0xee, 0xda, 0x35, 0xff, 0xf2, 0xff, 0x2f, 0xff, 0xff, 0xff, 0xf2, 0x19, 0x00, 0x0e, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x76, 0x91, 0x5f, 0x5f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xad, 0xdd, 0xde, 0xee, 0xee,
+0xde, 0xe6, 0x66, 0xed, 0xdd, 0x35, 0xff, 0xff, 0xff, 0xff, 0x2f, 0xff, 0xff, 0xff, 0x25, 0x00, 0x67, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x40, 0x98, 0x5f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x2f, 0xff, 0x2a, 0xaa, 0xde, 0xee, 0xee,
+0xde, 0x6e, 0xee, 0xed, 0xdd, 0x35, 0xff, 0xff, 0xff, 0xff, 0xff, 0x2f, 0xff, 0xff, 0xf3, 0x37, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0xa9, 0x00, 0x98, 0x5f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xad, 0xde, 0xee, 0xee,
+0xee, 0x66, 0x6e, 0xdd, 0xea, 0x85, 0xff, 0xff, 0x2f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x1a, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x7e, 0x00, 0x00, 0xcb, 0x5f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, 0xf7, 0xde, 0x66, 0x66, 0xee,
+0xee, 0xe6, 0xee, 0xdd, 0xe3, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf2, 0xff, 0x8c, 0xd7, 0x77, 0x77, 0x77, 0x77, 0x7e, 0x90, 0x00, 0x00, 0xcb, 0x5f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x3a, 0xaa, 0xe6, 0x66, 0x6e, 0xee,
+0x66, 0x66, 0x6e, 0xdd, 0xa3, 0x85, 0xff, 0xff, 0xf2, 0xff, 0x2f, 0xf2, 0xff, 0xff, 0xf5, 0x8b, 0x09, 0x6d, 0xad, 0xde, 0x69, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x5f, 0xff, 0xf2, 0xff, 0x2f, 0xff, 0xf3, 0x32, 0xaa, 0xde, 0x66, 0x66, 0x6e, 0xde,
+0x6e, 0xe6, 0xee, 0xdd, 0xa1, 0x85, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x8c, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xcb, 0x5f, 0xff, 0xff, 0xff, 0xff, 0x55, 0x8a, 0xaa, 0xdd, 0xe6, 0x64, 0x66, 0xee, 0xdd,
+0xee, 0xee, 0xee, 0xdd, 0xd3, 0x8b, 0x88, 0x85, 0x55, 0x5f, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xbb, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xcb, 0x8f, 0xff, 0xff, 0xff, 0x55, 0x88, 0xad, 0xda, 0xad, 0x66, 0x46, 0xee, 0xed, 0xdd,
+0xad, 0xee, 0xee, 0xdd, 0xea, 0xaa, 0x81, 0xbb, 0x18, 0x88, 0x85, 0x5f, 0xff, 0xff, 0x58, 0xbc, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xcb, 0x88, 0xff, 0xff, 0x55, 0x81, 0x3a, 0xdd, 0xdd, 0xae, 0x66, 0x66, 0xed, 0xdd, 0xdd,
+0xae, 0xee, 0xed, 0xdd, 0xed, 0xdd, 0xda, 0xa3, 0x1b, 0xbb, 0xbb, 0x88, 0x85, 0x58, 0x8b, 0xcc, 0x99, 0xee, 0xed, 0xed, 0xdd, 0xdd, 0xed, 0xee, 0x69, 0x9b, 0xb8, 0x58, 0x58, 0x8b, 0xba, 0xad, 0xee, 0xda, 0xde, 0x66, 0x6e, 0xee, 0xdd, 0xdd,
+0xa6, 0x6e, 0xed, 0xdd, 0xde, 0xdd, 0xad, 0xed, 0xda, 0xd8, 0xbc, 0xcb, 0xbb, 0xbb, 0xbc, 0xc9, 0xbd, 0xee, 0xed, 0xee, 0xed, 0xdd, 0xed, 0xdd, 0xda, 0xcc, 0xbb, 0xb8, 0xbb, 0xbb, 0xad, 0xdd, 0xdd, 0xdd, 0xee, 0x66, 0x66, 0xee, 0xdd, 0xdd,
+0xe6, 0x6e, 0xed, 0xdd, 0xee, 0xdd, 0xdd, 0xdd, 0xdd, 0xee, 0xed, 0xdb, 0xcc, 0xcc, 0xcc, 0x9a, 0xee, 0xee, 0xdd, 0xde, 0xee, 0xdd, 0xde, 0xdd, 0xaa, 0x39, 0xcc, 0xbb, 0xbc, 0xba, 0xdd, 0xdd, 0xed, 0xdd, 0xd6, 0x6e, 0x66, 0x6d, 0xdd, 0xde,
+0x64, 0x6e, 0xed, 0xdd, 0xee, 0xdd, 0xdd, 0xee, 0xed, 0xe6, 0xe6, 0x6d, 0xa1, 0xcc, 0x9b, 0xdd, 0xee, 0xed, 0xde, 0xde, 0xdd, 0xed, 0xde, 0xdd, 0xde, 0xee, 0x1c, 0xcc, 0xc1, 0xae, 0xed, 0xdd, 0xee, 0xde, 0xee, 0x6e, 0x6e, 0xed, 0xaa, 0xee,
+0xe6, 0x6e, 0xde, 0xdd, 0xde, 0xdd, 0xdd, 0xde, 0xee, 0xee, 0xee, 0xee, 0xda, 0xaa, 0xdd, 0xed, 0xee, 0xdd, 0xee, 0xed, 0xee, 0xdd, 0xdd, 0xdd, 0xde, 0xe6, 0xed, 0xda, 0xdd, 0xde, 0xdd, 0xdd, 0xde, 0xee, 0xee, 0xee, 0xee, 0xad, 0xad, 0xee,
+0xee, 0xed, 0xdd, 0xed, 0xde, 0xdd, 0xdd, 0xde, 0xed, 0xed, 0xdd, 0xdd, 0xda, 0xdd, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xdd, 0xdd, 0xdd, 0xde, 0xde, 0xee, 0xee, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xde, 0xee, 0xed, 0xde, 0xdd, 0xaa, 0xad, 0xee,
+0xde, 0xde, 0xed, 0xdd, 0xed, 0xee, 0xdd, 0xde, 0xee, 0xdd, 0xdd, 0xdd, 0xad, 0xde, 0xee, 0xee, 0xe6, 0xee, 0x6e, 0xee, 0xed, 0xdd, 0xdd, 0xdd, 0xdd, 0xde, 0xed, 0xed, 0xed, 0xde, 0xee, 0xde, 0xdd, 0xee, 0xdd, 0xdd, 0xdd, 0xdd, 0xde, 0xee
+};
+
+#endif
+
+#ifdef INCLUDE_LINUX_LOGOBW
+
+unsigned char linux_logo_bw[] __initdata = {
+0x20, 0xa9, 0x40, 0xa0, 0x22, 0x00, 0x08, 0x2a, 0x50, 0x28,
+0xb0, 0x95, 0x70, 0xa0, 0x28, 0x00, 0x2c, 0x25, 0x5c, 0x28,
+0x41, 0x52, 0x80, 0x00, 0xa1, 0x00, 0x28, 0x54, 0xa0, 0x00,
+0x70, 0x29, 0x40, 0x40, 0x9f, 0xf0, 0x54, 0x0a, 0x50, 0x10,
+0x80, 0xa4, 0x81, 0x55, 0x7f, 0xfd, 0x50, 0x29, 0x20, 0x55,
+0xa0, 0x54, 0x00, 0x90, 0xff, 0xff, 0x28, 0x15, 0x00, 0x90,
+0x41, 0x48, 0x05, 0x01, 0xff, 0xff, 0xa0, 0x52, 0x00, 0x40,
+0x20, 0xa8, 0x01, 0x55, 0xff, 0xf7, 0xd8, 0x2a, 0x11, 0x2a,
+0x41, 0x40, 0xa4, 0xab, 0xff, 0xff, 0xc0, 0x50, 0x08, 0xaa,
+0x22, 0xa0, 0x55, 0x53, 0xff, 0xff, 0xf0, 0xa8, 0x2a, 0xaa,
+0x02, 0x81, 0x24, 0x83, 0xff, 0xff, 0xe0, 0xa0, 0x54, 0x90,
+0x01, 0x45, 0x52, 0x03, 0xff, 0xff, 0xf0, 0x51, 0x52, 0x80,
+0x15, 0x15, 0x28, 0x07, 0xff, 0xff, 0xf5, 0x45, 0x54, 0x00,
+0x55, 0x15, 0x54, 0x03, 0xff, 0xef, 0xf5, 0x42, 0x8b, 0x02,
+0x2a, 0x48, 0x50, 0x37, 0x1f, 0x87, 0xf5, 0x15, 0x28, 0x14,
+0x2a, 0x54, 0x50, 0x13, 0x0f, 0x03, 0xfa, 0x85, 0x14, 0x12,
+0x54, 0x50, 0x80, 0xaa, 0x4e, 0x33, 0xf5, 0x12, 0x20, 0x14,
+0x54, 0x14, 0x40, 0xaa, 0xef, 0x7b, 0xf5, 0x09, 0x20, 0x2a,
+0x50, 0xa2, 0x82, 0xaa, 0xef, 0x79, 0xfa, 0x28, 0x80, 0xaa,
+0xac, 0x20, 0x05, 0xaa, 0xe0, 0x7b, 0xf5, 0x28, 0x01, 0x6a,
+0x50, 0x80, 0x0a, 0xa3, 0x40, 0x33, 0xf4, 0x10, 0x02, 0xa8,
+0x28, 0x40, 0x06, 0xa3, 0x40, 0x03, 0xf3, 0x10, 0x01, 0xa8,
+0x10, 0x81, 0x15, 0x03, 0x00, 0x03, 0xf4, 0x20, 0x45, 0x40,
+0x28, 0x40, 0x15, 0x43, 0x80, 0x0b, 0xfa, 0x10, 0x05, 0x50,
+0x50, 0x82, 0x15, 0x42, 0x00, 0x23, 0xf8, 0x20, 0x85, 0x51,
+0xa8, 0xa0, 0x2a, 0x83, 0x80, 0x4b, 0xfa, 0x10, 0x45, 0x50,
+0x50, 0x42, 0x95, 0x0b, 0x6a, 0x83, 0xdc, 0x28, 0x4a, 0xa2,
+0x50, 0x40, 0x55, 0x0b, 0x20, 0x41, 0xdc, 0x00, 0x2a, 0x82,
+0x40, 0x01, 0x00, 0x07, 0x1f, 0x01, 0xfe, 0x00, 0x80, 0x02,
+0x50, 0x21, 0x40, 0x17, 0x00, 0x00, 0xff, 0x08, 0x50, 0x02,
+0x22, 0x54, 0x80, 0x2e, 0x00, 0x00, 0xff, 0x14, 0xa0, 0x0a,
+0xa9, 0x12, 0xaa, 0xae, 0x00, 0x00, 0x7f, 0x82, 0x14, 0xaa,
+0x54, 0x49, 0x55, 0x5c, 0x00, 0x00, 0x7f, 0xa9, 0x55, 0x55,
+0xa5, 0x15, 0x52, 0xb8, 0x00, 0x00, 0x3f, 0xc5, 0x54, 0xaa,
+0x08, 0x12, 0x85, 0x78, 0x00, 0x00, 0x3f, 0xe9, 0x21, 0x55,
+0x05, 0x48, 0x41, 0x78, 0x00, 0x00, 0x3f, 0xf4, 0x90, 0x44,
+0x02, 0x25, 0x0a, 0xf0, 0x00, 0x00, 0x3f, 0xf9, 0x42, 0xaa,
+0x01, 0x11, 0x55, 0xf8, 0x00, 0x00, 0x1f, 0xf8, 0x2a, 0xaa,
+0x00, 0x0a, 0x15, 0xf0, 0x00, 0x00, 0x0f, 0xfe, 0x92, 0x51,
+0x00, 0x25, 0x43, 0xf0, 0x00, 0x00, 0x0f, 0xfd, 0x4a, 0x94,
+0x55, 0x52, 0x2b, 0xe0, 0x00, 0x00, 0x07, 0xfe, 0xa0, 0x4a,
+0x55, 0x00, 0x13, 0xc0, 0x00, 0x00, 0x07, 0xfe, 0x2a, 0x22,
+0x21, 0x50, 0x07, 0xc0, 0x00, 0x00, 0x03, 0xff, 0x04, 0x50,
+0x28, 0x20, 0x07, 0xcf, 0x8f, 0xff, 0xc3, 0xff, 0x00, 0x4a,
+0x40, 0x92, 0x17, 0x86, 0x02, 0x38, 0xe3, 0xff, 0x0a, 0xaa,
+0x50, 0x4a, 0xaf, 0x87, 0x06, 0x38, 0xe3, 0xff, 0xaa, 0xaa,
+0x28, 0xa1, 0x5f, 0x07, 0x0c, 0x38, 0xe3, 0xff, 0x55, 0x12,
+0x08, 0x15, 0x5f, 0x03, 0x0c, 0x30, 0xe1, 0xff, 0x95, 0x14,
+0x10, 0x21, 0x5f, 0x03, 0x18, 0x31, 0xc3, 0xff, 0xa8, 0x14,
+0x10, 0x94, 0xbf, 0x03, 0x18, 0x7f, 0x01, 0xff, 0x94, 0x14,
+0x50, 0xa9, 0x7e, 0x03, 0x10, 0x77, 0x03, 0xff, 0xa8, 0x28,
+0x28, 0x95, 0x7f, 0x03, 0xb0, 0x73, 0x81, 0xff, 0xa8, 0x28,
+0xd1, 0x52, 0xfe, 0x03, 0xa0, 0x61, 0x83, 0xff, 0xa8, 0x00,
+0x50, 0x2a, 0x3f, 0x01, 0xc0, 0x61, 0xc3, 0xff, 0xa0, 0x50,
+0xa0, 0xa5, 0x23, 0x01, 0xc0, 0xe1, 0xc3, 0xff, 0x40, 0x2a,
+0xa0, 0x54, 0x01, 0x81, 0xc1, 0xf0, 0xf1, 0xff, 0x80, 0x48,
+0x41, 0x48, 0x01, 0xc0, 0x00, 0x00, 0x03, 0xfe, 0x01, 0x20,
+0x21, 0x40, 0x80, 0xe0, 0x00, 0x00, 0x01, 0xfe, 0x08, 0xaa,
+0x41, 0x50, 0x00, 0x78, 0x00, 0x00, 0x03, 0xfc, 0x15, 0x2a,
+0x22, 0x80, 0x00, 0x3c, 0x00, 0x00, 0x00, 0xfc, 0x04, 0xaa,
+0x01, 0x20, 0x00, 0x3e, 0x00, 0x00, 0x01, 0x40, 0x12, 0x90,
+0x05, 0x20, 0x00, 0x1f, 0x00, 0x00, 0x10, 0x20, 0x09, 0x00,
+0x15, 0x00, 0x00, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x04, 0x00,
+0x55, 0x20, 0x00, 0x0f, 0x80, 0x00, 0x30, 0x00, 0x01, 0x02,
+0x2a, 0x00, 0x00, 0x07, 0xc0, 0x00, 0x60, 0x00, 0x00, 0x14,
+0x2a, 0x00, 0x00, 0x03, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x12,
+0x54, 0x00, 0x00, 0x00, 0x00, 0x01, 0xe0, 0x00, 0x00, 0x14,
+0x54, 0xa0, 0x00, 0x02, 0x00, 0x03, 0xf0, 0x00, 0x00, 0x2a,
+0x50, 0x00, 0x00, 0x01, 0x00, 0x0f, 0xe0, 0x00, 0x00, 0xaa,
+0xac, 0x00, 0x00, 0x01, 0xe0, 0xff, 0xf0, 0x00, 0x01, 0x6a,
+0x50, 0x40, 0x00, 0x02, 0xff, 0xff, 0xe0, 0x00, 0x82, 0xa8,
+0x94, 0x34, 0x00, 0x01, 0xff, 0xff, 0xf0, 0x00, 0x01, 0xa8,
+0x28, 0x85, 0xa0, 0x05, 0xff, 0xff, 0xe8, 0x08, 0x02, 0xa0,
+0x08, 0x40, 0x3d, 0x0b, 0xe0, 0x01, 0x74, 0x28, 0x45, 0x50,
+0x60, 0x82, 0x06, 0xef, 0x15, 0x08, 0x35, 0xa0, 0x0a, 0xa1,
+0x38, 0x40, 0x10, 0xfe, 0x50, 0x80, 0x1d, 0x60, 0x85, 0x50,
+0xc0, 0x82, 0xae, 0x38, 0x82, 0x00, 0x27, 0x88, 0x55, 0x42,
+0x50, 0x41, 0x21, 0x02, 0x49, 0x40, 0x50, 0x00, 0x25, 0x42,
+0x40, 0x00, 0x80, 0x09, 0x54, 0x80, 0x28, 0x00, 0x50, 0x02,
+0x50, 0x50, 0x40, 0x04, 0xaa, 0x00, 0x08, 0x14, 0x10, 0x02
+};
+
+#endif
+
diff -ruN linux-mips/include/asm-mips/mipsregs.h linux-vr/include/asm-mips/mipsregs.h
--- linux-mips/include/asm-mips/mipsregs.h	Fri Nov 10 00:11:53 2000
+++ linux-vr/include/asm-mips/mipsregs.h	Thu Nov 23 15:03:49 2000
@@ -76,9 +76,68 @@
 #define CP1_REVISION   $0
 #define CP1_STATUS     $31
 
+/* ++ kei ++*/
+#define FPU_CSR_FLUSH   0x01000000      /* flush denormalised results to 0 */
+#define FPU_CSR_COND    0x00800000      /* $fcc0 */
+#define FPU_CSR_COND0   0x00800000      /* $fcc0 */
+#define FPU_CSR_COND1   0x02000000      /* $fcc1 */
+#define FPU_CSR_COND2   0x04000000      /* $fcc2 */
+#define FPU_CSR_COND3   0x08000000      /* $fcc3 */
+#define FPU_CSR_COND4   0x10000000      /* $fcc4 */
+#define FPU_CSR_COND5   0x20000000      /* $fcc5 */
+#define FPU_CSR_COND6   0x40000000      /* $fcc6 */
+#define FPU_CSR_COND7   0x80000000      /* $fcc7 */
+
+/*
+ * X the exception cause indicator
+ * E the exception enable
+ * S the sticky/flag bit
+*/
+#define FPU_CSR_ALL_X 0x0003f000
+#define FPU_CSR_UNI_X   0x00020000
+#define FPU_CSR_INV_X   0x00010000
+#define FPU_CSR_DIV_X   0x00008000
+#define FPU_CSR_OVF_X   0x00004000
+#define FPU_CSR_UDF_X   0x00002000
+#define FPU_CSR_INE_X   0x00001000
+
+#define FPU_CSR_ALL_E   0x00000f80
+#define FPU_CSR_INV_E   0x00000800
+#define FPU_CSR_DIV_E   0x00000400
+#define FPU_CSR_OVF_E   0x00000200
+#define FPU_CSR_UDF_E   0x00000100
+#define FPU_CSR_INE_E   0x00000080
+
+#define FPU_CSR_ALL_S   0x0000007c
+#define FPU_CSR_INV_S   0x00000040
+#define FPU_CSR_DIV_S   0x00000020
+#define FPU_CSR_OVF_S   0x00000010
+#define FPU_CSR_UDF_S   0x00000008
+#define FPU_CSR_INE_S   0x00000004
+
+/* rounding mode */
+#define FPU_CSR_RN      0x0     /* nearest */
+#define FPU_CSR_RZ      0x1     /* towards zero */
+#define FPU_CSR_RU      0x2     /* towards +Infinity */
+#define FPU_CSR_RD      0x3     /* towards -Infinity */
+/* -- kei -- */
+
+#ifdef __KERNEL__
+/* Only use config.h if compiling kernel.
+ * Others will have to #define CONFIG_CPU_VR41XX if necessary.  bdl */
+#include <linux/config.h>
+#endif
+
 /*
  * Values for PageMask register
  */
+#ifdef CONFIG_CPU_VR41XX
+#define PM_1K   0x00000000
+#define PM_4K   0x00001800
+#define PM_16K  0x00007800
+#define PM_64K  0x0001f800
+#define PM_256K 0x0007f800
+#else
 #define PM_4K   0x00000000
 #define PM_16K  0x00006000
 #define PM_64K  0x0001e000
@@ -86,6 +145,8 @@
 #define PM_1M   0x001fe000
 #define PM_4M   0x007fe000
 #define PM_16M  0x01ffe000
+#endif
+
 
 /*
  * Values used for computation of new tlb entries
@@ -179,6 +240,7 @@
 	return res;                                             \
 }
 
+__BUILD_SET_CP0(conf,CP0_CONF)
 __BUILD_SET_CP0(status,CP0_STATUS)
 __BUILD_SET_CP0(cause,CP0_CAUSE)
 __BUILD_SET_CP0(config,CP0_CONFIG)
@@ -284,6 +346,28 @@
 #define  CAUSEF_CE		(3   << 28)
 #define  CAUSEB_BD		31
 #define  CAUSEF_BD		(1   << 31)
+
+/*
+ * Bits in the r39xx configuration register (register #3)
+ */
+
+#define CONFB_ICS               19
+#define CONFF_ICS               (7 << 19)
+#define CONFB_DCS               16
+#define CONFF_DCS               (7 << 16)
+#define CONFB_RF                10
+#define CONFF_RF                (3 << 10)
+#define CONFB_DOZE              9
+#define CONFB_HALT              8
+#define CONFB_LOCK              7
+#define CONFB_DCBR              6
+#define CONFB_ICE               5
+#define CONFB_DCE               4
+#define CONFB_IRSIZE            2
+#define CONFF_IRSIZE            (3 << 2)
+#define CONFB_DRSIZE            0
+#define CONFF_DRSIZE            (3 << 0)
+
 
 /*
  * Bits in the coprozessor 0 config register.
diff -ruN linux-mips/include/asm-mips/mmu_context.h linux-vr/include/asm-mips/mmu_context.h
--- linux-mips/include/asm-mips/mmu_context.h	Mon Sep 11 23:53:14 2000
+++ linux-vr/include/asm-mips/mmu_context.h	Tue Sep 19 07:39:49 2000
@@ -19,7 +19,7 @@
 extern unsigned long asid_cache;
 extern pgd_t *current_pgd;
 
-#if defined(CONFIG_CPU_R3000)
+#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_R39XX)
 
 #define ASID_INC	0x40
 #define ASID_MASK	0xfc0
diff -ruN linux-mips/include/asm-mips/pci.h linux-vr/include/asm-mips/pci.h
--- linux-mips/include/asm-mips/pci.h	Fri Nov 10 00:11:55 2000
+++ linux-vr/include/asm-mips/pci.h	Thu Nov 23 15:05:44 2000
@@ -201,6 +201,16 @@
 #endif
 }
 
+/* Return whether the given PCI device DMA address mask can
+ * be supported properly.  For example, if your device can
+ * only drive the low 24-bits during PCI bus mastering, then
+ * you would pass 0x00ffffff as the mask to this function.
+ */
+extern inline int pci_dma_supported(struct pci_dev *hwdev, dma_addr_t mask)
+{
+        return 1;
+}
+
 /*
  * These macros should be used after a pci_map_sg call has been done
  * to get bus addresses of each of the SG entries and their lengths.
diff -ruN linux-mips/include/asm-mips/pgtable.h linux-vr/include/asm-mips/pgtable.h
--- linux-mips/include/asm-mips/pgtable.h	Fri Nov 10 00:11:57 2000
+++ linux-vr/include/asm-mips/pgtable.h	Thu Nov 23 15:03:49 2000
@@ -116,7 +116,7 @@
 #define _PAGE_ACCESSED              (1<<3)  /* implemented in software */
 #define _PAGE_MODIFIED              (1<<4)  /* implemented in software */
 
-#if defined(CONFIG_CPU_R3000)
+#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_R39XX)
 
 #define _PAGE_GLOBAL                (1<<8)
 #define _PAGE_VALID                 (1<<9)
@@ -305,7 +305,11 @@
  * is simple.
  */
 #define page_address(page)	((page)->virtual)
+#ifdef CONFIG_CPU_VR41XX
+#define pte_page(x)		(mem_map+(unsigned long)((pte_val(x) >> (PAGE_SHIFT + 2))))
+#else
 #define pte_page(x)		(mem_map+(unsigned long)((pte_val(x) >> PAGE_SHIFT)))
+#endif
 
 /*
  * The following only work if pte_present() is true.
@@ -376,6 +380,17 @@
  * Conversion functions: convert a page and protection to a page entry,
  * and a page entry and page directory to the page they refer to.
  */
+#ifdef CONFIG_CPU_VR41XX
+#define mk_pte(page, pgprot)						\
+({									\
+	pte_t   __pte;							\
+									\
+	pte_val(__pte) = ((unsigned long)(page - mem_map) << (PAGE_SHIFT + 2)) | \
+	                 pgprot_val(pgprot);				\
+									\
+	__pte;								\
+})
+#else
 #define mk_pte(page, pgprot)						\
 ({									\
 	pte_t   __pte;							\
@@ -385,10 +400,15 @@
 									\
 	__pte;								\
 })
+#endif
 
 extern inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot)
 {
+#ifdef CONFIG_CPU_VR41XX
+	return __pte((physpage << 2) | pgprot_val(pgprot));
+#else
 	return __pte(physpage | pgprot_val(pgprot));
+#endif
 }
 
 extern inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
diff -ruN linux-mips/include/asm-mips/power.h linux-vr/include/asm-mips/power.h
--- linux-mips/include/asm-mips/power.h	Wed Dec 31 16:00:00 1969
+++ linux-vr/include/asm-mips/power.h	Sun Mar 26 23:24:39 2000
@@ -0,0 +1,24 @@
+/*
+ * power.h - Common power management defines
+ *
+ * Copyright (C) 2000 Michael Klar
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ */
+
+#ifndef __ASM_POWER_H
+#define __ASM_POWER_H
+
+#ifndef _LANGUAGE_ASSEMBLY
+extern unsigned int powerevent_queued;
+extern unsigned int hibernation_state;
+#endif
+
+#define LOAD_MAGIC (('L'<<24) | ('O'<<16) | ('A'<<8) | 'D')
+#define HIB_MAGIC ((' '<<24) | ('H'<<16) | ('I'<<8) | 'B')
+#define RUN_MAGIC ((' '<<24) | ('R'<<16) | ('U'<<8) | 'N')
+
+#endif /* __ASM_POWER_H */
diff -ruN linux-mips/include/asm-mips/processor.h linux-vr/include/asm-mips/processor.h
--- linux-mips/include/asm-mips/processor.h	Mon Sep 11 23:53:15 2000
+++ linux-vr/include/asm-mips/processor.h	Thu Nov 23 15:03:49 2000
@@ -102,11 +102,15 @@
 	unsigned int control;
 } __attribute__((aligned(8)));
 
+
+typedef unsigned long long fpureg_t;
+
 /*
  * FIXME: no fpu emulator yet (but who cares anyway?)
  */
 struct mips_fpu_soft_struct {
-	long	dummy;
+	fpureg_t        regs[NUM_FPU_REGS];
+	unsigned int sr;
 };
 
 union mips_fpu_union {
@@ -148,6 +152,24 @@
 	mm_segment_t current_ds;
 	unsigned long irix_trampoline;  /* Wheee... */
 	unsigned long irix_oldctx;
+
+	/*
+	* These are really only needed if the full FPU emulator
+	* is configured.  Would be made conditional on
+	* MIPS_FPU_EMULATOR if it weren't for the fact that
+	* having offset.h rebuilt differently for different
+	* config options would be asking for trouble.
+	*/
+
+	/*
+	* Saved EPC during delay-slot emulation (see math-emu/cp1emu.c)
+	*/
+	unsigned long dsemul_epc;
+
+	/*
+	* Pointer to instruction used to induce address error
+	*/
+	unsigned long dsemul_aerpc;
 };
 
 #endif /* !defined (_LANGUAGE_ASSEMBLY) */
@@ -177,6 +199,11 @@
 	 * For now the default is to fix address errors \
 	 */ \
 	MF_FIXADE, { 0 }, 0, 0 \
+	/* \
+	* dsemul_epc and dsemul_aerpc should never be used uninitialized, 
+	* but... \
+	*/ \
+	, 0, 0 \
 }
 
 #ifdef __KERNEL__
diff -ruN linux-mips/include/asm-mips/r39xx.h linux-vr/include/asm-mips/r39xx.h
--- linux-mips/include/asm-mips/r39xx.h	Wed Dec 31 16:00:00 1969
+++ linux-vr/include/asm-mips/r39xx.h	Thu Nov 23 15:11:59 2000
@@ -0,0 +1,721 @@
+/* $Id: r39xx.h,v 1.17 2000/11/17 21:57:18 pavel Exp $
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __R39XX_H__
+#define __R39XX_H__
+
+#include <asm/addrspace.h>
+ 
+/******************************************************************************
+*
+* 	01  General macro definitions
+*
+******************************************************************************/
+
+#define REGISTER_BASE   0xb0c00000
+
+#ifndef _LANGUAGE_ASSEMBLY
+
+	#define REG_AT(x)	(*((volatile unsigned long *)(REGISTER_BASE + x)))
+
+#else
+
+	#define REG_AT(x)   (REGISTER_BASE + x)
+
+#endif
+
+#define BIT(x)	(1 << x)
+
+/******************************************************************************
+*
+* 	02  Bus Interface Unit
+*
+******************************************************************************/
+
+#define MemConfig0    REG_AT(0x000)
+#define MemConfig1    REG_AT(0x004)
+#define MemConfig2    REG_AT(0x008)
+#define MemConfig3    REG_AT(0x00c)
+#define MemConfig4    REG_AT(0x010)
+#define MemConfig5    REG_AT(0x014)
+#define MemConfig6    REG_AT(0x018)
+#define MemConfig7    REG_AT(0x01c)
+#define MemConfig8    REG_AT(0x020)
+
+/* Memory config register 1 */
+
+#define MEM1_ENCS1USER	BIT(21)
+
+/* Memory config register 3 */
+
+#define MEM3_CARD1ACCVAL_MASK	(BIT(24) | BIT(25) | BIT(26) | BIT(27))
+#define MEM3_CARD1IOEN		BIT(4)
+
+/* Memory config register 4 */
+
+#define MEM4_ARBITRATIONEN	BIT(29)
+#define MEM4_MEMPOWERDOWN	BIT(16)
+#define MEM4_ENREFRESH1		BIT(15)
+#define MEM4_ENREFRESH0		BIT(14)
+
+#define MEM4_ENWATCH            BIT(24)
+#define MEM4_WATCHTIMEVAL_MASK  (0xf)
+#define MEM4_WATCHTIMEVAL_SHIFT (20)
+
+#define MEM4_WATCHTIME_VALUE    (0xf)
+
+
+/******************************************************************************
+*
+*	06  Clock module
+*
+******************************************************************************/
+
+#define ClockControl  	REG_AT(0x1C0)
+
+#define CLK_CHICLKDIV_MASK    0xff000000
+#define CLK_CHICLKDIV_SHIFT   24
+#define CLK_ENCLKTEST         BIT(23)
+#define CLK_CLKTESTSELSIB     BIT(22)
+#define CLK_CHIMCLKSEL        BIT(21)
+#define CLK_CHICLKDIR	      BIT(20)
+#define CLK_ENCHIMCLK	      BIT(19)
+#define CLK_ENVIDCLK	      BIT(18)
+#define CLK_ENMBUSCLK         BIT(17)
+#define CLK_ENSPICLK	      BIT(16)
+#define CLK_ENTIMERCLK	      BIT(15)
+#define CLK_ENFASTTIMERCLK    BIT(14)
+#define CLK_SIBMCLKDIR	      BIT(13)
+#define CLK_ENSIBMCLK	      BIT(11)
+#define CLK_SIBMCLKDIV_MASK   (BIT(10) | BIT(9) | BIT(8))
+#define CLK_SIBMCLKDIV_SHIFT  8
+#define CLK_CSERSEL	      BIT(7)
+#define CLK_CSERDIV_MASK      (BIT(6) | BIT(5) | BIT(4))
+#define CLK_CSERDIV_SHIFT     4
+#define CLK_ENCSERCLK	      BIT(3)
+#define CLK_ENIRCLK           BIT(2)
+#define CLK_EN_UART_A	      BIT(1)
+#define CLK_EN_UART_B	      BIT(0)
+
+
+/******************************************************************************
+*
+* 	07  CHI module
+*
+******************************************************************************/
+
+#define CHIControl		REG_AT(0x1D8)
+#define CHIPointerEnable	REG_AT(0x1DC)
+#define CHIReceivePtrA		REG_AT(0x1E0)
+#define CHIReceivePtrB		REG_AT(0x1E4)
+#define CHITransmitPtrA		REG_AT(0x1E8)
+#define CHITransmitPtrB		REG_AT(0x1EC)
+#define CHISize			REG_AT(0x1F0)
+#define CHIReceiveStart		REG_AT(0x1F4)
+#define CHITransmitStart	REG_AT(0x1F8)
+#define CHIHoldingReg		REG_AT(0x1FC)
+
+/* CHI Control Register */
+/* <incomplete!> */
+#define	CHI_RXEN		BIT(2)
+#define	CHI_TXEN		BIT(1)
+#define	CHI_ENCHI		BIT(0)
+
+
+/******************************************************************************
+*
+*	08  Interrupt module
+*
+******************************************************************************/
+
+/* Register locations */
+
+#define IntStatus1    REG_AT(0x100)
+#define IntStatus2    REG_AT(0x104)
+#define IntStatus3    REG_AT(0x108)
+#define IntStatus4    REG_AT(0x10c)
+#define IntStatus5    REG_AT(0x110)
+#define IntStatus6    REG_AT(0x114)
+
+#define IntClear1     REG_AT(0x100)
+#define IntClear2     REG_AT(0x104)
+#define IntClear3     REG_AT(0x108)
+#define IntClear4     REG_AT(0x10c)
+#define IntClear5     REG_AT(0x110)
+#define IntClear6     REG_AT(0x114)
+
+#define IntEnable1    REG_AT(0x118)
+#define IntEnable2    REG_AT(0x11c)
+#define IntEnable3    REG_AT(0x120)
+#define IntEnable4    REG_AT(0x124)
+#define IntEnable5    REG_AT(0x128)
+#define IntEnable6    REG_AT(0x12c)
+
+/* Interrupt Status Register 1 at offset 100 */
+#define INT1_LCDINT		BIT(31)
+#define INT1_DFINT              BIT(30)
+#define INT1_CHIDMAHALF		BIT(29)
+#define INT1_CHIDMAFULL		BIT(28)
+#define INT1_CHIDMACNTINT       BIT(27)
+#define INT1_CHIRXAINT		BIT(26)
+#define INT1_CHIRXBINT		BIT(25)
+#define INT1_CHIACTINT          BIT(24)
+#define INT1_CHIERRINT          BIT(23)
+#define INT1_SND0_5INT          BIT(22)
+#define INT1_SND1_0INT		BIT(21)
+#define INT1_TEL0_5INT          BIT(20)
+#define INT1_TEL1_0INT          BIT(19)
+#define INT1_SNDDMACNTINT       BIT(18)
+#define INT1_TELDMACNTINT       BIT(17)
+#define INT1_LSNDCLIPINT        BIT(16)
+#define INT1_RSNDCLIPINT        BIT(15)
+#define INT1_VALSNDPOSINT       BIT(14)
+#define INT1_VALSNDNEGINT       BIT(13)
+#define INT1_VALTELPOSINT       BIT(12)
+#define INT1_VALTELNEGINT       BIT(11)
+#define INT1_SNDININT           BIT(10)
+#define INT1_TELININT           BIT(9)
+#define INT1_SIBSF0INT          BIT(8)
+#define INT1_SIBSF1INT          BIT(7)
+#define INT1_SIBIRQPOSINT       BIT(6)
+#define INT1_SIBIRQNEGINT       BIT(5)
+
+/* Interrupt Status Register 2 at offset 104 */
+#define INT2_UARTARXINT		BIT(31)
+#define INT2_UARTARXOVERRUN	BIT(30)
+#define INT2_UARTAFRAMEINT	BIT(29)
+#define INT2_UARTABREAKINT	BIT(28)
+#define INT2_UARTATXINT		BIT(26)
+#define INT2_UARTATXOVERRUN	BIT(25)
+#define INT2_UARTAEMPTY		BIT(24)
+
+#define INT2_UARTBRXINT		BIT(21)
+#define INT2_UARTBRXOVERRUN	BIT(20)
+#define INT2_UARTBFRAMEINT	BIT(29)
+#define INT2_UARTBBREAKINT	BIT(18)
+#define INT2_UARTBTXINT		BIT(16)
+#define INT2_UARTBTXOVERRUN	BIT(15)
+#define INT2_UARTBEMPTY		BIT(14)
+
+#define INT2_UARTA_RX		(BIT(31) | BIT(30) | BIT(29) | BIT(28) | BIT(27))
+#define INT2_UARTA_TX		(BIT(26) | BIT(25) | BIT(24))
+#define INT2_UARTA_DMA		(BIT(23) | BIT(22))
+
+#define INT2_UARTB_RX		(BIT(21) | BIT(20) | BIT(19) | BIT(18) | BIT(17))
+#define INT2_UARTB_TX		(BIT(16) | BIT(15) | BIT(14))
+#define INT2_UARTB_DMA		(BIT(13) | BIT(12))
+
+/* Interrupt Status Register 5 */
+#define INT5_RTCINT	 BIT(31)
+#define INT5_ALARMINT	 BIT(30)
+#define INT5_PERIODICINT BIT(29)
+#define INT5_POSPWRINT 	 BIT(27)
+#define INT5_NEGPWRINT	 BIT(26)
+#define INT5_POSPWROKINT BIT(25)
+#define INT5_NEGPWROKINT BIT(24)
+#define INT5_POSONBUTINT BIT(23)
+#define INT5_NEGONBUTINT BIT(22)
+#define INT5_SPIAVAILINT BIT(21)
+#define INT5_SPIRCVINT	 BIT(19)
+#define INT5_SPIEMPTYINT BIT(18)
+#define INT5_IOPOSINT6	 BIT(13)
+#define INT5_IOPOSINT5	 BIT(12)
+#define INT5_IOPOSINT4	 BIT(11)
+#define INT5_IOPOSINT3	 BIT(10)
+#define INT5_IOPOSINT2	 BIT(9)
+#define INT5_IOPOSINT1	 BIT(8)
+#define INT5_IOPOSINT0	 BIT(7)
+#define INT5_IONEGINT6	 BIT(6)
+#define INT5_IONEGINT5	 BIT(5)
+#define INT5_IONEGINT4	 BIT(4)
+#define INT5_IONEGINT3	 BIT(3)
+#define INT5_IONEGINT2	 BIT(2)
+#define INT5_IONEGINT1	 BIT(1)
+#define INT5_IONEGINT0	 BIT(0)
+
+#define INT5_IONEGINT_SHIFT 0
+#define	INT5_IONEGINT_MASK  (0x7F<<INT5_IONEGINT_SHIFT)
+#define INT5_IOPOSINT_SHIFT 7
+#define	INT5_IOPOSINT_MASK  (0x7F<<INT5_IOPOSINT_SHIFT)
+
+/* Interrupt Status Register 6 */
+#define INT6_IRQHIGH	BIT(31)
+#define INT6_IRQLOW	BIT(30)
+#define INT6_INTVECT	(BIT(5) | BIT(4) | BIT(3) | BIT(2))
+
+
+/* Interrupt Enable Register 6 */
+#define INT6_GLOBALEN		BIT(18)
+#define INT6_PWROKINT		BIT(15)
+#define	INT6_ALARMINT		BIT(14)
+#define INT6_PERIODICINT 	BIT(13)
+#define	INT6_MBUSINT		BIT(12)
+#define INT6_UARTARXINT		BIT(11)
+#define INT6_UARTBRXINT		BIT(10)
+#define	INT6_MFIOPOSINT1619	BIT(9)
+#define INT6_IOPOSINT56         BIT(8)
+#define	INT6_MFIONEGINT1619	BIT(7)
+#define INT6_IONEGINT56         BIT(6)
+#define	INT6_MBUSDMAFULLINT	BIT(5)
+#define	INT6_SNDDMACNTINT	BIT(4)
+#define	INT6_TELDMACNTINT	BIT(3)
+#define	INT6_CHIDMACNTINT	BIT(2)
+#define INT6_IOPOSNEGINT0       BIT(1)
+
+
+/******************************************************************************
+*
+*	09  GPIO and MFIO modules
+*
+******************************************************************************/
+
+#define IOControl   	REG_AT(0x180)
+#define MFIOOutput   	REG_AT(0x184)
+#define MFIODirection  	REG_AT(0x188)
+#define MFIOInput  	REG_AT(0x18c)
+#define MFIOSelect   	REG_AT(0x190)
+#define IOPowerDown   	REG_AT(0x194)
+#define MFIOPowerDown  	REG_AT(0x198)
+
+#define IODIN_MASK      0x0000007f
+#define IODIN_SHIFT     0
+#define IODOUT_MASK     0x00007f00
+#define IODOUT_SHIFT    8
+#define IODIREC_MASK    0x007f0000
+#define IODIREC_SHIFT   16
+#define IODEBSEL_MASK   0x7f000000
+#define IODEBSEL_SHIFT  24
+
+/*
+ * Helio specific.  Obviously awaiting platform-identificiation.
+ */
+
+#ifdef CONFIG_VTECH_HELIO
+   /* These were checked against the VT-OS SDK includes */
+
+   /* IO pins */
+
+   #define IO_PIN_KEY_STOP          BIT(6)  # 174 (6) KeyStop
+   #define IO_PIN_KEY_PLAY          BIT(5)  # 175 (5) PlaySoundKey
+   #define IO_PIN_KEY_UP            BIT(4)  # 177 (4) KeyUp
+   #define IO_PIN_KEY_DOWN          BIT(3)  # 176 (3) KeyDown
+   #define IO_PIN_KEY_BTN_3         BIT(2)  # 178 (2) IOCtrl
+   #define IO_PIN_KEY_BTN_2         BIT(1)  # 179 (1) IOCtrl
+   #define IO_PIN_KEY_BTN_1         BIT(0)  # 180 (0) IOCtrl
+
+   /* Multi-Function IO pins */
+
+   #define MFIO_PIN_IO_KEY8         BIT(0)	// input (RecordKey)
+   #define MFIO_PIN_MODEM_CTS       BIT(2)	// input
+   #define MFIO_PIN_LCD_POWER       BIT(3)	// output
+   #define MFIO_PIN_MODEM_RTS       BIT(4)	// output
+   #define MFIO_PIN_AUDIO_DISABLE   BIT(6)	// output
+   #define MFIO_PIN_BAT_DOOR        BIT(8)	// input
+   #define MFIO_PIN_EL              BIT(9)	// output
+   #define MFIO_PIN_BACKLIGHT       BIT(9)	// output (alias for EL)
+   #define MFIO_PIN_UART_TX_ENABLE  BIT(10)	// output
+   #define MFIO_PIN_UART_RX_DISABLE BIT(16)	// output
+   #define MFIO_PIN_DIAGNOSTIC      BIT(19)	// input
+   #define MFIO_PIN_POWER_ON        BIT(23)	// input
+   #define MFIO_PIN_HOTSYNC_KEY     BIT(25)	// input
+
+/* 
+
+   Don't trust these yet, they seem to be on the
+   keyboard/telecom connector, but since we don't have
+   such a beast, we really can't tell.
+
+   #define MFIO_PIN_ONHOOK          BIT(5)	// output
+   #define MFIO_PIN_FLASH_RDY       BIT(7)	// input
+   #define MFIO_PIN_TRING           BIT(11) 	// output
+   #define MFIO_PIN_SIO_DATA_IN     BIT(13)	// input
+   #define MFIO_PIN_SIO_DATA_OUT    BIT(14)	// output
+   #define MFIO_PIN_SIO_CLK         BIT(15)	// output
+   #define MFIO_PIN_SIO_DATA_RDY    BIT(28)	// input
+   #define MFIO_PIN_SIO_CS          BIT(29)	// output
+   #define MFIO_PIN_SIO_DEVDET      BIT(30)	// input
+   #define MFIO_PIN_SIO_DEVDET_PWR  BIT(31)	// output
+
+*/
+
+#endif
+
+#ifdef CONFIG_SHARP_MOBILON
+#define MFIO_PIN_PCMCIA_IRQ	 BIT(2)
+#endif
+
+#ifdef CONFIG_PHILIPS_VELO
+/* These are guessed from my philips velo 1. I hope they are same on other models -- pavel@ucw.cz.
+   If you are reading this take a look at analysis at http://atrey.karlin.mff.cuni.cz/~pavel/velo/.
+ */
+/* BIT(0) is unknown input */
+#define MFIO_PIN_KEYBOARD        BIT(1)	/* On keypress this goes up and down */
+#define MFIO_PIN_RESET_MOTOROLA  BIT(2)	/* Not really sure */
+/* BIT(3) is unknown input */
+#define MFIO_PIN_IRDA_UNKNOWN1   BIT(4) /* 0 when irda is in use? */
+#define MFIO_PIN_IRDA_UNKNOWN2   BIT(5) /* same as unknown1? */
+/* BIT(6) is input, it changes on pressing spacebar or arrow down */
+/* BIT(7) is unknown output */
+/* BIT(8) is unkonwn output */
+/* BIT(9) is unkonwn output */
+/* BIT(10) is unkonwn output */
+/* BIT(11) is unkonwn output */
+#define MFIO_PIN_HOTSYNC_KEY	 BIT(12) /* It is Mic button, in fact, hopefully it is more usefull this way */
+/* BIT(13) changes when DTR from host changes (or not?) */
+/* BIT(14) changes from time to time; it definitely has *something* to do with serial */
+/* BIT(15) is unknown input */
+#define MFIO_PIN_ONHOOK          BIT(16) /* This may well be power to serial port. I'm not sure. It does only 8mA difference. */
+#define MFIO_PIN_LCD_POWER	 BIT(17)
+#define MFIO_PIN_SERIAL_UNKNOWN	 BIT(18) /* Strange bit, power for serial? */ 
+/* BIT(19) is unknown output */
+/* BIT(20) is unknown output */
+/* BIT(21)..BIT(24) are unknown inputs */
+#define MFIO_PIN_BACKLIGHT       BIT(25)
+#define MFIO_PIN_RESET_BETTY     BIT(26) /* wild guess */
+/* BIT(27) is unknown input */
+/* BIT(28) is output, power consumption goes up by 46mA */
+/* BIT(29) is unknown output */
+#define MFIO_PIN_MODEM_RTS	 BIT(30) /* input pin, got from RTS signal on host;  I hope I have naming right */
+#define MFIO_PIN_MODEM_CTS       BIT(31) /* output pin playing with CTS signal on host; I hope I have naming right */
+#endif
+
+
+/******************************************************************************
+*
+*	10  IR module
+*
+******************************************************************************/
+
+#define IRControl1                  REG_AT(0x0a0)
+#define IRControl2                  REG_AT(0x0a4)
+
+/* IR Control 1 Register */
+
+#define IR_CARDRET                  BIT(24)
+#define IR_BAUDVAL_MASK             0x00ff0000
+#define IR_BAUDVAL_SHIFT            16
+#define IR_TESTIR                   BIT(4)
+#define IR_DTINVERT                 BIT(3)
+#define IR_RXPWR                    BIT(2)
+#define IR_ENSTATE                  BIT(1)
+#define IR_ENCONSM                  BIT(0)
+
+/* IR Control 2 Register */
+
+#define IR_PER_MASK                 0xff000000
+#define IR_PER_SHIFT                24
+#define IR_ONTIME_MASK              0x00ff0000
+#define IR_ONTIME_SHIFT             16
+#define IR_DELAYVAL_MASK            0x0000ff00
+#define IR_DELAYVAL_SHIFT           8
+#define IR_WAITVAL_MASK             0x000000ff
+#define IR_WAITVAL_SHIFT            0
+
+
+/******************************************************************************
+*
+*	11  Magicbus Module
+*
+******************************************************************************/
+
+#define MbusCntrl1		REG_AT(0x0e0)
+#define MbusCntrl2		REG_AT(0x0e4)
+#define MbusDMACntrl1		REG_AT(0x0e8)
+#define MbusDMACntrl2		REG_AT(0x0ec)
+#define MbusDMACount		REG_AT(0x0f0)
+#define MbusTxReg		REG_AT(0x0f4)
+#define MbusRxReg		REG_AT(0x0f8)
+
+#define	MBUS_CLKPOL		BIT(4)
+#define	MBUS_SLAVE		BIT(3)
+#define	MBUS_FSLAVE		BIT(2)
+#define	MBUS_LONG		BIT(1)
+#define	MBUS_ENMBUS		BIT(0)
+
+
+/******************************************************************************
+*
+*	12  Power module
+*
+******************************************************************************/
+
+#define PowerControl   	            REG_AT(0x1C4)
+
+#define PWR_ONBUTN                  BIT(31)
+#define PWR_PWRINT                  BIT(30)
+#define PWR_PWROK                   BIT(29)
+#define PWR_VIDRF_MASK              (BIT(28) | BIT(27))
+#define PWR_VIDRF_SHIFT             27
+#define PWR_SLOWBUS                 BIT(26)
+#define PWR_DIVMOD                  BIT(25)
+#define PWR_STPTIMERVAL_MASK        (BIT(15) | BIT(14) | BIT(13) | BIT(12))
+#define PWR_STPTIMERVAL_SHIFT       12
+#define PWR_ENSTPTIMER              BIT(11)
+#define PWR_ENFORCESHUTDWN          BIT(10)
+#define PWR_FORCESHUTDWN            BIT(9)
+#define PWR_FORCESHUTDWNOCC         BIT(8)
+#define PWR_SELC2MS                 BIT(7)
+#define PWR_BPDBVCC3                BIT(5)
+#define PWR_STOPCPU                 BIT(4)
+#define PWR_DBNCONBUTN              BIT(3)
+#define PWR_COLDSTART               BIT(2)
+#define PWR_PWRCS                   BIT(1)
+#define PWR_VCCON                   BIT(0)
+
+/******************************************************************************
+*
+*	13  SIB (Serial Interconnect Bus) Module
+*
+******************************************************************************/
+
+/* Register locations */
+
+#define SIBSize	      	        REG_AT(0x060)
+#define SIBSoundRXStart	      	REG_AT(0x064)
+#define SIBSoundTXStart         REG_AT(0x068)
+#define SIBTelecomRXStart       REG_AT(0x06C)
+#define SIBTelecomTXStart       REG_AT(0x070)
+#define SIBControl              REG_AT(0x074)
+#define SIBSoundTXRXHolding     REG_AT(0x078)
+#define SIBTelecomTXRXHolding   REG_AT(0x07C)
+#define SIBSubFrame0Control     REG_AT(0x080)
+#define SIBSubFrame1Control     REG_AT(0x084)
+#define SIBSubFrame0Status      REG_AT(0x088)
+#define SIBSubFrame1Status      REG_AT(0x08C)
+#define SIBDMAControl           REG_AT(0x090)
+
+/* SIB Size Register */
+
+#define SIB_SNDSIZE_MASK        0x3ffc0000
+#define SIB_SNDSIZE_SHIFT       18
+#define SIB_TELSIZE_MASK        0x00003ffc
+#define SIB_TELSIZE_SHIFT       2
+
+/* SIB Control Register */
+
+#define SIB_SIBIRQ              BIT(31)
+#define SIB_ENCNTTEST           BIT(30)
+#define SIB_ENDMATEST           BIT(29)
+#define SIB_SNDMONO             BIT(28)
+#define SIB_RMONOSNDIN          BIT(27)
+#define SIB_SIBSCLKDIV_MASK     (BIT(26) | BIT(25) | BIT(24))
+#define SIB_SIBSCLKDIV_SHIFT    24
+#define SIB_TEL16               BIT(23)
+#define SIB_TELFSDIV_MASK       0x007f0000
+#define SIB_TELFSDIV_SHIFT      16
+#define SIB_SND16               BIT(15)
+#define SIB_SNDFSDIV_MASK       0x00007f00
+#define SIB_SNDFSDIV_SHIFT      8
+#define SIB_SELTELSF1           BIT(7)
+#define SIB_SELSNDSF1           BIT(6)
+#define SIB_ENTEL               BIT(5)
+#define SIB_ENSND               BIT(4)
+#define SIB_SIBLOOP             BIT(3)
+#define SIB_ENSF1               BIT(2)
+#define SIB_ENSF0               BIT(1)
+#define SIB_ENSIB               BIT(0)
+
+/* SIB Frame Format (SIBSubFrame0Status and SIBSubFrame1Status) */
+
+#define SIB_REGISTER_EXT        BIT(31)  /* Must be zero */
+#define SIB_ADDRESS_MASK        0x78000000
+#define SIB_ADDRESS_SHIFT       27
+#define SIB_WRITE               BIT(26)
+#define SIB_AUD_VALID           BIT(17)
+#define SIB_TEL_VALID           BIT(16)
+#define SIB_DATA_MASK           0x00ff
+#define SIB_DATA_SHIFT          0
+
+/* SIB DMA Control Register */
+
+#define SIB_SNDBUFF1TIME        BIT(31)
+#define SIB_SNDDMALOOP          BIT(30)
+#define SIB_SNDDMAPTR_MASK      0x3ffc0000
+#define SIB_SNDDMAPTR_SHIFT     18
+#define SIB_ENDMARXSND          BIT(17)
+#define SIB_ENDMATXSND          BIT(16)
+#define SIB_TELBUFF1TIME        BIT(15)
+#define SIB_TELDMALOOP          BIT(14)
+#define SIB_TELDMAPTR_MASK      0x00003ffc
+#define SIB_TELDMAPTR_SHIFT     2
+#define SIB_ENDMARXTEL          BIT(1)
+#define SIB_ENDMATXTEL          BIT(0)
+
+/******************************************************************************
+*
+* 	14  SPI module
+*
+******************************************************************************/
+
+#define SPIControl		REG_AT(0x160)
+#define SPITransmit		REG_AT(0x164)
+#define SPIReceive		REG_AT(0x164)
+
+#define SPI_SPION		BIT(17)
+#define SPI_EMPTY		BIT(16)
+#define SPI_DELAYVAL_MASK	(BIT(12) | BIT(13) | BIT(14) | BIT(15))
+#define SPI_DELAYVAL_SHIFT	12
+#define	SPI_BAUDRATE_MASK	(BIT(8) | BIT(9) | BIT(10) | BIT(11))
+#define	SPI_BAUDRATE_SHIFT	8
+#define	SPI_PHAPOL		BIT(5)
+#define	SPI_CLKPOL		BIT(4)
+#define	SPI_WORD		BIT(2)
+#define	SPI_LSB			BIT(1)
+#define	SPI_ENSPI		BIT(0)
+
+
+/******************************************************************************
+*
+*	15  Timer module
+*
+******************************************************************************/
+
+#define RTChigh	      	REG_AT(0x140)
+#define RTClow	        REG_AT(0x144)
+#define RTCalarmHigh    REG_AT(0x148)
+#define RTCalarmLow     REG_AT(0x14c)
+#define RTCtimerControl REG_AT(0x150)
+#define RTCperiodTimer  REG_AT(0x154)
+
+/* RTC Timer Control */
+#define TIM_FREEZEPRE	BIT(7)
+#define TIM_FREEZERTC	BIT(6)
+#define TIM_FREEZETIMER	BIT(5)
+#define TIM_ENPERTIMER	BIT(4)
+#define TIM_RTCCLEAR	BIT(3)
+
+#define	RTC_HIGHMASK	(0xFF)
+
+/* RTC Periodic Timer */
+#define	TIM_PERCNT	0xFFFF0000
+#define	TIM_PERVAL	0x0000FFFF
+
+/* For a system clock frequency of 36.864MHz, the timer counts at one tick
+   every 868nS (ie CLK/32). Therefore 11520 counts gives a 10mS interval
+ */
+
+#define PER_TIMER_COUNT (1152000/HZ)
+
+/******************************************************************************
+*
+*	16  UART module
+*
+******************************************************************************/
+
+#define UartA_Ctrl1   REG_AT(0x0b0)
+#define UartA_Ctrl2   REG_AT(0x0b4)
+#define UartA_DMActl1 REG_AT(0x0b8)
+#define UartA_DMActl2 REG_AT(0x0bc)
+#define UartA_DMAcnt  REG_AT(0x0c0)
+#define UartA_Data    REG_AT(0x0c4)
+#define UartB_Ctrl1   REG_AT(0x0c8)
+#define UartB_Ctrl2   REG_AT(0x0cc)
+#define UartB_DMActl1 REG_AT(0x0d0)
+#define UartB_DMActl2 REG_AT(0x0d4)
+#define UartB_DMAcnt  REG_AT(0x0d8)
+#define UartB_Data    REG_AT(0x0dc)
+
+/* bit allocations within UART control register 1 */
+ 
+#define UART_ON			BIT(31)	/* indicates status of UART */
+#define UART_TX_EMPTY		BIT(30)	/* tx holding and shift registers empty */
+#define UART_PRX_HOLD_FULL	BIT(29)	/* pre-rx holding register full */
+#define UART_RX_HOLD_FULL	BIT(28)	/* rx holding register is full */
+#define UART_EN_DMA_RX 		BIT(15)	/* enable rx DMA */
+#define UART_EN_DMA_TX 		BIT(14)	/* enable tx DMA */
+#define UART_BREAK_HALT 	BIT(12)	/* enable halt after receiving break */
+#define UART_DMA_LOOP		BIT(10)	/* enable DMA loop-roud */
+#define UART_PULSE_THREE	BIT(9)	/* tx data is 3 low pulses */
+#define UART_PULSE_SIX		BIT(8)	/* tx data is 6 low pulses */
+#define UART_DT_INVERT		BIT(7)	/* invert txd and rxd */
+#define UART_DIS_TXD		BIT(6)	/* set txd low */
+#define UART_LOOPBACK		BIT(4)	/* enable loopback mode */
+#define UART_ENABLE		BIT(0)	/* enable UART */
+		 
+#define SER_SEVEN_BIT		BIT(3)	/* use 7-bit data */
+#define SER_EIGHT_BIT		    0	/* use 8-bit data */
+#define SER_EVEN_PARITY 	(BIT(2) | BIT(1))	/* use even parity */
+#define SER_ODD_PARITY  	BIT(1)	/* use odd parity */
+#define SER_NO_PARITY		    0	/* enable parity checking */
+#define SER_TWO_STOP		BIT(5)	/* transmit 2 stop bits */
+#define SER_ONE_STOP		    0	/* transmit 1 stop bits */
+
+/* Baud rate definitions for UART control register 2 */
+
+#define SER_BAUD_230400	   ( 0)
+#define SER_BAUD_115200	   ( 1)
+#define SER_BAUD_76800	   ( 2)
+#define SER_BAUD_57600	   ( 3)
+#define SER_BAUD_38400     ( 5)		/* divisors are  3.6864MHz      */
+#define SER_BAUD_19200     (11)		/*		----------- - 1 */
+#ifdef CONFIG_VTECH_HELIO_EMULATOR
+#define SER_BAUD_9600      (23)
+#else  
+#define SER_BAUD_9600      (22)		/*		(baud * 16)     */
+#endif
+#define SER_BAUD_4800      (47)
+#define SER_BAUD_2400      (95)
+#define SER_BAUD_1200      (191)
+#define SER_BAUD_600       (383)
+#define SER_BAUD_300	   (767)
+
+
+/******************************************************************************
+*
+*	17  Video module
+*
+******************************************************************************/
+
+#define VidCtrl1	REG_AT(0x028)
+#define VidCtrl2	REG_AT(0x02C)
+#define VidCtrl3	REG_AT(0x030)
+#define VidCtrl4	REG_AT(0x034)
+#define VidCtrl5	REG_AT(0x038)
+#define VidCtrl6	REG_AT(0x03C)
+#define VidCtrl7	REG_AT(0x040)
+#define VidCtrl8	REG_AT(0x044)
+#define VidCtrl9	REG_AT(0x048)
+#define VidCtrl10	REG_AT(0x04C)
+#define VidCtrl11	REG_AT(0x050)
+#define VidCtrl12	REG_AT(0x054)
+#define VidCtrl13	REG_AT(0x058)
+#define VidCtrl14	REG_AT(0x05C)
+
+/* VidCtrl1 */
+#define LINECNT         0xffc00000
+#define LINECNT_SHIFT   22
+#define LOADDLY         BIT(21)
+#define BAUDVAL         (BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16))
+#define BAUDVAL_SHIFT   16
+#define VIDDONEVAL      (BIT(15) | BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10) | BIT(9))
+#define VIDDONEVAL_SHIFT  9
+#define ENFREEZEFRAME 	BIT(8)
+#define BITSEL_MASK	0xc0
+#define BITSEL_SHIFT	6
+#define DISPSPLIT       BIT(5)
+#define DISP8           BIT(4)
+#define DFMODE          BIT(3)
+#define INVVID          BIT(2)
+#define DISPON		BIT(1)
+#define ENVID		BIT(0)
+
+/* VidCtrl2 */
+#define VIDRATE_MASK    0xffc00000
+#define VIDRATE_SHIFT   22
+#define HORZVAL_MASK	0x001ff000
+#define HORZVAL_SHIFT	12
+#define LINEVAL_MASK	0x000001ff
+
+/* VidCtrl3 */
+#define VIDBANK_MASK	0xfff00000
+#define VIDBASEHI_MASK	0x000ffff0
+
+/* VidCtrl4 */
+#define VIDBASELO_MASK	0x000ffff0
+
+
+#endif
diff -ruN linux-mips/include/asm-mips/serial.h linux-vr/include/asm-mips/serial.h
--- linux-mips/include/asm-mips/serial.h	Fri Nov 10 00:12:04 2000
+++ linux-vr/include/asm-mips/serial.h	Thu Nov 23 15:11:29 2000
@@ -10,6 +10,7 @@
 #include <linux/config.h>
 #include <asm/bootinfo.h>
 #include <asm/jazz.h>
+#include <asm/vr41xx.h>
 
 /*
  * This assumes you have a 1.8432 MHz clock for your UART.
@@ -29,6 +30,8 @@
 #define JAZZ_BASE_BAUD BASE_BAUD
 #endif
 
+#define VR41XX_BASE_BAUD 1152000
+
 /* Standard COM flags (except for COM4, because of the 8514 problem) */
 #ifdef CONFIG_SERIAL_DETECT_IRQ
 #define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ)
@@ -76,6 +79,50 @@
 #define JAZZ_SERIAL_PORT_DEFNS
 #endif
 
+#ifdef CONFIG_CPU_VR41XX
+/* note: serial driver misbehaves if port == 0, even if port not used */
+#define _VR41XX_SERIAL_INIT(base, irqno)	\
+	{ type: PORT_16550A,			\
+	  baud_base: VR41XX_BASE_BAUD,		\
+	  port: (unsigned long)base,		\
+	  irq: irqno,				\
+	  flags: STD_COM_FLAGS,			\
+	  iomem_base: (unsigned char *)base,	\
+	  io_type: SERIAL_VADDR }
+
+#ifdef CONFIG_CPU_VR4122
+#define VR41XX_SERIAL_PORT_DEFNS			\
+	_VR41XX_SERIAL_INIT(VR41XX_SIURB, VR41XX_IRQ_SIU),	/* ttyS0 */ \
+	_VR41XX_SERIAL_INIT(VR41XX_SIURB, VR41XX_IRQ_SIU),	/* ttyS1 (IrDA) */
+#define MAX_VR_PORT 1
+#define SHARED_RS232_LINE 0
+#define SHARED_IRDA_LINE 1
+#else
+#ifdef CONFIG_CPU_VR4181
+
+#define VR41XX_SERIAL_PORT_DEFNS	\
+	_VR41XX_SERIAL_INIT(VR41XX_SIURB, VR41XX_IRQ_SIU),	/* ttyS0 */	\
+	_VR41XX_SERIAL_INIT(VR41XX_SIURB_2, VR41XX_IRQ_SIU),	/* ttyS1 (IrDA) */ \
+	_VR41XX_SERIAL_INIT(VR41XX_SIURB_2, VR41XX_IRQ_SIU),	/* ttyS2 */
+#define MAX_VR_PORT 2
+#define SHARED_RS232_LINE 2
+#define SHARED_IRDA_LINE 1
+
+#else	/* VR4121 and similar */
+
+#define VR41XX_SERIAL_PORT_DEFNS	\
+	_VR41XX_SERIAL_INIT(VR41XX_SIURB, VR41XX_IRQ_SIU),	/* ttyS0 */	\
+	_VR41XX_SERIAL_INIT(VR41XX_SIURB, VR41XX_IRQ_SIU),	/* ttyS1 (IrDA) */
+#define MAX_VR_PORT 1
+#define SHARED_RS232_LINE 0
+#define SHARED_IRDA_LINE 1
+#endif  /* CONFIG_CPU_VR4181 */
+#endif  /* CONFIG_CPU_VR4122 */
+
+#else	/* non-VR41xx */
+#define VR41XX_SERIAL_PORT_DEFNS
+#endif
+
 #ifdef CONFIG_MIPS_EV96100
 #include <asm/galileo-boards/ev96100.h>
 #include <asm/galileo-boards/ev96100int.h>
@@ -163,9 +210,19 @@
 #define MCA_SERIAL_PORT_DFNS
 #endif
 
+#ifdef CONFIG_NEC_HARRIER
+#define NEC_HARRIER_SERIAL_PORT_DFNS			\
+	{ 0, VR41XX_BASE_BAUD, (unsigned long)NEC_HARRIER_SIO1,  VR41XX_IRQ_SIO, STD_COM_FLAGS },	/* ttyS1 */ \
+	{ 0, VR41XX_BASE_BAUD, (unsigned long)NEC_HARRIER_SIO2,  VR41XX_IRQ_SIO, STD_COM_FLAGS },	/* ttyS2 */ 
+#else
+#define NEC_HARRIER_SERIAL_PORT_DFNS
+#endif
+
 #define SERIAL_PORT_DFNS		\
+	VR41XX_SERIAL_PORT_DEFNS	\
         EV96100_SERIAL_PORT_DEFNS       \
 	JAZZ_SERIAL_PORT_DEFNS		\
 	STD_SERIAL_PORT_DEFNS		\
 	EXTRA_SERIAL_PORT_DEFNS		\
-	HUB6_SERIAL_PORT_DFNS           
+	HUB6_SERIAL_PORT_DFNS		\
+	NEC_HARRIER_SERIAL_PORT_DFNS
diff -ruN linux-mips/include/asm-mips/stackframe.h linux-vr/include/asm-mips/stackframe.h
--- linux-mips/include/asm-mips/stackframe.h	Fri Nov 10 00:12:08 2000
+++ linux-vr/include/asm-mips/stackframe.h	Thu Nov 23 15:11:38 2000
@@ -144,7 +144,7 @@
 		lw	$23, PT_R23(sp);                 \
 		lw	$30, PT_R30(sp)
 
-#if defined(CONFIG_CPU_R3000)
+#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_R39XX)
 
 #define RESTORE_SOME                                     \
 		.set	push;                            \
diff -ruN linux-mips/include/asm-mips/unaligned.h linux-vr/include/asm-mips/unaligned.h
--- linux-mips/include/asm-mips/unaligned.h	Fri Nov 10 00:12:11 2000
+++ linux-vr/include/asm-mips/unaligned.h	Sun Nov 12 12:33:10 2000
@@ -9,6 +9,8 @@
 #ifndef _ASM_UNALIGNED_H
 #define _ASM_UNALIGNED_H
 
+#include <linux/types.h>
+
 extern void __get_unaligned_bad_length(void);
 extern void __put_unaligned_bad_length(void);
 
diff -ruN linux-mips/include/asm-mips/vr4121.h linux-vr/include/asm-mips/vr4121.h
--- linux-mips/include/asm-mips/vr4121.h	Wed Dec 31 16:00:00 1969
+++ linux-vr/include/asm-mips/vr4121.h	Wed Sep 13 08:25:13 2000
@@ -0,0 +1,478 @@
+/* $Id: vr4121.h,v 1.1 2000/06/05 01:30:57 brad Exp $
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1999 by Michael Klar
+ */
+#ifndef __ASM_MIPS_VR4121_H 
+#define __ASM_MIPS_VR4121_H 
+
+#include <asm/addrspace.h>
+
+// CPU interrupts
+#define VR41XX_IRQ_SW1       0  // IP0 - Software interrupt
+#define VR41XX_IRQ_SW2       1  // IP1 - Software interrupt
+#define VR41XX_IRQ_INT0      2  // IP2 - All but battery, high speed modem, and real time clock
+#define VR41XX_IRQ_INT1      3  // IP3 - RTC Long1 (system timer)
+#define VR41XX_IRQ_INT2      4  // IP4 - RTC Long2
+#define VR41XX_IRQ_INT3      5  // IP5 - High Speed Modem
+#define VR41XX_IRQ_INT4      6  // IP6 - Unused
+#define VR41XX_IRQ_TIMER     7  // IP7 - Timer interrupt from CPO_COMPARE (Note: RTC Long1 is the system timer.)
+
+// Cascaded from VR41XX_IRQ_INT0 (ICU mapped interrupts)
+#define VR41XX_IRQ_BATTERY   8
+#define VR41XX_IRQ_POWER     9
+#define VR41XX_IRQ_RTCL1     10  // Use VR41XX_IRQ_INT1 instead.
+#define VR41XX_IRQ_ETIMER    11
+#define VR41XX_IRQ_RFU12     12
+#define VR41XX_IRQ_PIU       13
+#define VR41XX_IRQ_AIU       14
+#define VR41XX_IRQ_KIU       15
+#define VR41XX_IRQ_GIU       16  // This is a cascade to IRQs 40-71. Do not use.
+#define VR41XX_IRQ_SIU       17
+#define VR41XX_IRQ_WRBERR    18
+#define VR41XX_IRQ_SOFT      19
+#define VR41XX_IRQ_RFU20     20
+#define VR41XX_IRQ_DOZEPIU   21
+#define VR41XX_IRQ_RFU22     22
+#define VR41XX_IRQ_RFU23     23
+#define VR41XX_IRQ_RTCL2     24  // Use VR41XX_IRQ_INT2 instead.
+#define VR41XX_IRQ_LED       25
+#define VR41XX_IRQ_HSP       26  // Use VR41XX_IRQ_INT3 instead.
+#define VR41XX_IRQ_TCLK      27
+#define VR41XX_IRQ_FIR       28
+#define VR41XX_IRQ_DSIU      29
+#define VR41XX_IRQ_RFU30     30
+#define VR41XX_IRQ_RFU31     31
+#define VR41XX_IRQ_RFU32     32
+#define VR41XX_IRQ_RFU33     33
+#define VR41XX_IRQ_RFU34     34
+#define VR41XX_IRQ_RFU35     35
+#define VR41XX_IRQ_RFU36     36
+#define VR41XX_IRQ_RFU37     37
+#define VR41XX_IRQ_RFU38     38
+#define VR41XX_IRQ_RFU39     39
+
+// Cascaded from VR41XX_IRQ_GIU
+#define VR41XX_IRQ_GPIO0     40
+#define VR41XX_IRQ_GPIO1     41
+#define VR41XX_IRQ_GPIO2     42
+#define VR41XX_IRQ_GPIO3     43
+#define VR41XX_IRQ_GPIO4     44
+#define VR41XX_IRQ_GPIO5     45
+#define VR41XX_IRQ_GPIO6     46
+#define VR41XX_IRQ_GPIO7     47
+#define VR41XX_IRQ_GPIO8     48
+#define VR41XX_IRQ_GPIO9     49
+#define VR41XX_IRQ_GPIO10    50
+#define VR41XX_IRQ_GPIO11    51
+#define VR41XX_IRQ_GPIO12    52
+#define VR41XX_IRQ_GPIO13    53
+#define VR41XX_IRQ_GPIO14    54
+#define VR41XX_IRQ_GPIO15    55
+#define VR41XX_IRQ_GPIO16    56
+#define VR41XX_IRQ_GPIO17    57
+#define VR41XX_IRQ_GPIO18    58
+#define VR41XX_IRQ_GPIO19    59
+#define VR41XX_IRQ_GPIO20    60
+#define VR41XX_IRQ_GPIO21    61
+#define VR41XX_IRQ_GPIO22    62
+#define VR41XX_IRQ_GPIO23    63
+#define VR41XX_IRQ_GPIO24    64
+#define VR41XX_IRQ_GPIO25    65
+#define VR41XX_IRQ_GPIO26    66
+#define VR41XX_IRQ_GPIO27    67
+#define VR41XX_IRQ_GPIO28    68
+#define VR41XX_IRQ_GPIO29    69
+#define VR41XX_IRQ_GPIO30    70
+#define VR41XX_IRQ_GPIO31    71
+
+// Alternative to above GPIO IRQ defines
+#define VR41XX_IRQ_GPIO(pin) ((VR41XX_IRQ_GPIO0) + (pin))
+
+#define VR41XX_IRQ_MAX       71
+
+#ifndef _LANGUAGE_ASSEMBLY
+#define __preg8		(volatile unsigned char*)
+#define __preg16	(volatile unsigned short*)
+#define __preg32	(volatile unsigned int*)
+#else
+#define __preg8
+#define __preg16
+#define __preg32
+#endif
+
+// Embedded CPU peripheral registers
+
+// Bus Control Unit (BCU)
+#define VR41XX_BCUCNTREG1	__preg16(KSEG1 + 0x0B000000)	/* BCU Control Register 1 (R/W) */
+#define VR41XX_BCUCNTREG2	__preg16(KSEG1 + 0x0B000002)	/* BCU Control Register 2 (R/W) */
+#define VR41XX_ROMSIZEREG	__preg16(KSEG1 + 0x0B000004)	/* ROM Size Register (R/W) */
+#define VR41XX_RAMSIZEREG	__preg16(KSEG1 + 0x0B000006)	/* DRAM Size Register (R/W) */
+#define VR41XX_BCUSPEEDREG	__preg16(KSEG1 + 0x0B00000A)	/* BCU Access Cycle Change Register (R/W) */
+#define VR41XX_BCUERRSTREG	__preg16(KSEG1 + 0x0B00000C)	/* BCU BUS ERROR Status Register (R/W) */
+#define VR41XX_BCURFCNTREG	__preg16(KSEG1 + 0x0B00000E)	/* BCU Refresh Control Register (R/W) */
+#define VR41XX_REVIDREG		__preg16(KSEG1 + 0x0B000010)	/* Revision ID Register (R) */
+#define VR41XX_BCURFCOUNTREG	__preg16(KSEG1 + 0x0B000012)	/* BCU Refresh Count Register (R/W) */
+#define VR41XX_CLKSPEEDREG	__preg16(KSEG1 + 0x0B000014)	/* Clock Speed Register (R) */
+#define VR41XX_BCUCNTREG3	__preg16(KSEG1 + 0x0B000016)	/* BCU Control Register 3 (R/W) */
+#define VR41XX_SDRAMMODEREG	__preg16(KSEG1 + 0x0B00001A)	/* SDRAM Mode Register */
+#define VR41XX_SROMMODEREG	__preg16(KSEG1 + 0x0B00001C)	/* SROM Mode Register */
+#define VR41XX_SDRAMCNTREG	__preg16(KSEG1 + 0x0B00001E)	/* SDRAM Control Register */
+#define VR41XX_BCUTOUTCNTREG	__preg16(KSEG1 + 0x0B000300)	/* BCU Timeout Control Register */
+#define VR41XX_BCUTOUTCOUNTREG	__preg16(KSEG1 + 0x0B000302)	/* BCU Timeout Count Register */
+
+// DMA Address Unit (DMAAU)
+#define VR41XX_AIUIBALREG	__preg16(KSEG1 + 0x0B000020)	/* AIU IN DMA Base Address Register Low (R/W) */
+#define VR41XX_AIUIBAHREG	__preg16(KSEG1 + 0x0B000022)	/* AIU IN DMA Base Address Register High (R/W) */
+#define VR41XX_AIUIALREG	__preg16(KSEG1 + 0x0B000024)	/* AIU IN DMA Address Register Low (R/W) */
+#define VR41XX_AIUIAHREG	__preg16(KSEG1 + 0x0B000026)	/* AIU IN DMA Address Register High (R/W) */
+#define VR41XX_AIUOBALREG	__preg16(KSEG1 + 0x0B000028)	/* AIU OUT DMA Base Address Register Low (R/W) */
+#define VR41XX_AIUOBAHREG	__preg16(KSEG1 + 0x0B00002A)	/* AIU OUT DMA Base Address Register High (R/W) */
+#define VR41XX_AIUOALREG	__preg16(KSEG1 + 0x0B00002C)	/* AIU OUT DMA Address Register Low (R/W) */
+#define VR41XX_AIUOAHREG	__preg16(KSEG1 + 0x0B00002E)	/* AIU OUT DMA Address Register High (R/W) */
+#define VR41XX_FIRBALREG	__preg16(KSEG1 + 0x0B000030)	/* FIR DMA Base Address Register Low (R/W) */
+#define VR41XX_FIRBAHREG	__preg16(KSEG1 + 0x0B000032)	/* FIR DMA Base Address Register High (R/W) */
+#define VR41XX_FIRALREG		__preg16(KSEG1 + 0x0B000034)	/* FIR DMA Address Register Low (R/W) */
+#define VR41XX_FIRAHREG		__preg16(KSEG1 + 0x0B000036)	/* FIR DMA Address Register High (R/W) */
+
+// DMA Control Unit (DCU)
+#define VR41XX_DMARSTREG	__preg16(KSEG1 + 0x0B000040)	/* DMA Reset Register (R/W) */
+#define VR41XX_DMAIDLEREG	__preg16(KSEG1 + 0x0B000042)	/* DMA Idle Register (R) */
+#define VR41XX_DMASENREG	__preg16(KSEG1 + 0x0B000044)	/* DMA Sequencer Enable Register (R/W) */
+#define VR41XX_DMAMSKREG	__preg16(KSEG1 + 0x0B000046)	/* DMA Mask Register (R/W) */
+#define VR41XX_DMAREQREG	__preg16(KSEG1 + 0x0B000048)	/* DMA Request Register (R) */
+#define VR41XX_TDREG		__preg16(KSEG1 + 0x0B00004A)	/* Transfer Direction Register (R/W) */
+
+// Clock Mask Unit (CMU)
+#define VR41XX_CMUCLKMSK	__preg16(KSEG1 + 0x0B000060)	/* CMU Clock Mask Register (R/W) */
+#define VR41XX_CMUCLKMSK_MSKPIUPCLK	0x0001
+#define VR41XX_CMUCLKMSK_MSKSIU		0x0102
+
+// Interrupt Control Unit (ICU)
+#define VR41XX_SYSINT1REG	__preg16(KSEG1 + 0x0B000080)	/* Level 1 System interrupt register 1 (R) */
+#define VR41XX_PIUINTREGro	__preg16(KSEG1 + 0x0B000082)	/* Level 2 PIU interrupt register (R) */
+#define VR41XX_AIUINTREG	__preg16(KSEG1 + 0x0B000084)	/* Level 2 AIU interrupt register (R) */
+#define VR41XX_KIUINTREG	__preg16(KSEG1 + 0x0B000086)	/* Level 2 KIU interrupt register (R) */
+#define VR41XX_GIUINTLREG	__preg16(KSEG1 + 0x0B000088)	/* Level 2 GIU interrupt register Low (R) */
+#define VR41XX_DSIUINTREG	__preg16(KSEG1 + 0x0B00008A)	/* Level 2 DSIU interrupt register (R) */
+#define VR41XX_MSYSINT1REG	__preg16(KSEG1 + 0x0B00008C)	/* Level 1 mask system interrupt register 1 (R/W) */
+#define VR41XX_MPIUINTREG	__preg16(KSEG1 + 0x0B00008E)	/* Level 2 mask PIU interrupt register (R/W) */
+#define VR41XX_MAIUINTREG	__preg16(KSEG1 + 0x0B000090)	/* Level 2 mask AIU interrupt register (R/W) */
+#define VR41XX_MKIUINTREG	__preg16(KSEG1 + 0x0B000092)	/* Level 2 mask KIU interrupt register (R/W) */
+#define VR41XX_MGIUINTLREG	__preg16(KSEG1 + 0x0B000094)	/* Level 2 mask GIU interrupt register Low (R/W) */
+#define VR41XX_MDSIUINTREG	__preg16(KSEG1 + 0x0B000096)	/* Level 2 mask DSIU interrupt register (R/W) */
+#define VR41XX_NMIREG		__preg16(KSEG1 + 0x0B000098)	/* NMI register (R/W) */
+#define VR41XX_SOFTINTREG	__preg16(KSEG1 + 0x0B00009A)	/* Software interrupt register (R/W) */
+#define VR41XX_SYSINT2REG	__preg16(KSEG1 + 0x0B000200)	/* Level 1 System interrupt register 2 (R) */
+#define VR41XX_GIUINTHREG	__preg16(KSEG1 + 0x0B000202)	/* Level 2 GIU interrupt register High (R) */
+#define VR41XX_FIRINTREG	__preg16(KSEG1 + 0x0B000204)	/* Level 2 FIR interrupt register (R) */
+#define VR41XX_MSYSINT2REG	__preg16(KSEG1 + 0x0B000206)	/* Level 1 mask system interrupt register 2 (R/W) */
+#define VR41XX_MGIUINTHREG	__preg16(KSEG1 + 0x0B000208)	/* Level 2 mask GIU interrupt register High (R/W) */
+#define VR41XX_MFIRINTREG	__preg16(KSEG1 + 0x0B00020A)	/* Level 2 mask FIR interrupt register (R/W) */
+
+// Power Management Unit (PMU)
+#define VR41XX_PMUINTREG	__preg16(KSEG1 + 0x0B0000A0)	/* PMU Status Register (R/W) */
+#define VR41XX_PMUINT_POWERSW  0x1	/* Power switch */
+#define VR41XX_PMUINT_BATT     0x2	/* Low batt during normal operation */
+#define VR41XX_PMUINT_DEADMAN  0x4	/* Deadman's switch */
+#define VR41XX_PMUINT_RESET    0x8	/* Reset switch */
+#define VR41XX_PMUINT_RTCRESET 0x10	/* RTC Reset */
+#define VR41XX_PMUINT_TIMEOUT  0x20	/* HAL Timer Reset */
+#define VR41XX_PMUINT_BATTLOW  0x100	/* Battery low */
+#define VR41XX_PMUINT_RTC      0x200	/* RTC Alarm */
+#define VR41XX_PMUINT_DCD      0x400	/* DCD# */
+#define VR41XX_PMUINT_GPIO0    0x1000	/* GPIO0 */
+#define VR41XX_PMUINT_GPIO1    0x2000	/* GPIO1 */
+#define VR41XX_PMUINT_GPIO2    0x4000	/* GPIO2 */
+#define VR41XX_PMUINT_GPIO3    0x8000	/* GPIO3 */
+
+#define VR41XX_PMUCNTREG	__preg16(KSEG1 + 0x0B0000A2)	/* PMU Control Register (R/W) */
+#define VR41XX_PMUWAITREG	__preg16(KSEG1 + 0x0B0000A8)	/* PMU Wait Counter Register (R/W) */
+#define VR41XX_PMUINT2REG	__preg16(KSEG1 + 0x0B0000A4)	/* PMU Interrupt/Status 2 Register (R/W) */
+#define VR41XX_PMUCNT2REG	__preg16(KSEG1 + 0x0B0000A6)	/* PMU Control 2 Resister (R/W) */
+
+// Real Time Clock Unit (RTC)
+#define VR41XX_ETIMELREG	__preg16(KSEG1 + 0x0B0000C0)	/* Elapsed Time L Register (R/W) */
+#define VR41XX_ETIMEMREG	__preg16(KSEG1 + 0x0B0000C2)	/* Elapsed Time M Register (R/W) */
+#define VR41XX_ETIMEHREG	__preg16(KSEG1 + 0x0B0000C4)	/* Elapsed Time H Register (R/W) */
+#define VR41XX_ECMPLREG		__preg16(KSEG1 + 0x0B0000C8)	/* Elapsed Compare L Register (R/W) */
+#define VR41XX_ECMPMREG		__preg16(KSEG1 + 0x0B0000CA)	/* Elapsed Compare M Register (R/W) */
+#define VR41XX_ECMPHREG		__preg16(KSEG1 + 0x0B0000CC)	/* Elapsed Compare H Register (R/W) */
+#define VR41XX_RTCL1LREG	__preg16(KSEG1 + 0x0B0000D0)	/* RTC Long 1 L Register (R/W) */
+#define VR41XX_RTCL1HREG	__preg16(KSEG1 + 0x0B0000D2)	/* RTC Long 1 H Register (R/W) */
+#define VR41XX_RTCL1CNTLREG	__preg16(KSEG1 + 0x0B0000D4)	/* RTC Long 1 Count L Register (R) */
+#define VR41XX_RTCL1CNTHREG	__preg16(KSEG1 + 0x0B0000D6)	/* RTC Long 1 Count H Register (R) */
+#define VR41XX_RTCL2LREG	__preg16(KSEG1 + 0x0B0000D8)	/* RTC Long 2 L Register (R/W) */
+#define VR41XX_RTCL2HREG	__preg16(KSEG1 + 0x0B0000DA)	/* RTC Long 2 H Register (R/W) */
+#define VR41XX_RTCL2CNTLREG	__preg16(KSEG1 + 0x0B0000DC)	/* RTC Long 2 Count L Register (R) */
+#define VR41XX_RTCL2CNTHREG	__preg16(KSEG1 + 0x0B0000DE)	/* RTC Long 2 Count H Register (R) */
+#define VR41XX_RTCINTREG	__preg16(KSEG1 + 0x0B0001DE)	/* RTC Interrupt Register (R/W) */
+#define VR41XX_TCLKLREG		__preg16(KSEG1 + 0x0B0001C0)	/* TCLK L Register (R/W) */
+#define VR41XX_TCLKHREG		__preg16(KSEG1 + 0x0B0001C2)	/* TCLK H Register (R/W) */
+#define VR41XX_TCLKCNTLREG	__preg16(KSEG1 + 0x0B0001C4)	/* TCLK Count L Register (R) */
+#define VR41XX_TCLKCNTHREG	__preg16(KSEG1 + 0x0B0001C6)	/* TCLK Count H Register (R) */
+
+// Deadman's Switch Unit (DSU)
+#define VR41XX_DSUCNTREG	__preg16(KSEG1 + 0x0B0000E0)	/* DSU Control Register (R/W) */
+#define VR41XX_DSUSETREG	__preg16(KSEG1 + 0x0B0000E2)	/* DSU Dead Time Set Register (R/W) */
+#define VR41XX_DSUCLRREG	__preg16(KSEG1 + 0x0B0000E4)	/* DSU Clear Register (W) */
+#define VR41XX_DSUTIMREG	__preg16(KSEG1 + 0x0B0000E6)	/* DSU Elapsed Time Register (R/W) */
+
+// General Purpose I/O Unit (GIU)
+#define VR41XX_GIUIOSELL	__preg16(KSEG1 + 0x0B000100)	/* GPIO Input/Output Select Register L (R/W) */
+#define VR41XX_GIUIOSELH	__preg16(KSEG1 + 0x0B000102)	/* GPIO Input/Output Select Register H (R/W) */
+#define VR41XX_GIUPIODL		__preg16(KSEG1 + 0x0B000104)	/* GPIO Port Input/Output Data Register L (R/W) */
+#define VR41XX_GIUPIODL_GPIO15  0x8000
+#define VR41XX_GIUPIODL_GPIO14  0x4000
+#define VR41XX_GIUPIODL_GPIO13  0x2000
+#define VR41XX_GIUPIODL_GPIO12  0x1000
+#define VR41XX_GIUPIODL_GPIO11  0x0800
+#define VR41XX_GIUPIODL_GPIO10  0x0400
+#define VR41XX_GIUPIODL_GPIO9  0x0200
+#define VR41XX_GIUPIODL_GPIO8  0x0100
+#define VR41XX_GIUPIODL_GPIO7  0x0080
+#define VR41XX_GIUPIODL_GPIO6  0x0040
+#define VR41XX_GIUPIODL_GPIO5  0x0020
+#define VR41XX_GIUPIODL_GPIO4  0x0010
+#define VR41XX_GIUPIODL_GPIO3  0x0008
+#define VR41XX_GIUPIODL_GPIO2  0x0004
+#define VR41XX_GIUPIODL_GPIO1  0x0002
+#define VR41XX_GIUPIODL_GPIO0  0x0001
+#define VR41XX_GIUPIODH		__preg16(KSEG1 + 0x0B000106)	/* GPIO Port Input/Output Data Register H (R/W) */
+#define VR41XX_GIUPIODH_GPIO31  0x8000
+#define VR41XX_GIUPIODH_GPIO30  0x4000
+#define VR41XX_GIUPIODH_GPIO29  0x2000
+#define VR41XX_GIUPIODH_GPIO28  0x1000
+#define VR41XX_GIUPIODH_GPIO27  0x0800
+#define VR41XX_GIUPIODH_GPIO26  0x0400
+#define VR41XX_GIUPIODH_GPIO25  0x0200
+#define VR41XX_GIUPIODH_GPIO24  0x0100
+#define VR41XX_GIUPIODH_GPIO23  0x0080
+#define VR41XX_GIUPIODH_GPIO22  0x0040
+#define VR41XX_GIUPIODH_GPIO21  0x0020
+#define VR41XX_GIUPIODH_GPIO20  0x0010
+#define VR41XX_GIUPIODH_GPIO19  0x0008
+#define VR41XX_GIUPIODH_GPIO18  0x0004
+#define VR41XX_GIUPIODH_GPIO17  0x0002
+#define VR41XX_GIUPIODH_GPIO16  0x0001
+#define VR41XX_GIUINTSTATL	__preg16(KSEG1 + 0x0B000108)	/* GPIO Interrupt Status Register L (R/W) */
+#define VR41XX_GIUINTSTATH	__preg16(KSEG1 + 0x0B00010A)	/* GPIO Interrupt Status Register H (R/W) */
+#define VR41XX_GIUINTENL	__preg16(KSEG1 + 0x0B00010C)	/* GPIO Interrupt Enable Register L (R/W) */
+#define VR41XX_GIUINTENH	__preg16(KSEG1 + 0x0B00010E)	/* GPIO Interrupt Enable Register H (R/W) */
+#define VR41XX_GIUINTTYPL	__preg16(KSEG1 + 0x0B000110)	/* GPIO Interrupt Type (Edge or Level) Select Register (R/W) */
+#define VR41XX_GIUINTTYPH	__preg16(KSEG1 + 0x0B000112)	/* GPIO Interrupt Type (Edge or Level) Select Register (R/W) */
+#define VR41XX_GIUINTALSELL	__preg16(KSEG1 + 0x0B000114)	/* GPIO Interrupt Active Level Select Register L (R/W) */
+#define VR41XX_GIUINTALSELH	__preg16(KSEG1 + 0x0B000116)	/* GPIO Interrupt Active Level Select Register H (R/W) */
+#define VR41XX_GIUINTHTSELL	__preg16(KSEG1 + 0x0B000118)	/* GPIO Interrupt Hold/Through Select Register L (R/W) */
+#define VR41XX_GIUINTHTSELH	__preg16(KSEG1 + 0x0B00011A)	/* GPIO Interrupt Hold/Through Select Register H (R/W) */
+
+#define VR41XX_GIUPODATL	__preg16(KSEG1 + 0x0B00011C)	/* GPIO Port Output Data Register L (R/W) */
+#define VR41XX_GIUPODATL_GPIO47  0x8000
+#define VR41XX_GIUPODATL_GPIO46  0x4000
+#define VR41XX_GIUPODATL_GPIO45  0x2000
+#define VR41XX_GIUPODATL_GPIO44  0x1000
+#define VR41XX_GIUPODATL_GPIO43  0x0800
+#define VR41XX_GIUPODATL_GPIO42  0x0400
+#define VR41XX_GIUPODATL_GPIO41  0x0200
+#define VR41XX_GIUPODATL_GPIO40  0x0100
+#define VR41XX_GIUPODATL_GPIO39  0x0080
+#define VR41XX_GIUPODATL_GPIO38  0x0040
+#define VR41XX_GIUPODATL_GPIO37  0x0020
+#define VR41XX_GIUPODATL_GPIO36  0x0010
+#define VR41XX_GIUPODATL_GPIO35  0x0008
+#define VR41XX_GIUPODATL_GPIO34  0x0004
+#define VR41XX_GIUPODATL_GPIO33  0x0002
+#define VR41XX_GIUPODATL_GPIO32  0x0001
+#define VR41XX_GIUPODATL_PODAT15  0x8000
+#define VR41XX_GIUPODATL_PODAT14  0x4000
+#define VR41XX_GIUPODATL_PODAT13  0x2000
+#define VR41XX_GIUPODATL_PODAT12  0x1000
+#define VR41XX_GIUPODATL_PODAT11  0x0800
+#define VR41XX_GIUPODATL_PODAT10  0x0400
+#define VR41XX_GIUPODATL_PODAT9  0x0200
+#define VR41XX_GIUPODATL_PODAT8  0x0100
+#define VR41XX_GIUPODATL_PODAT7  0x0080
+#define VR41XX_GIUPODATL_PODAT6  0x0040
+#define VR41XX_GIUPODATL_PODAT5  0x0020
+#define VR41XX_GIUPODATL_PODAT4  0x0010
+#define VR41XX_GIUPODATL_PODAT3  0x0008
+#define VR41XX_GIUPODATL_PODAT2  0x0004
+#define VR41XX_GIUPODATL_PODAT1  0x0002
+#define VR41XX_GIUPODATL_PODAT0  0x0001
+#define VR41XX_GIUPODATH	__preg16(KSEG1 + 0x0B00011E)	/* GPIO Port Output Data Register H (R/W) */
+#define VR41XX_GIUPODATH_GPIO51  0x0008
+#define VR41XX_GIUPODATH_GPIO50  0x0004
+#define VR41XX_GIUPODATH_GPIO49  0x0002
+#define VR41XX_GIUPODATH_GPIO48  0x0001
+#define VR41XX_GIUPODATH_PODAT3  0x0008
+#define VR41XX_GIUPODATH_PODAT2  0x0004
+#define VR41XX_GIUPODATH_PODAT1  0x0002
+#define VR41XX_GIUPODATH_PODAT0  0x0001
+#define VR41XX_GIUUSEUPDN	__preg16(KSEG1 + 0x0B0002E0)	/* GPIO Pullup/Down User Register (R/W) */
+#define VR41XX_GIUTERMUPDN	__preg16(KSEG1 + 0x0B0002E2)	/* GPIO Terminal Pullup/Down Register (R/W) */
+#define VR41XX_SECIRQMASKL	VR41XX_GIUINTENL
+#define VR41XX_SECIRQMASKH	VR41XX_GIUINTENH
+
+// Touch Panel Interface Unit (PIU)
+#define VR41XX_PIUCNTREG	__preg16(KSEG1 + 0x0B000122)	/* PIU Control register (R/W) */
+#define VR41XX_PIUCNTREG_PIUSEQEN	0x0004
+#define VR41XX_PIUCNTREG_PIUPWR		0x0002
+#define VR41XX_PIUCNTREG_PADRST		0x0001
+
+#define VR41XX_PIUINTREG	__preg16(KSEG1 + 0x0B000124)	/* PIU Interrupt cause register (R/W) */
+#define VR41XX_PIUINTREG_OVP		0x8000
+#define VR41XX_PIUINTREG_PADCMD		0x0040
+#define VR41XX_PIUINTREG_PADADP		0x0020
+#define VR41XX_PIUINTREG_PADPAGE1	0x0010
+#define VR41XX_PIUINTREG_PADPAGE0	0x0008
+#define VR41XX_PIUINTREG_PADDLOST	0x0004
+#define VR41XX_PIUINTREG_PENCHG		0x0001
+
+#define VR41XX_PIUSIVLREG	__preg16(KSEG1 + 0x0B000126)	/* PIU Data sampling interval register (R/W) */
+#define VR41XX_PIUSTBLREG	__preg16(KSEG1 + 0x0B000128)	/* PIU A/D converter start delay register (R/W) */
+#define VR41XX_PIUCMDREG	__preg16(KSEG1 + 0x0B00012A)	/* PIU A/D command register (R/W) */
+#define VR41XX_PIUASCNREG	__preg16(KSEG1 + 0x0B000130)	/* PIU A/D port scan register (R/W) */
+#define VR41XX_PIUAMSKREG	__preg16(KSEG1 + 0x0B000132)	/* PIU A/D scan mask register (R/W) */
+#define VR41XX_PIUCIVLREG	__preg16(KSEG1 + 0x0B00013E)	/* PIU Check interval register (R) */
+#define VR41XX_PIUPB00REG	__preg16(KSEG1 + 0x0B0002A0)	/* PIU Page 0 Buffer 0 register (R/W) */
+#define VR41XX_PIUPB01REG	__preg16(KSEG1 + 0x0B0002A2)	/* PIU Page 0 Buffer 1 register (R/W) */
+#define VR41XX_PIUPB02REG	__preg16(KSEG1 + 0x0B0002A4)	/* PIU Page 0 Buffer 2 register (R/W) */
+#define VR41XX_PIUPB03REG	__preg16(KSEG1 + 0x0B0002A6)	/* PIU Page 0 Buffer 3 register (R/W) */
+#define VR41XX_PIUPB10REG	__preg16(KSEG1 + 0x0B0002A8)	/* PIU Page 1 Buffer 0 register (R/W) */
+#define VR41XX_PIUPB11REG	__preg16(KSEG1 + 0x0B0002AA)	/* PIU Page 1 Buffer 1 register (R/W) */
+#define VR41XX_PIUPB12REG	__preg16(KSEG1 + 0x0B0002AC)	/* PIU Page 1 Buffer 2 register (R/W) */
+#define VR41XX_PIUPB13REG	__preg16(KSEG1 + 0x0B0002AE)	/* PIU Page 1 Buffer 3 register (R/W) */
+#define VR41XX_PIUAB0REG	__preg16(KSEG1 + 0x0B0002B0)	/* PIU A/D scan Buffer 0 register (R/W) */
+#define VR41XX_PIUAB1REG	__preg16(KSEG1 + 0x0B0002B2)	/* PIU A/D scan Buffer 1 register (R/W) */
+#define VR41XX_PIUAB2REG	__preg16(KSEG1 + 0x0B0002B4)	/* PIU A/D scan Buffer 2 register (R/W) */
+#define VR41XX_PIUAB3REG	__preg16(KSEG1 + 0x0B0002B6)	/* PIU A/D scan Buffer 3 register (R/W) */
+#define VR41XX_PIUPB04REG	__preg16(KSEG1 + 0x0B0002BC)	/* PIU Page 0 Buffer 4 register (R/W) */
+#define VR41XX_PIUPB14REG	__preg16(KSEG1 + 0x0B0002BE)	/* PIU Page 1 Buffer 4 register (R/W) */
+
+// Audio Interface Unit (AIU)
+#define VR41XX_SODATREG		__preg16(KSEG1 + 0x0B000166)	/* Speaker Output Data Register (R/W) */
+#define VR41XX_SCNTREG		__preg16(KSEG1 + 0x0B000168)	/* Speaker Output Control Register (R/W) */
+#define VR41XX_MIDATREG		__preg16(KSEG1 + 0x0B000170)	/* Mike Input Data Register (R/W) */
+#define VR41XX_MCNTREG		__preg16(KSEG1 + 0x0B000172)	/* Mike Input Control Register (R/W) */
+#define VR41XX_DVALIDREG	__preg16(KSEG1 + 0x0B000178)	/* Data Valid Register (R/W) */
+#define VR41XX_SEQREG		__preg16(KSEG1 + 0x0B00017A)	/* Sequential Register (R/W) */
+#define VR41XX_INTREG		__preg16(KSEG1 + 0x0B00017C)	/* Interrupt Register (R/W) */
+#define VR41XX_MDMADATREG	__preg16(KSEG1 + 0x0B000160)	/* Mike DMA Data Register (R/W) */
+#define VR41XX_SDMADATREG	__preg16(KSEG1 + 0x0B000162)	/* Speaker DMA Data Register (R/W) */
+#define VR41XX_SCNVRREG		__preg16(KSEG1 + 0x0B00016A)	/* Speaker Conversion Rate Register (R/W) */
+#define VR41XX_MCNVRREG		__preg16(KSEG1 + 0x0B000174)	/* Mike Conversion Rate Register (R/W) */
+
+// Keyboard Interface Unit (KIU)
+#define VR41XX_KIUDAT0		__preg16(KSEG1 + 0x0B000180)	/* KIU Data0 Register (R/W) */
+#define VR41XX_KIUDAT1		__preg16(KSEG1 + 0x0B000182)	/* KIU Data1 Register (R/W) */
+#define VR41XX_KIUDAT2		__preg16(KSEG1 + 0x0B000184)	/* KIU Data2 Register (R/W) */
+#define VR41XX_KIUDAT3		__preg16(KSEG1 + 0x0B000186)	/* KIU Data3 Register (R/W) */
+#define VR41XX_KIUDAT4		__preg16(KSEG1 + 0x0B000188)	/* KIU Data4 Register (R/W) */
+#define VR41XX_KIUDAT5		__preg16(KSEG1 + 0x0B00018A)	/* KIU Data5 Register (R/W) */
+#define VR41XX_KIUSCANREP	__preg16(KSEG1 + 0x0B000190)	/* KIU Scan/Repeat Register (R/W) */
+#define VR41XX_KIUSCANREP_KEYEN      0x8000
+#define VR41XX_KIUSCANREP_SCANSTP    0x0008
+#define VR41XX_KIUSCANREP_SCANSTART  0x0004
+#define VR41XX_KIUSCANREP_ATSTP      0x0002
+#define VR41XX_KIUSCANREP_ATSCAN     0x0001
+#define VR41XX_KIUSCANS		__preg16(KSEG1 + 0x0B000192)	/* KIU Scan Status Register (R) */
+#define VR41XX_KIUWKS		__preg16(KSEG1 + 0x0B000194)	/* KIU Wait Keyscan Stable Register (R/W) */
+#define VR41XX_KIUWKI		__preg16(KSEG1 + 0x0B000196)	/* KIU Wait Keyscan Interval Register (R/W) */
+#define VR41XX_KIUINT		__preg16(KSEG1 + 0x0B000198)	/* KIU Interrupt Register (R/W) */
+#define VR41XX_KIUINT_KDATLOST       0x0004
+#define VR41XX_KIUINT_KDATRDY        0x0002
+#define VR41XX_KIUINT_SCANINT        0x0001
+#define VR41XX_KIURST		__preg16(KSEG1 + 0x0B00019A)	/* KIU Reset Register (W) */
+#define VR41XX_KIUGPEN		__preg16(KSEG1 + 0x0B00019C)	/* KIU General Purpose Output Enable (R/W) */
+#define VR41XX_SCANLINE		__preg16(KSEG1 + 0x0B00019E)	/* KIU Scan Line Register (R/W) */
+
+// Debug Serial Interface Unit (DSIU)
+#define VR41XX_PORTREG		__preg16(KSEG1 + 0x0B0001A0)	/* Port Change Register (R/W) */
+#define VR41XX_MODEMREG		__preg16(KSEG1 + 0x0B0001A2)	/* Modem Control Register (R) */
+#define VR41XX_ASIM00REG	__preg16(KSEG1 + 0x0B0001A4)	/* Asynchronous Mode 0 Register (R/W) */
+#define VR41XX_ASIM01REG	__preg16(KSEG1 + 0x0B0001A6)	/* Asynchronous Mode 1 Register (R/W) */
+#define VR41XX_RXB0RREG		__preg16(KSEG1 + 0x0B0001A8)	/* Receive Buffer Register (Extended) (R) */
+#define VR41XX_RXB0LREG		__preg16(KSEG1 + 0x0B0001AA)	/* Receive Buffer Register (R) */
+#define VR41XX_TXS0RREG		__preg16(KSEG1 + 0x0B0001AC)	/* Transmit Data Register (Extended) (R/W) */
+#define VR41XX_TXS0LREG		__preg16(KSEG1 + 0x0B0001AE)	/* Transmit Data Register (R/W) */
+#define VR41XX_ASIS0REG		__preg16(KSEG1 + 0x0B0001B0)	/* Status Register (R) */
+#define VR41XX_INTR0REG		__preg16(KSEG1 + 0x0B0001B2)	/* Debug SIU Interrupt Register (R/W) */
+#define VR41XX_BPRM0REG		__preg16(KSEG1 + 0x0B0001B6)	/* Baud rate Generator Prescaler Mode Register (R/W) */
+#define VR41XX_DSIURESETREG	__preg16(KSEG1 + 0x0B0001B8)	/* Debug SIU Reset Register (R/W) */
+
+// LED Control Unit (LED)
+#define VR41XX_LEDHTSREG	__preg16(KSEG1 + 0x0B000240)	/* LED H Time Set register (R/W) */
+#define VR41XX_LEDLTSREG	__preg16(KSEG1 + 0x0B000242)	/* LED L Time Set register (R/W) */
+#define VR41XX_LEDCNTREG	__preg16(KSEG1 + 0x0B000248)	/* LED Control register (R/W) */
+#define VR41XX_LEDASTCREG	__preg16(KSEG1 + 0x0B00024A)	/* LED Auto Stop Time Count register (R/W) */
+#define VR41XX_LEDINTREG	__preg16(KSEG1 + 0x0B00024C)	/* LED Interrupt register (R/W) */
+
+// Serial Interface Unit (SIU / SIU1 and SIU2)
+#define VR41XX_SIURB		__preg8(KSEG1 + 0x0C000000)	/* Receiver Buffer Register (Read) DLAB = 0 (R) */
+#define VR41XX_SIUTH		__preg8(KSEG1 + 0x0C000000)	/* Transmitter Holding Register (Write) DLAB = 0 (W) */
+#define VR41XX_SIUDLL		__preg8(KSEG1 + 0x0C000000)	/* Divisor Latch (Least Significant Byte) DLAB = 1 (R/W) */
+#define VR41XX_SIUIE		__preg8(KSEG1 + 0x0C000001)	/* Interrupt Enable DLAB = 0 (R/W) */
+#define VR41XX_SIUDLM		__preg8(KSEG1 + 0x0C000001)	/* Divisor Latch (Most Significant Byte) DLAB = 1 (R/W) */
+#define VR41XX_SIUIID		__preg8(KSEG1 + 0x0C000002)	/* Interrupt Identification Register (Read) (R) */
+#define VR41XX_SIUFC		__preg8(KSEG1 + 0x0C000002)	/* FIFO Control Register (Write) (W) */
+#define VR41XX_SIULC		__preg8(KSEG1 + 0x0C000003)	/* Line Control Register (R/W) */
+#define VR41XX_SIUMC		__preg8(KSEG1 + 0x0C000004)	/* MODEM Control Register (R/W) */
+#define VR41XX_SIULS		__preg8(KSEG1 + 0x0C000005)	/* Line Status Register (R/W) */
+#define VR41XX_SIUMS		__preg8(KSEG1 + 0x0C000006)	/* MODEM Status Register (R/W) */
+#define VR41XX_SIUSC		__preg8(KSEG1 + 0x0C000007)	/* Scratch Register (R/W) */
+#define VR41XX_SIUIRSEL		__preg8(KSEG1 + 0x0C000008)	/* SIU/FIR IrDA Selector (R/W) */
+#define VR41XX_SIURESET		__preg8(KSEG1 + 0x0C000009)	/* SIU Reset Register (R/W) */
+#define VR41XX_SIUCSEL		__preg8(KSEG1 + 0x0C00000A)	/* SIU Echo-Back Control Register (R/W) */
+
+// Modem Interface Unit (HSP)
+// Not sure if some of these are right type, some may be 16 bit regs:
+#define VR41XX_HSPINIT		__preg8(KSEG1 + 0x0C000020)	/* HSP Initialize Register (R/W) */
+#define VR41XX_HSPDATAL		__preg8(KSEG1 + 0x0C000022)	/* HSP Data Register L (R/W) */
+#define VR41XX_HSPDATAH		__preg8(KSEG1 + 0x0C000023)	/* HSP Data Register H (R/W) */
+#define VR41XX_HSPINDEX		__preg8(KSEG1 + 0x0C000024)	/* HSP Index Register (W) */
+#define VR41XX_HSPID		__preg8(KSEG1 + 0x0C000028)	/* HSP ID Register (R) */
+#define VR41XX_HSPPCS		__preg8(KSEG1 + 0x0C000029)	/* HSP I/O Address Program Confirmation Register (R) */
+#define VR41XX_HSPPCTEL		__preg8(KSEG1 + 0x0C000029)	/* HSP Signature Checking Port (W) */
+
+// Fast IrDA Interface Unit (FIR)
+#define VR41XX_FRSTR		__preg16(KSEG1 + 0x0C000040)	/* FIR Reset register (R/W) */
+#define VR41XX_DPINTR		__preg16(KSEG1 + 0x0C000042)	/* DMA Page Interrupt register (R/W) */
+#define VR41XX_DPCNTR		__preg16(KSEG1 + 0x0C000044)	/* DMA Control register (R/W) */
+#define VR41XX_TDR		__preg16(KSEG1 + 0x0C000050)	/* Transmit Data register (W) */
+#define VR41XX_RDR		__preg16(KSEG1 + 0x0C000052)	/* Receive Data register (R) */
+#define VR41XX_IMR		__preg16(KSEG1 + 0x0C000054)	/* Interrupt Mask register (R/W) */
+#define VR41XX_FSR		__preg16(KSEG1 + 0x0C000056)	/* FIFO Setup register (R/W) */
+#define VR41XX_IRSR1		__preg16(KSEG1 + 0x0C000058)	/* Infrared Setup register 1 (R/W) */
+#define VR41XX_CRCSR		__preg16(KSEG1 + 0x0C00005C)	/* CRC Setup register (R/W) */
+#define VR41XX_FIRCR		__preg16(KSEG1 + 0x0C00005E)	/* FIR Control register (R/W) */
+#define VR41XX_MIRCR		__preg16(KSEG1 + 0x0C000060)	/* MIR Control register (R/W) */
+#define VR41XX_DMACR		__preg16(KSEG1 + 0x0C000062)	/* DMA Control register (R/W) */
+#define VR41XX_DMAER		__preg16(KSEG1 + 0x0C000064)	/* DMA Enable register (R/W) */
+#define VR41XX_TXIR		__preg16(KSEG1 + 0x0C000066)	/* Transmit Indication register (R) */
+#define VR41XX_RXIR		__preg16(KSEG1 + 0x0C000068)	/* Receive Indication register (R) */
+#define VR41XX_IFR		__preg16(KSEG1 + 0x0C00006A)	/* Interrupt Flag register (R) */
+#define VR41XX_RXSTS		__preg16(KSEG1 + 0x0C00006C)	/* Receive Status (R) */
+#define VR41XX_TXFL		__preg16(KSEG1 + 0x0C00006E)	/* Transmit Frame Length (R/W) */
+#define VR41XX_MRXF		__preg16(KSEG1 + 0x0C000070)	/* Maximum Receive Frame Length (R/W) */
+#define VR41XX_RXFL		__preg16(KSEG1 + 0x0C000074)	/* Receive Frame Length (R) */
+
+// physical address spaces
+#define VR41XX_LCD             0x0a000000
+#define VR41XX_INTERNAL_IO_2   0x0b000000
+#define VR41XX_INTERNAL_IO_1   0x0c000000
+#define VR41XX_ISA_MEM         0x10000000
+#define VR41XX_ISA_IO          0x14000000
+#define VR41XX_ROM             0x18000000
+
+// This is the base address for IO port decoding to which the 16 bit IO port address
+// is added.  Defining it to 0 will usually cause a kernel oops any time port IO is
+// attempted, which can be handy for turning up parts of the kernel that make
+// incorrect architecture assumptions (by assuming that everything acts like a PC),
+// but we need it correctly defined to use the PCMCIA/CF controller:
+#define VR41XX_PORT_BASE	(KSEG1 + VR41XX_ISA_IO)
+#define VR41XX_ISAMEM_BASE	(KSEG1 + VR41XX_ISA_MEM)
+
+#endif /* __ASM_MIPS_VR4121_H */
diff -ruN linux-mips/include/asm-mips/vr4122.h linux-vr/include/asm-mips/vr4122.h
--- linux-mips/include/asm-mips/vr4122.h	Wed Dec 31 16:00:00 1969
+++ linux-vr/include/asm-mips/vr4122.h	Wed Nov 15 12:09:27 2000
@@ -0,0 +1,472 @@
+/* $Id: vr4122.h,v 1.1 2000/11/15 20:09:27 mikemac Exp $
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1999 by Michael Klar
+ * Copyright (C) 2000 by Michael R. McDonald
+ */
+#ifndef __ASM_MIPS_VR4122_H 
+#define __ASM_MIPS_VR4122_H 
+
+#include <asm/addrspace.h>
+
+/* CPU interrupts */
+#define VR41XX_IRQ_SW1       0  /* IP0 - Software interrupt */
+#define VR41XX_IRQ_SW2       1  /* IP1 - Software interrupt */
+#define VR41XX_IRQ_INT0      2  /* IP2 - All but battery, high speed modem, and real time clock */
+#define VR41XX_IRQ_INT1      3  /* IP3 - RTC Long1 (system timer) */
+#define VR41XX_IRQ_INT2      4  /* IP4 - RTC Long2 */
+#define VR41XX_IRQ_INT3      5  /* IP5 - High Speed Modem */
+#define VR41XX_IRQ_INT4      6  /* IP6 - Unused */
+#define VR41XX_IRQ_TIMER     7  /* IP7 - Timer interrupt from CPO_COMPARE (Note: RTC Long1 is the system timer.) */
+
+/* Cascaded from VR41XX_IRQ_INT0 (ICU mapped interrupts) */
+#define VR41XX_IRQ_BATTERY   8
+#define VR41XX_IRQ_POWER     9
+#define VR41XX_IRQ_RTCL1     10  /* Use VR41XX_IRQ_INT1 instead. */
+#define VR41XX_IRQ_ETIMER    11
+#define VR41XX_IRQ_RFU12     12
+#define VR41XX_IRQ_RFU13     13
+#define VR41XX_IRQ_RFU14     14
+#define VR41XX_IRQ_RFU15     15
+#define VR41XX_IRQ_GIU       16  /* This is a cascade to IRQs 40-71. Do not use. */
+#define VR41XX_IRQ_SIU       17
+#define VR41XX_IRQ_WRBERR    18
+#define VR41XX_IRQ_SOFT      19
+#define VR41XX_IRQ_RFU20     20
+#define VR41XX_IRQ_DOZEPIU   21
+#define VR41XX_IRQ_RFU22     22
+#define VR41XX_IRQ_RFU23     23
+#define VR41XX_IRQ_RTCL2     24  /* Use VR41XX_IRQ_INT2 instead. */
+#define VR41XX_IRQ_LED       25
+#define VR41XX_IRQ_HSP       26  /* Use VR41XX_IRQ_INT3 instead. */
+#define VR41XX_IRQ_TCLK      27
+#define VR41XX_IRQ_FIR       28
+#define VR41XX_IRQ_DSIU      29
+#define VR41XX_IRQ_PCIU      30
+#define VR41XX_IRQ_RFU31     31
+#define VR41XX_IRQ_RFU32     32
+#define VR41XX_IRQ_RFU33     33
+#define VR41XX_IRQ_RFU34     34
+#define VR41XX_IRQ_RFU35     35
+#define VR41XX_IRQ_RFU36     36
+#define VR41XX_IRQ_RFU37     37
+#define VR41XX_IRQ_RFU38     38
+#define VR41XX_IRQ_RFU39     39
+
+/* Cascaded from VR41XX_IRQ_GIU */
+#define VR41XX_IRQ_GPIO0     40
+#define VR41XX_IRQ_GPIO1     41
+#define VR41XX_IRQ_GPIO2     42
+#define VR41XX_IRQ_GPIO3     43
+#define VR41XX_IRQ_GPIO4     44
+#define VR41XX_IRQ_GPIO5     45
+#define VR41XX_IRQ_GPIO6     46
+#define VR41XX_IRQ_GPIO7     47
+#define VR41XX_IRQ_GPIO8     48
+#define VR41XX_IRQ_GPIO9     49
+#define VR41XX_IRQ_GPIO10    50
+#define VR41XX_IRQ_GPIO11    51
+#define VR41XX_IRQ_GPIO12    52
+#define VR41XX_IRQ_GPIO13    53
+#define VR41XX_IRQ_GPIO14    54
+#define VR41XX_IRQ_GPIO15    55
+#define VR41XX_IRQ_GPIO16    56
+#define VR41XX_IRQ_GPIO17    57
+#define VR41XX_IRQ_GPIO18    58
+#define VR41XX_IRQ_GPIO19    59
+#define VR41XX_IRQ_GPIO20    60
+#define VR41XX_IRQ_GPIO21    61
+#define VR41XX_IRQ_GPIO22    62
+#define VR41XX_IRQ_GPIO23    63
+#define VR41XX_IRQ_GPIO24    64
+#define VR41XX_IRQ_GPIO25    65
+#define VR41XX_IRQ_GPIO26    66
+#define VR41XX_IRQ_GPIO27    67
+#define VR41XX_IRQ_GPIO28    68
+#define VR41XX_IRQ_GPIO29    69
+#define VR41XX_IRQ_GPIO30    70
+#define VR41XX_IRQ_GPIO31    71
+
+#ifdef CONFIG_NEC_HARRIER
+#define VR41XX_IRQ_4173		VR41XX_IRQ_GPIO1
+#define VR41XX_IRQ_MQ200	VR41XX_IRQ_GPIO4
+#define VR41XX_IRQ_PCI		VR41XX_IRQ_GPIO5
+#define VR41XX_IRQ_SIO		VR41XX_IRQ_GPIO8
+#endif
+
+/* Alternative to above GPIO IRQ defines */
+#define VR41XX_IRQ_GPIO(pin) ((VR41XX_IRQ_GPIO0) + (pin))
+
+#define VR41XX_IRQ_MAX       71
+
+#ifndef _LANGUAGE_ASSEMBLY
+#define __preg8		(volatile unsigned char*)
+#define __preg16	(volatile unsigned short*)
+#define __preg32	(volatile unsigned int*)
+#else
+#define __preg8
+#define __preg16
+#define __preg32
+#endif
+
+/* Embedded CPU peripheral registers */
+
+/* Bus Control Unit (BCU) */
+#define VR41XX_BCUCNTREG1	__preg16(KSEG1 + 0x0F000000)	/* BCU Control Register 1 */
+#define VR41XX_ROMSIZEREG	__preg16(KSEG1 + 0x0F000004)	/* ROM Size Register */
+#define VR41XX_ROMSPEEDREG	__preg16(KSEG1 + 0x0F000006)	/* BCU Access Cycle Change Register */
+#define VR41XX_BCUSPEEDREG	VR41XX_ROMSPEEDREG		/* BCU Access Cycle Change Register */
+#define VR41XX_IO0SPEEDREG	__preg16(KSEG1 + 0x0F000008)	/* I/O Access Cycle Change Register 0 */
+#define VR41XX_IO1SPEEDREG	__preg16(KSEG1 + 0x0F00000A)	/* I/O Access Cycle Change Register 1 */
+#define VR41XX_REVIDREG		__preg16(KSEG1 + 0x0F000010)	/* Revision ID Register */
+#define VR41XX_CLKSPEEDREG	__preg16(KSEG1 + 0x0F000014)	/* Clock Speed Register */
+#define VR41XX_BCUCNTREG3	__preg16(KSEG1 + 0x0F000016)	/* BCU Control Register 3 */
+#define VR41XX_BCUCACHECNTREG	__preg16(KSEG1 + 0x0F000018)	/* BCU Cache Control Register */
+
+/* DMA Address Unit (DMAAU) */
+#define VR41XX_CSIIBALREG	__preg16(KSEG1 + 0x0F000020)	/* CSI reception DMA base address register low */
+#define VR41XX_CSIIBAHREG	__preg16(KSEG1 + 0x0F000022)	/* CSI reception DMA base address register high */
+#define VR41XX_CSIIALREG	__preg16(KSEG1 + 0x0F000024)	/* CSI reception DMA address register low */
+#define VR41XX_CSIIAHREG	__preg16(KSEG1 + 0x0F000026)	/* CSI reception DMA address register high */
+#define VR41XX_CSIOBALREG	__preg16(KSEG1 + 0x0F000028)	/* CSI transmission DMA base address register low */
+#define VR41XX_CSIOBAHREG	__preg16(KSEG1 + 0x0F00002A)	/* CSI transmission DMA base address register high */
+#define VR41XX_CSIOALREG	__preg16(KSEG1 + 0x0F00002C)	/* CSI transmission DMA address register low */
+#define VR41XX_CSIOAHREG	__preg16(KSEG1 + 0x0F00002E)	/* CSI transmission DMA address register high */
+#define VR41XX_FIRBALREG	__preg16(KSEG1 + 0x0F000030)	/* FIR DMA Base Address Register Low */
+#define VR41XX_FIRBAHREG	__preg16(KSEG1 + 0x0F000032)	/* FIR DMA Base Address Register High */
+#define VR41XX_FIRALREG		__preg16(KSEG1 + 0x0F000034)	/* FIR DMA Address Register Low */
+#define VR41XX_FIRAHREG		__preg16(KSEG1 + 0x0F000036)	/* FIR DMA Address Register High */
+#define VR41XX_RAMBALREG	__preg16(KSEG1 + 0x0F0001E0)	/* RAM base address lower address between IO space and RAM */
+#define VR41XX_RAMBAHREG	__preg16(KSEG1 + 0x0F0001E2)	/* RAM base address higher address between IO space and RAM */
+#define VR41XX_RAMALREG		__preg16(KSEG1 + 0x0F0001E4)	/* RAM address lower address between IO space and RAM */
+#define VR41XX_RAMAHREG		__preg16(KSEG1 + 0x0F0001E6)	/* RAM address higher address between IO space and RAM */
+#define VR41XX_IOBALREG		__preg16(KSEG1 + 0x0F0001E8)	/* IO base address lower address between IO space and RAM */
+#define VR41XX_IOBAHREG		__preg16(KSEG1 + 0x0F0001EA)	/* IO base address higher address between IO space and RAM */
+#define VR41XX_IOALREG		__preg16(KSEG1 + 0x0F0001EC)	/* IO address lower address between IO space and RAM */
+#define VR41XX_IOAHREG		__preg16(KSEG1 + 0x0F0001EE)	/* IO address higher address between IO space and RAM */
+
+/* DMA Control Unit (DCU) */
+#define VR41XX_DMARSTREG	__preg16(KSEG1 + 0x0F000040)	/* DMA Reset Register */
+#define VR41XX_DMAIDLEREG	__preg16(KSEG1 + 0x0F000042)	/* DMA Idle Register */
+#define VR41XX_DMASENREG	__preg16(KSEG1 + 0x0F000044)	/* DMA Sequencer Enable Register */
+#define VR41XX_DMAMSKREG	__preg16(KSEG1 + 0x0F000046)	/* DMA Mask Register */
+#define VR41XX_DMAREQREG	__preg16(KSEG1 + 0x0F000048)	/* DMA Request Register */
+#define VR41XX_TDREG		__preg16(KSEG1 + 0x0F00004A)	/* Transfer Direction Register */
+#define VR41XX_DMAABITREG	__preg16(KSEG1 + 0x0F00004C)	/* DMA arbitration protocol selection register */
+#define VR41XX_CONTROLREG	__preg16(KSEG1 + 0x0F00004E)	/* DMA control register */
+#define VR41XX_BASSCNTLREG	__preg16(KSEG1 + 0x0F000050)	/* DMA transfer byte size register low */
+#define VR41XX_BASSCNTHREG	__preg16(KSEG1 + 0x0F000052)	/* DMA transfer byte size register high */
+#define VR41XX_CURRENTCNTLREG	__preg16(KSEG1 + 0x0F000054)	/* DMA remaining transfer byte size register low */
+#define VR41XX_CURRENTCNTHREG	__preg16(KSEG1 + 0x0F000056)	/* DMA remaining transfer byte size register high */
+#define VR41XX_TCINTR		__preg16(KSEG1 + 0x0F000058)	/* Terminal count interrupt request */
+
+/* Clock Mask Unit (CMU) */
+#define VR41XX_CMUCLKMSK	__preg16(KSEG1 + 0x0F000060)	/* CMU Clock Mask Register */
+#define VR41XX_CMUCLKMSK_MSKPIUPCLK	0x0001
+#define VR41XX_CMUCLKMSK_MSKSIU		0x0102
+
+/* Interrupt Control Unit (ICU) */
+#define VR41XX_SYSINT1REG	__preg16(KSEG1 + 0x0F000080)	/* Level 1 System interrupt register 1 */
+#define VR41XX_GIUINTLREG	__preg16(KSEG1 + 0x0F000088)	/* Level 2 GIU interrupt register Low */
+#define VR41XX_DSIUINTREG	__preg16(KSEG1 + 0x0F00008A)	/* Level 2 DSIU interrupt register */
+#define VR41XX_MSYSINT1REG	__preg16(KSEG1 + 0x0F00008C)	/* Level 1 mask system interrupt register 1 */
+#define VR41XX_MGIUINTLREG	__preg16(KSEG1 + 0x0F000094)	/* Level 2 mask GIU interrupt register Low */
+#define VR41XX_MDSIUINTREG	__preg16(KSEG1 + 0x0F000096)	/* Level 2 mask DSIU interrupt register */
+#define VR41XX_NMIREG		__preg16(KSEG1 + 0x0F000098)	/* NMI register */
+#define VR41XX_SOFTINTREG	__preg16(KSEG1 + 0x0F00009A)	/* Software interrupt register */
+#define VR41XX_SYSINT2REG	__preg16(KSEG1 + 0x0F0000A0)	/* Level 1 System interrupt register 2 */
+#define VR41XX_GIUINTHREG	__preg16(KSEG1 + 0x0F0000A2)	/* Level 2 GIU interrupt register High */
+#define VR41XX_FIRINTREG	__preg16(KSEG1 + 0x0F0000A4)	/* Level 2 FIR interrupt register */
+#define VR41XX_MSYSINT2REG	__preg16(KSEG1 + 0x0F0000A6)	/* Level 1 mask system interrupt register 2 */
+#define VR41XX_MGIUINTHREG	__preg16(KSEG1 + 0x0F0000A8)	/* Level 2 mask GIU interrupt register High */
+#define VR41XX_MFIRINTREG	__preg16(KSEG1 + 0x0F0000AA)	/* Level 2 mask FIR interrupt register */
+#define VR41XX_PCIINTREG	__preg16(KSEG1 + 0x0F0000AC)	/* Level 2 PCI interrupt register */
+#define VR41XX_SCUINTREG	__preg16(KSEG1 + 0x0F0000AE)	/* Level 2 SCU interrupt register */
+#define VR41XX_CSIINTREG	__preg16(KSEG1 + 0x0F0000B0)	/* Level 2 CSI interrupt register */
+#define VR41XX_MPCIINTREG	__preg16(KSEG1 + 0x0F0000B2)	/* Level 2 mask PCI interrupt register */
+#define VR41XX_MSCUINTREG	__preg16(KSEG1 + 0x0F0000B4)	/* Level 2 mask SCU interrupt register */
+#define VR41XX_MCSIINTREG	__preg16(KSEG1 + 0x0F0000B6)	/* Level 2 mask CSI interrupt register */
+
+/* Power Management Unit (PMU) */
+#define VR41XX_PMUINTREG	__preg16(KSEG1 + 0x0F0000C0)	/* PMU Status Register */
+#define VR41XX_PMUINT_POWERSW  0x1	/* Power switch */
+#define VR41XX_PMUINT_BATT     0x2	/* Low batt during normal operation */
+#define VR41XX_PMUINT_DEADMAN  0x4	/* Deadman's switch */
+#define VR41XX_PMUINT_RESET    0x8	/* Reset switch */
+#define VR41XX_PMUINT_RTCRESET 0x10	/* RTC Reset */
+#define VR41XX_PMUINT_TIMEOUT  0x20	/* HAL Timer Reset */
+#define VR41XX_PMUINT_BATTLOW  0x100	/* Battery low */
+#define VR41XX_PMUINT_RTC      0x200	/* RTC Alarm */
+#define VR41XX_PMUINT_DCD      0x400	/* DCD# */
+#define VR41XX_PMUINT_GPIO0    0x1000	/* GPIO0 */
+#define VR41XX_PMUINT_GPIO1    0x2000	/* GPIO1 */
+#define VR41XX_PMUINT_GPIO2    0x4000	/* GPIO2 */
+#define VR41XX_PMUINT_GPIO3    0x8000	/* GPIO3 */
+
+#define VR41XX_PMUCNTREG	__preg16(KSEG1 + 0x0F0000C2)	/* PMU Control Register */
+#define VR41XX_PMUINT2REG	__preg16(KSEG1 + 0x0F0000C4)	/* PMU Interrupt/Status 2 Register */
+#define VR41XX_PMUCNT2REG	__preg16(KSEG1 + 0x0F0000C6)	/* PMU Control 2 Resister */
+#define VR41XX_PMUWAITREG	__preg16(KSEG1 + 0x0F0000C8)	/* PMU Wait Counter Register */
+#define VR41XX_PMUTCLKDIVREG	__preg16(KSEG1 + 0x0F0000CC)	/* PMU Tclk Div mode register */
+#define VR41XX_PMUINTRCLKDIVREG	__preg16(KSEG1 + 0x0F0000CE)	/* PMU INT clock Div mode register */
+#define VR41XX_PMUCLKRUNREG	__preg16(KSEG1 + 0x0F0000D6)	/* PMU CLKRUN control register */
+
+
+/* Real Time Clock Unit (RTC) */
+#define VR41XX_ETIMELREG	__preg16(KSEG1 + 0x0F000100)	/* Elapsed Time L Register */
+#define VR41XX_ETIMEMREG	__preg16(KSEG1 + 0x0F000102)	/* Elapsed Time M Register */
+#define VR41XX_ETIMEHREG	__preg16(KSEG1 + 0x0F000104)	/* Elapsed Time H Register */
+#define VR41XX_ECMPLREG		__preg16(KSEG1 + 0x0F000108)	/* Elapsed Compare L Register */
+#define VR41XX_ECMPMREG		__preg16(KSEG1 + 0x0F00010A)	/* Elapsed Compare M Register */
+#define VR41XX_ECMPHREG		__preg16(KSEG1 + 0x0F00010C)	/* Elapsed Compare H Register */
+#define VR41XX_RTCL1LREG	__preg16(KSEG1 + 0x0F000110)	/* RTC Long 1 L Register */
+#define VR41XX_RTCL1HREG	__preg16(KSEG1 + 0x0F000112)	/* RTC Long 1 H Register */
+#define VR41XX_RTCL1CNTLREG	__preg16(KSEG1 + 0x0F000114)	/* RTC Long 1 Count L Register */
+#define VR41XX_RTCL1CNTHREG	__preg16(KSEG1 + 0x0F000116)	/* RTC Long 1 Count H Register */
+#define VR41XX_RTCL2LREG	__preg16(KSEG1 + 0x0F000118)	/* RTC Long 2 L Register */
+#define VR41XX_RTCL2HREG	__preg16(KSEG1 + 0x0F00011A)	/* RTC Long 2 H Register */
+#define VR41XX_RTCL2CNTLREG	__preg16(KSEG1 + 0x0F00011C)	/* RTC Long 2 Count L Register */
+#define VR41XX_RTCL2CNTHREG	__preg16(KSEG1 + 0x0F00011E)	/* RTC Long 2 Count H Register */
+#define VR41XX_TCLKLREG		__preg16(KSEG1 + 0x0F000120)	/* TCLK L Register */
+#define VR41XX_TCLKHREG		__preg16(KSEG1 + 0x0F000122)	/* TCLK H Register */
+#define VR41XX_TCLKCNTLREG	__preg16(KSEG1 + 0x0F000124)	/* TCLK Count L Register */
+#define VR41XX_TCLKCNTHREG	__preg16(KSEG1 + 0x0F000126)	/* TCLK Count H Register */
+#define VR41XX_RTCINTREG	__preg16(KSEG1 + 0x0F00013E)	/* RTC Interrupt Register */
+
+/* Deadman's Switch Unit (DSU) */
+#define VR41XX_DSUCNTREG	__preg16(KSEG1 + 0x0F0000E0)	/* DSU Control Register */
+#define VR41XX_DSUSETREG	__preg16(KSEG1 + 0x0F0000E2)	/* DSU Dead Time Set Register */
+#define VR41XX_DSUCLRREG	__preg16(KSEG1 + 0x0F0000E4)	/* DSU Clear Register */
+#define VR41XX_DSUTIMREG	__preg16(KSEG1 + 0x0F0000E6)	/* DSU Elapsed Time Register */
+
+/* General Purpose I/O Unit (GIU) */
+#define VR41XX_GIUIOSELL	__preg16(KSEG1 + 0x0F000140)	/* GPIO Input/Output Select Register L */
+#define VR41XX_GIUIOSELH	__preg16(KSEG1 + 0x0F000142)	/* GPIO Input/Output Select Register H */
+#define VR41XX_GIUPIODL		__preg16(KSEG1 + 0x0F000144)	/* GPIO Port Input/Output Data Register L */
+#define VR41XX_GIUPIODL_GPIO15  0x8000
+#define VR41XX_GIUPIODL_GPIO14  0x4000
+#define VR41XX_GIUPIODL_GPIO13  0x2000
+#define VR41XX_GIUPIODL_GPIO12  0x1000
+#define VR41XX_GIUPIODL_GPIO11  0x0800
+#define VR41XX_GIUPIODL_GPIO10  0x0400
+#define VR41XX_GIUPIODL_GPIO9  0x0200
+#define VR41XX_GIUPIODL_GPIO8  0x0100
+#define VR41XX_GIUPIODL_GPIO7  0x0080
+#define VR41XX_GIUPIODL_GPIO6  0x0040
+#define VR41XX_GIUPIODL_GPIO5  0x0020
+#define VR41XX_GIUPIODL_GPIO4  0x0010
+#define VR41XX_GIUPIODL_GPIO3  0x0008
+#define VR41XX_GIUPIODL_GPIO2  0x0004
+#define VR41XX_GIUPIODL_GPIO1  0x0002
+#define VR41XX_GIUPIODL_GPIO0  0x0001
+#define VR41XX_GIUPIODH		__preg16(KSEG1 + 0x0F000146)	/* GPIO Port Input/Output Data Register H */
+#define VR41XX_GIUPIODH_GPIO31  0x8000
+#define VR41XX_GIUPIODH_GPIO30  0x4000
+#define VR41XX_GIUPIODH_GPIO29  0x2000
+#define VR41XX_GIUPIODH_GPIO28  0x1000
+#define VR41XX_GIUPIODH_GPIO27  0x0800
+#define VR41XX_GIUPIODH_GPIO26  0x0400
+#define VR41XX_GIUPIODH_GPIO25  0x0200
+#define VR41XX_GIUPIODH_GPIO24  0x0100
+#define VR41XX_GIUPIODH_GPIO23  0x0080
+#define VR41XX_GIUPIODH_GPIO22  0x0040
+#define VR41XX_GIUPIODH_GPIO21  0x0020
+#define VR41XX_GIUPIODH_GPIO20  0x0010
+#define VR41XX_GIUPIODH_GPIO19  0x0008
+#define VR41XX_GIUPIODH_GPIO18  0x0004
+#define VR41XX_GIUPIODH_GPIO17  0x0002
+#define VR41XX_GIUPIODH_GPIO16  0x0001
+#define VR41XX_GIUINTSTATL	__preg16(KSEG1 + 0x0F000148)	/* GPIO Interrupt Status Register L */
+#define VR41XX_GIUINTSTATH	__preg16(KSEG1 + 0x0F00014A)	/* GPIO Interrupt Status Register H */
+#define VR41XX_GIUINTENL	__preg16(KSEG1 + 0x0F00014C)	/* GPIO Interrupt Enable Register L */
+#define VR41XX_GIUINTENH	__preg16(KSEG1 + 0x0F00014E)	/* GPIO Interrupt Enable Register H */
+#define VR41XX_GIUINTTYPL	__preg16(KSEG1 + 0x0F000150)	/* GPIO Interrupt Type (Edge or Level) Select Register */
+#define VR41XX_GIUINTTYPH	__preg16(KSEG1 + 0x0F000152)	/* GPIO Interrupt Type (Edge or Level) Select Register */
+#define VR41XX_GIUINTALSELL	__preg16(KSEG1 + 0x0F000154)	/* GPIO Interrupt Active Level Select Register L */
+#define VR41XX_GIUINTALSELH	__preg16(KSEG1 + 0x0F000156)	/* GPIO Interrupt Active Level Select Register H */
+#define VR41XX_GIUINTHTSELL	__preg16(KSEG1 + 0x0F000158)	/* GPIO Interrupt Hold/Through Select Register L */
+#define VR41XX_GIUINTHTSELH	__preg16(KSEG1 + 0x0F00015A)	/* GPIO Interrupt Hold/Through Select Register H */
+
+#define VR41XX_GIUPODATEN	__preg16(KSEG1 + 0x0F00015C)	/* GPIO Port Output Data Enable Register */
+#define VR41XX_GIUPODATL	__preg16(KSEG1 + 0x0F00015E)	/* GPIO Port Output Data Register L */
+#define VR41XX_GIUPODATL_GPIO47  0x8000
+#define VR41XX_GIUPODATL_GPIO46  0x4000
+#define VR41XX_GIUPODATL_GPIO45  0x2000
+#define VR41XX_GIUPODATL_GPIO44  0x1000
+#define VR41XX_GIUPODATL_GPIO43  0x0800
+#define VR41XX_GIUPODATL_GPIO42  0x0400
+#define VR41XX_GIUPODATL_GPIO41  0x0200
+#define VR41XX_GIUPODATL_GPIO40  0x0100
+#define VR41XX_GIUPODATL_GPIO39  0x0080
+#define VR41XX_GIUPODATL_GPIO38  0x0040
+#define VR41XX_GIUPODATL_GPIO37  0x0020
+#define VR41XX_GIUPODATL_GPIO36  0x0010
+#define VR41XX_GIUPODATL_GPIO35  0x0008
+#define VR41XX_GIUPODATL_GPIO34  0x0004
+#define VR41XX_GIUPODATL_GPIO33  0x0002
+#define VR41XX_GIUPODATL_GPIO32  0x0001
+#define VR41XX_GIUPODATL_PODAT15  0x8000
+#define VR41XX_GIUPODATL_PODAT14  0x4000
+#define VR41XX_GIUPODATL_PODAT13  0x2000
+#define VR41XX_GIUPODATL_PODAT12  0x1000
+#define VR41XX_GIUPODATL_PODAT11  0x0800
+#define VR41XX_GIUPODATL_PODAT10  0x0400
+#define VR41XX_GIUPODATL_PODAT9  0x0200
+#define VR41XX_GIUPODATL_PODAT8  0x0100
+#define VR41XX_GIUPODATL_PODAT7  0x0080
+#define VR41XX_GIUPODATL_PODAT6  0x0040
+#define VR41XX_GIUPODATL_PODAT5  0x0020
+#define VR41XX_GIUPODATL_PODAT4  0x0010
+#define VR41XX_GIUPODATL_PODAT3  0x0008
+#define VR41XX_GIUPODATL_PODAT2  0x0004
+#define VR41XX_GIUPODATL_PODAT1  0x0002
+#define VR41XX_GIUPODATL_PODAT0  0x0001
+#define VR41XX_SECIRQMASKL	VR41XX_GIUINTENL
+#define VR41XX_SECIRQMASKH	VR41XX_GIUINTENH
+
+/* SDRAM Control Unit (SDRAMU) */
+#define VR41XX_SDRAMMODEREG	__preg16(KSEG1 + 0x0F000400)	/* SDRAM mode register */
+#define VR41XX_SDRAMCNTREG	__preg16(KSEG1 + 0x0F000402)	/* SDRAM control register */
+#define VR41XX_BCURFCNTREG	__preg16(KSEG1 + 0x0F000404)	/* BCU refresh control register */
+#define VR41XX_BCURFCOUNTREG	__preg16(KSEG1 + 0x0F000406)	/* BCU refresh cycle count register */
+#define VR41XX_RAMSIZEREG	__preg16(KSEG1 + 0x0F000408)	/* DRAM size register */
+
+/* Debug Serial Interface Unit (DSIU) */
+#define VR41XX_PORTREG		__preg16(KSEG1 + 0x0F000820)	/* Port Change Register */
+#define VR41XX_MODEMREG		__preg16(KSEG1 + 0x0F000822)	/* Modem Control Register */
+#define VR41XX_ASIM00REG	__preg16(KSEG1 + 0x0F000824)	/* Asynchronous Mode 0 Register */
+#define VR41XX_ASIM01REG	__preg16(KSEG1 + 0x0F000826)	/* Asynchronous Mode 1 Register */
+#define VR41XX_RXB0RREG		__preg16(KSEG1 + 0x0F000828)	/* Receive Buffer Register (Extended) */
+#define VR41XX_RXB0LREG		__preg16(KSEG1 + 0x0F00082A)	/* Receive Buffer Register */
+#define VR41XX_TXS0RREG		__preg16(KSEG1 + 0x0F00082C)	/* Transmit Data Register (Extended) */
+#define VR41XX_TXS0LREG		__preg16(KSEG1 + 0x0F00082E)	/* Transmit Data Register */
+#define VR41XX_ASIS0REG		__preg16(KSEG1 + 0x0F000830)	/* Status Register */
+#define VR41XX_INTR0REG		__preg16(KSEG1 + 0x0F000832)	/* Debug SIU Interrupt Register */
+#define VR41XX_BPRM0REG		__preg16(KSEG1 + 0x0F000836)	/* Baud rate Generator Prescaler Mode Register */
+#define VR41XX_DSIURESETREG	__preg16(KSEG1 + 0x0F000838)	/* Debug SIU Reset Register */
+
+/* LED Control Unit (LED) */
+#define VR41XX_LEDHTSREG	__preg16(KSEG1 + 0x0F000180)	/* LED H Time Set register */
+#define VR41XX_LEDLTSREG	__preg16(KSEG1 + 0x0F000182)	/* LED L Time Set register */
+#define VR41XX_LEDCNTREG	__preg16(KSEG1 + 0x0F000188)	/* LED Control register */
+#define VR41XX_LEDASTCREG	__preg16(KSEG1 + 0x0F00018A)	/* LED Auto Stop Time Count register */
+#define VR41XX_LEDINTREG	__preg16(KSEG1 + 0x0F00018C)	/* LED Interrupt register */
+
+/* Serial Interface Unit (SIU / SIU1 and SIU2) */
+#define VR41XX_SIURB		__preg8(KSEG1 + 0x0F000800)	/* Receiver Buffer Register (Read) DLAB = 0 */
+#define VR41XX_SIUTH		__preg8(KSEG1 + 0x0F000800)	/* Transmitter Holding Register (Write) DLAB = 0 */
+#define VR41XX_SIUDLL		__preg8(KSEG1 + 0x0F000800)	/* Divisor Latch (Least Significant Byte) DLAB = 1 */
+#define VR41XX_SIUIE		__preg8(KSEG1 + 0x0F000801)	/* Interrupt Enable DLAB = 0 */
+#define VR41XX_SIUDLM		__preg8(KSEG1 + 0x0F000801)	/* Divisor Latch (Most Significant Byte) DLAB = 1 */
+#define VR41XX_SIUIID		__preg8(KSEG1 + 0x0F000802)	/* Interrupt Identification Register (Read) */
+#define VR41XX_SIUFC		__preg8(KSEG1 + 0x0F000802)	/* FIFO Control Register (Write) */
+#define VR41XX_SIULC		__preg8(KSEG1 + 0x0F000803)	/* Line Control Register */
+#define VR41XX_SIUMC		__preg8(KSEG1 + 0x0F000804)	/* MODEM Control Register */
+#define VR41XX_SIULS		__preg8(KSEG1 + 0x0F000805)	/* Line Status Register */
+#define VR41XX_SIUMS		__preg8(KSEG1 + 0x0F000806)	/* MODEM Status Register */
+#define VR41XX_SIUSC		__preg8(KSEG1 + 0x0F000807)	/* Scratch Register */
+#define VR41XX_SIUIRSEL		__preg8(KSEG1 + 0x0F000808)	/* SIU/FIR IrDA Selector */
+#define VR41XX_SIURESET		__preg8(KSEG1 + 0x0F000809)	/* SIU Reset Register */
+#define VR41XX_SIUCSEL		__preg8(KSEG1 + 0x0F00080A)	/* SIU Echo-Back Control Register */
+
+/* Fast IrDA Interface Unit (FIR) */
+#define VR41XX_FRSTR		__preg16(KSEG1 + 0x0F000840)	/* FIR Reset register */
+#define VR41XX_DPINTR		__preg16(KSEG1 + 0x0F000842)	/* DMA Page Interrupt register */
+#define VR41XX_DPCNTR		__preg16(KSEG1 + 0x0F000844)	/* DMA Control register */
+#define VR41XX_TDR		__preg16(KSEG1 + 0x0F000850)	/* Transmit Data register */
+#define VR41XX_RDR		__preg16(KSEG1 + 0x0F000852)	/* Receive Data register */
+#define VR41XX_IMR		__preg16(KSEG1 + 0x0F000854)	/* Interrupt Mask register */
+#define VR41XX_FSR		__preg16(KSEG1 + 0x0F000856)	/* FIFO Setup register */
+#define VR41XX_IRSR1		__preg16(KSEG1 + 0x0F000858)	/* Infrared Setup register 1 */
+#define VR41XX_CRCSR		__preg16(KSEG1 + 0x0F00085C)	/* CRC Setup register */
+#define VR41XX_FIRCR		__preg16(KSEG1 + 0x0F00085E)	/* FIR Control register */
+#define VR41XX_MIRCR		__preg16(KSEG1 + 0x0F000860)	/* MIR Control register */
+#define VR41XX_DMACR		__preg16(KSEG1 + 0x0F000862)	/* DMA Control register */
+#define VR41XX_DMAER		__preg16(KSEG1 + 0x0F000864)	/* DMA Enable register */
+#define VR41XX_TXIR		__preg16(KSEG1 + 0x0F000866)	/* Transmit Indication register */
+#define VR41XX_RXIR		__preg16(KSEG1 + 0x0F000868)	/* Receive Indication register */
+#define VR41XX_IFR		__preg16(KSEG1 + 0x0F00086A)	/* Interrupt Flag register */
+#define VR41XX_RXSTS		__preg16(KSEG1 + 0x0F00086C)	/* Receive Status */
+#define VR41XX_TXFL		__preg16(KSEG1 + 0x0F00086E)	/* Transmit Frame Length */
+#define VR41XX_MRXF		__preg16(KSEG1 + 0x0F000870)	/* Maximum Receive Frame Length */
+#define VR41XX_RXFL		__preg16(KSEG1 + 0x0F000874)	/* Receive Frame Length */
+
+/* PCI Interface Unit (PCIU) */
+#define VR41XX_PCIMMAW1REG	__preg32(KSEG1 + 0x0F000C00)
+#define VR41XX_PCIMMAW2REG	__preg32(KSEG1 + 0x0F000C04)
+#define VR41XX_PCITAW1REG	__preg32(KSEG1 + 0x0F000C08)
+#define VR41XX_PCITAW2REG	__preg32(KSEG1 + 0x0F000C0C)
+#define VR41XX_PCIMIOAWREG	__preg32(KSEG1 + 0x0F000C10)
+#define VR41XX_PCICONFDREG	__preg32(KSEG1 + 0x0F000C14)
+#define VR41XX_PCICONFAREG	__preg32(KSEG1 + 0x0F000C18)
+#define VR41XX_PCIMAILREG	__preg32(KSEG1 + 0x0F000C1C)
+#define VR41XX_BUSERRADREG	__preg32(KSEG1 + 0x0F000C24)
+#define VR41XX_INTCNTSTAREG	__preg32(KSEG1 + 0x0F000C28)
+#define VR41XX_PCIEXACCREG	__preg32(KSEG1 + 0x0F000C2C)
+#define VR41XX_PCIRECONTREG	__preg32(KSEG1 + 0x0F000C30)
+#define VR41XX_PCIENREG		__preg32(KSEG1 + 0x0F000C34)
+#define VR41XX_PCICLKSELREG	__preg32(KSEG1 + 0x0F000C38)
+#define VR41XX_PCITRDYVREG	__preg32(KSEG1 + 0x0F000C3C)
+#define VR41XX_PCICLKRUNREG	__preg16(KSEG1 + 0x0F000C60)
+
+#define VR41XX_PCIVENDORIDREG	__preg16(KSEG1 + 0x0F000D00)
+#define VR41XX_PCIDEVICEIDREG	__preg16(KSEG1 + 0x0F000D02)
+#define VR41XX_PCICOMMABDREG	__preg32(KSEG1 + 0x0F000D04)
+#define VR41XX_PCIREVREG	__preg32(KSEG1 + 0x0F000D08)
+#define VR41XX_PCICACHELSREG	__preg32(KSEG1 + 0x0F000D0C)
+#define VR41XX_PCIMAILBAREG	__preg32(KSEG1 + 0x0F000D10)
+#define VR41XX_PCIMBA1REG	__preg32(KSEG1 + 0x0F000D14)
+#define VR41XX_PCIMBA2REG	__preg32(KSEG1 + 0x0F000D18)
+#define VR41XX_PCIINTLINEREG	__preg32(KSEG1 + 0x0F000D3C)
+#define VR41XX_PCIRETVALREG	__preg32(KSEG1 + 0x0F000D40)
+
+#ifdef CONFIG_NEC_HARRIER
+
+/* physical address spaces */
+#define VR41XX_LCD             0x0a000000
+#define VR41XX_INTERNAL_IO_2   0x0b000000
+#define VR41XX_INTERNAL_IO_1   0x0c000000
+#define VR41XX_ISA_MEM         0x10000000
+#define VR41XX_ISA_IO          0x16000000
+#define VR41XX_ROM             0x18000000
+
+#define NEC_HARRIER_SIO1	__preg16(KSEG1 + 0x0A000000)
+#define NEC_HARRIER_SIO2	__preg16(KSEG1 + 0x0A000010)
+
+#define NEC_HARRIER_FLSHCNTREG	__preg8(KSEG1 + 0x0DFFFFA0)
+#define NEC_HARRIER_FLSHBANKREG	__preg8(KSEG1 + 0x0DFFFFA4)
+#define NEC_HARRIER_SWSETREG	__preg8(KSEG1 + 0x0DFFFFA8)
+#define NEC_HARRIER_LED1REG	__preg8(KSEG1 + 0x0DFFFFC0)
+#define NEC_HARRIER_LED2REG	__preg8(KSEG1 + 0x0DFFFFC4)
+#define NEC_HARRIER_SDBINTREG	__preg8(KSEG1 + 0x0DFFFFD0)
+#define NEC_HARRIER_SDBINTMASK	__preg8(KSEG1 + 0x0DFFFFD4)
+#define NEC_HARRIER_RSTREG	__preg8(KSEG1 + 0x0DFFFFD8)
+#define NEC_HARRIER_PCIINTREG	__preg8(KSEG1 + 0x0DFFFFDC)
+#define NEC_HARRIER_PCIINTMASK	__preg8(KSEG1 + 0x0DFFFFE0)
+#define NEC_HARRIER_PCICLKREG	__preg32(KSEG1 + 0x0DFFFFE4)
+
+#define NEC_HARRIER_DISPLAY_LEDS(x) \
+    do { \
+	*NEC_HARRIER_LED1REG = (unsigned char) ((x)       & 0xff); \
+        *NEC_HARRIER_LED2REG = (unsigned char)(((x) >> 8) & 0xff); \
+    } while (0)
+ 
+
+/* This is the base address for IO port decoding to which the 16 bit IO port address */
+/* is added.  Defining it to 0 will usually cause a kernel oops any time port IO is */
+/* attempted, which can be handy for turning up parts of the kernel that make */
+/* incorrect architecture assumptions (by assuming that everything acts like a PC), */
+/* but we need it correctly defined to use the PCMCIA/CF controller: */
+#define VR41XX_PORT_BASE	(KSEG1 + VR41XX_ISA_IO)
+#define VR41XX_ISAMEM_BASE	(KSEG1 + VR41XX_ISA_MEM)
+
+#else  /* CONFIG_NEC_HARRIER */
+
+#define NEC_HARRIER_DISPLAY_LEDS(x) {}
+
+#endif /* CONFIG_NEC_HARRIER */
+
+#endif /* __ASM_MIPS_VR4122_H */
diff -ruN linux-mips/include/asm-mips/vr4181.h linux-vr/include/asm-mips/vr4181.h
--- linux-mips/include/asm-mips/vr4181.h	Wed Dec 31 16:00:00 1969
+++ linux-vr/include/asm-mips/vr4181.h	Tue Oct 31 21:49:24 2000
@@ -0,0 +1,476 @@
+/* $Id: vr4181.h,v 1.2 2000/10/30 04:53:03 brad Exp $
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1999 by Michael Klar
+ */
+#ifndef __ASM_MIPS_VR4181_H 
+#define __ASM_MIPS_VR4181_H 
+
+#include <asm/addrspace.h>
+
+// CPU interrupts
+#define VR41XX_IRQ_SW1       0  // IP0 - Software interrupt
+#define VR41XX_IRQ_SW2       1  // IP1 - Software interrupt
+#define VR41XX_IRQ_INT0      2  // IP2 - All but battery, high speed modem, and real time clock
+#define VR41XX_IRQ_INT1      3  // IP3 - RTC Long1 (system timer)
+#define VR41XX_IRQ_INT2      4  // IP4 - RTC Long2
+#define VR41XX_IRQ_INT3      5  // IP5 - High Speed Modem (unused on VR4181)
+#define VR41XX_IRQ_INT4      6  // IP6 - Unused
+#define VR41XX_IRQ_TIMER     7  // IP7 - Timer interrupt from CPO_COMPARE (Note: RTC Long1 is the system timer.)
+
+// Cascaded from VR41XX_IRQ_INT0 (ICU mapped interrupts)
+#define VR41XX_IRQ_BATTERY   8
+#define VR41XX_IRQ_POWER     9
+#define VR41XX_IRQ_RTCL1     10  // Use VR41XX_IRQ_INT1 instead.
+#define VR41XX_IRQ_ETIMER    11
+#define VR41XX_IRQ_RFU12     12
+#define VR41XX_IRQ_PIU       13
+#define VR41XX_IRQ_AIU       14
+#define VR41XX_IRQ_KIU       15
+#define VR41XX_IRQ_GIU       16  // This is a cascade to IRQs 40-71. Do not use.
+#define VR41XX_IRQ_SIU       17
+#define VR41XX_IRQ_RFU18     18
+#define VR41XX_IRQ_SOFT      19
+#define VR41XX_IRQ_RFU20     20
+#define VR41XX_IRQ_DOZEPIU   21
+#define VR41XX_IRQ_RFU22     22
+#define VR41XX_IRQ_RFU23     23
+#define VR41XX_IRQ_RTCL2     24  // Use VR41XX_IRQ_INT2 instead.
+#define VR41XX_IRQ_LED       25
+#define VR41XX_IRQ_ECU       26  // (CompactFlash)
+#define VR41XX_IRQ_CSU       27
+#define VR41XX_IRQ_USB       28
+#define VR41XX_IRQ_DMA       29
+#define VR41XX_IRQ_LCD       30
+#define VR41XX_IRQ_RFU31     31
+#define VR41XX_IRQ_RFU32     32
+#define VR41XX_IRQ_RFU33     33
+#define VR41XX_IRQ_RFU34     34
+#define VR41XX_IRQ_RFU35     35
+#define VR41XX_IRQ_RFU36     36
+#define VR41XX_IRQ_RFU37     37
+#define VR41XX_IRQ_RFU38     38
+#define VR41XX_IRQ_RFU39     39
+// Note: Still need to do the extra VR4181 IRQ definitions
+
+// Cascaded from VR41XX_IRQ_GIU
+#define VR41XX_IRQ_GPIO0     40
+#define VR41XX_IRQ_GPIO1     41
+#define VR41XX_IRQ_GPIO2     42
+#define VR41XX_IRQ_GPIO3     43
+#define VR41XX_IRQ_GPIO4     44
+#define VR41XX_IRQ_GPIO5     45
+#define VR41XX_IRQ_GPIO6     46
+#define VR41XX_IRQ_GPIO7     47
+#define VR41XX_IRQ_GPIO8     48
+#define VR41XX_IRQ_GPIO9     49
+#define VR41XX_IRQ_GPIO10    50
+#define VR41XX_IRQ_GPIO11    51
+#define VR41XX_IRQ_GPIO12    52
+#define VR41XX_IRQ_GPIO13    53
+#define VR41XX_IRQ_GPIO14    54
+#define VR41XX_IRQ_GPIO15    55
+
+// Alternative to above GPIO IRQ defines
+#define VR41XX_IRQ_GPIO(pin) ((VR41XX_IRQ_GPIO0) + (pin))
+
+#define VR41XX_IRQ_MAX       55
+
+#ifndef _LANGUAGE_ASSEMBLY
+#define __preg8		(volatile unsigned char*)
+#define __preg16	(volatile unsigned short*)
+#define __preg32	(volatile unsigned int*)
+#else
+#define __preg8
+#define __preg16
+#define __preg32
+#endif
+
+// Embedded CPU peripheral registers
+// Note that many of the registers have different physical address for VR4181
+
+// Bus Control Unit (BCU)
+#define VR41XX_BCUCNTREG1	__preg16(KSEG1 + 0x0A000000)	/* BCU control register 1 (R/W) */
+#define VR41XX_CMUCLKMSK	__preg16(KSEG1 + 0x0A000004)	/* Clock mask register (R/W) */
+#define VR41XX_CMUCLKMSK_MSKCSUPCLK  0x0040
+#define VR41XX_CMUCLKMSK_MSKAIUPCLK  0x0020
+#define VR41XX_CMUCLKMSK_MSKPIUPCLK  0x0010
+#define VR41XX_CMUCLKMSK_MSKADUPCLK  0x0008
+#define VR41XX_CMUCLKMSK_MSKSIU18M   0x0004
+#define VR41XX_CMUCLKMSK_MSKADU18M   0x0002
+#define VR41XX_CMUCLKMSK_MSKUSB      0x0001
+#define VR41XX_CMUCLKMSK_MSKSIU      VR41XX_CMUCLKMSK_MSKSIU18M
+#define VR41XX_BCUSPEEDREG	__preg16(KSEG1 + 0x0A00000C)	/* BCU access time parameter (R/W) */
+#define VR41XX_BCURFCNTREG	__preg16(KSEG1 + 0x0A000010)	/* BCU refresh control register (R/W) */
+#define VR41XX_REVIDREG		__preg16(KSEG1 + 0x0A000014)	/* Revision ID register (R) */
+#define VR41XX_CLKSPEEDREG	__preg16(KSEG1 + 0x0A000018)	/* Clock speed register (R) */
+#define VR41XX_EDOMCYTREG	__preg16(KSEG1 + 0x0A000300)	/* Memory cycle timing register (R/W) */
+#define VR41XX_MEMCFG_REG	__preg16(KSEG1 + 0x0A000304)	/* Memory configuration register (R/W) */
+#define VR41XX_MODE_REG		__preg16(KSEG1 + 0x0A000308)	/* SDRAM mode register (R/W) */
+#define VR41XX_SDTIMINGREG	__preg16(KSEG1 + 0x0A00030C)	/* SDRAM timing register (R/W) */
+
+// DMA Control Unit (DCU)
+#define VR41XX_MICDEST1REG1	__preg16(KSEG1 + 0x0A000020)	/* Microphone destination 1 address register 1 (R/W) */
+#define VR41XX_MICDEST1REG2	__preg16(KSEG1 + 0x0A000022)	/* Microphone destination 1 address register 2 (R/W) */
+#define VR41XX_MICDEST2REG1	__preg16(KSEG1 + 0x0A000024)	/* Microphone destination 2 address register 1 (R/W) */
+#define VR41XX_MICDEST2REG2	__preg16(KSEG1 + 0x0A000026)	/* Microphone destination 2 address register 2 (R/W) */
+#define VR41XX_SPKRRC1REG1	__preg16(KSEG1 + 0x0A000028)	/* Speaker Source 1 address register 1 (R/W) */
+#define VR41XX_SPKRRC1REG2	__preg16(KSEG1 + 0x0A00002A)	/* Speaker Source 1 address register 2 (R/W) */
+#define VR41XX_SPKRRC2REG1	__preg16(KSEG1 + 0x0A00002C)	/* Speaker Source 2 address register 1 (R/W) */
+#define VR41XX_SPKRRC2REG2	__preg16(KSEG1 + 0x0A00002E)	/* Speaker Source 2 address register 2 (R/W) */
+#define VR41XX_DMARSTREG	__preg16(KSEG1 + 0x0A000040)	/* DMA Reset register (R/W) */
+#define VR41XX_AIUDMAMSKREG	__preg16(KSEG1 + 0x0A000046)	/* Audio DMA mask register (R/W) */
+#define VR41XX_USBDMAMSKREG	__preg16(KSEG1 + 0x0A000600)	/* USB DMA Mask register (R/W) */
+#define VR41XX_USBRXS1AREG1	__preg16(KSEG1 + 0x0A000602)	/* USB Rx source 1 address register 1 (R/W) */
+#define VR41XX_USBRXS1AREG2	__preg16(KSEG1 + 0x0A000604)	/* USB Rx source 1 address register 2 (R/W) */
+#define VR41XX_USBRXS2AREG1	__preg16(KSEG1 + 0x0A000606)	/* USB Rx source 2 address register 1 (R/W) */
+#define VR41XX_USBRXS2AREG2	__preg16(KSEG1 + 0x0A000608)	/* USB Rx source 2 address register 2 (R/W) */
+#define VR41XX_USBTXS1AREG1	__preg16(KSEG1 + 0x0A00060A)	/* USB Tx source 1 address register 1 (R/W) */
+#define VR41XX_USBTXS1AREG2	__preg16(KSEG1 + 0x0A00060C)	/* USB Tx source 1 address register 2 (R/W) */
+#define VR41XX_USBTXS2AREG1	__preg16(KSEG1 + 0x0A00060E)	/* USB Tx source 2 address register 1 (R/W) */
+#define VR41XX_USBTXS2AREG2	__preg16(KSEG1 + 0x0A000610)	/* USB Tx source 2 address register 2 (R/W) */
+#define VR41XX_USBRXD1AREG1	__preg16(KSEG1 + 0x0A00062A)	/* USB Rx destination 1 address register 1 (R/W) */
+#define VR41XX_USBRXD1AREG2	__preg16(KSEG1 + 0x0A00062C)	/* USB Rx destination 1 address register 2 (R/W) */
+#define VR41XX_USBRXD2AREG1	__preg16(KSEG1 + 0x0A00062E)	/* USB Rx destination 2 address register 1 (R/W) */
+#define VR41XX_USBRXD2AREG2	__preg16(KSEG1 + 0x0A000630)	/* USB Rx destination 2 address register 2 (R/W) */
+#define VR41XX_USBTXD1AREG1	__preg16(KSEG1 + 0x0A000632)	/* USB Tx destination 1 address register 1 (R/W) */
+#define VR41XX_USBTXD1AREG2	__preg16(KSEG1 + 0x0A000634)	/* USB Tx destination 1 address register 2 (R/W) */
+#define VR41XX_USBTXD2AREG1	__preg16(KSEG1 + 0x0A000636)	/* USB Tx destination 2 address register 1 (R/W) */
+#define VR41XX_USBTXD2AREG2	__preg16(KSEG1 + 0x0A000638)	/* USB Tx destination 2 address register 2 (R/W) */
+#define VR41XX_RxRCLENREG	__preg16(KSEG1 + 0x0A000652)	/* USB Rx record length register (R/W) */
+#define VR41XX_TxRCLENREG	__preg16(KSEG1 + 0x0A000654)	/* USB Tx record length register (R/W) */
+#define VR41XX_MICRCLENREG	__preg16(KSEG1 + 0x0A000658)	/* Microphone record length register (R/W) */
+#define VR41XX_SPKRCLENREG	__preg16(KSEG1 + 0x0A00065A)	/* Speaker record length register (R/W) */
+#define VR41XX_USBCFGREG	__preg16(KSEG1 + 0x0A00065C)	/* USB configuration register (R/W) */
+#define VR41XX_MICDMACFGREG	__preg16(KSEG1 + 0x0A00065E)	/* Microphone DMA configuration register (R/W) */
+#define VR41XX_SPKDMACFGREG	__preg16(KSEG1 + 0x0A000660)	/* Speaker DMA configuration register (R/W) */
+#define VR41XX_DMAITRQREG	__preg16(KSEG1 + 0x0A000662)	/* DMA interrupt request register (R/W) */
+#define VR41XX_DMACLTREG	__preg16(KSEG1 + 0x0A000664)	/* DMA control register (R/W) */
+#define VR41XX_DMAITMKREG	__preg16(KSEG1 + 0x0A000666)	/* DMA interrupt mask register (R/W) */
+
+// ISA Bridge
+#define VR41XX_ISABRGCTL	__preg16(KSEG1 + 0x0B0002C0)	/* ISA Bridge Control Register (R/W) */
+#define VR41XX_ISABRGSTS	__preg16(KSEG1 + 0x0B0002C2)	/* ISA Bridge Status Register (R/W) */
+#define VR41XX_XISACTL		__preg16(KSEG1 + 0x0B0002C4)	/* External ISA Control Register (R/W) */
+
+// Clocked Serial Interface (CSI)
+#define VR41XX_CSIMODE		__preg16(KSEG1 + 0x0B000900)	/* CSI Mode Register (R/W) */
+#define VR41XX_CSIRXDATA	__preg16(KSEG1 + 0x0B000902)	/* CSI Receive Data Register (R) */
+#define VR41XX_CSITXDATA	__preg16(KSEG1 + 0x0B000904)	/* CSI Transmit Data Register (R/W) */
+#define VR41XX_CSILSTAT		__preg16(KSEG1 + 0x0B000906)	/* CSI Line Status Register (R/W) */
+#define VR41XX_CSIINTMSK	__preg16(KSEG1 + 0x0B000908)	/* CSI Interrupt Mask Register (R/W) */
+#define VR41XX_CSIINTSTAT	__preg16(KSEG1 + 0x0B00090a)	/* CSI Interrupt Status Register (R/W) */
+#define VR41XX_CSITXBLEN	__preg16(KSEG1 + 0x0B00090c)	/* CSI Transmit Burst Length Register (R/W) */
+#define VR41XX_CSIRXBLEN	__preg16(KSEG1 + 0x0B00090e)	/* CSI Receive Burst Length Register (R/W) */
+
+// Interrupt Control Unit (ICU)
+#define VR41XX_SYSINT1REG	__preg16(KSEG1 + 0x0A000080)	/* Level 1 System interrupt register 1 (R) */
+#define VR41XX_MSYSINT1REG	__preg16(KSEG1 + 0x0A00008C)	/* Level 1 mask system interrupt register 1 (R/W) */
+#define VR41XX_NMIREG		__preg16(KSEG1 + 0x0A000098)	/* NMI register (R/W) */
+#define VR41XX_SOFTINTREG	__preg16(KSEG1 + 0x0A00009A)	/* Software interrupt register (R/W) */
+#define VR41XX_SYSINT2REG	__preg16(KSEG1 + 0x0A000200)	/* Level 1 System interrupt register 2 (R) */
+#define VR41XX_MSYSINT2REG	__preg16(KSEG1 + 0x0A000206)	/* Level 1 mask system interrupt register 2 (R/W) */
+#define VR41XX_PIUINTREGro	__preg16(KSEG1 + 0x0B000082)	/* Level 2 PIU interrupt register (R) */
+#define VR41XX_AIUINTREG	__preg16(KSEG1 + 0x0B000084)	/* Level 2 AIU interrupt register (R) */
+#define VR41XX_MPIUINTREG	__preg16(KSEG1 + 0x0B00008E)	/* Level 2 mask PIU interrupt register (R/W) */
+#define VR41XX_MAIUINTREG	__preg16(KSEG1 + 0x0B000090)	/* Level 2 mask AIU interrupt register (R/W) */
+#define VR41XX_MKIUINTREG	__preg16(KSEG1 + 0x0B000092)	/* Level 2 mask KIU interrupt register (R/W) */
+#define VR41XX_KIUINTREG	__preg16(KSEG1 + 0x0B000198)	/* Level 2 KIU interrupt register (R) */
+
+// Power Management Unit (PMU)
+#define VR41XX_PMUINTREG	__preg16(KSEG1 + 0x0B0000A0)	/* PMU Status Register (R/W) */
+#define VR41XX_PMUINT_POWERSW  0x1	/* Power switch */
+#define VR41XX_PMUINT_BATT     0x2	/* Low batt during normal operation */
+#define VR41XX_PMUINT_DEADMAN  0x4	/* Deadman's switch */
+#define VR41XX_PMUINT_RESET    0x8	/* Reset switch */
+#define VR41XX_PMUINT_RTCRESET 0x10	/* RTC Reset */
+#define VR41XX_PMUINT_TIMEOUT  0x20	/* HAL Timer Reset */
+#define VR41XX_PMUINT_BATTLOW  0x100	/* Battery low */
+#define VR41XX_PMUINT_RTC      0x200	/* RTC Alarm */
+#define VR41XX_PMUINT_DCD      0x400	/* DCD# */
+#define VR41XX_PMUINT_GPIO0    0x1000	/* GPIO0 */
+#define VR41XX_PMUINT_GPIO1    0x2000	/* GPIO1 */
+#define VR41XX_PMUINT_GPIO2    0x4000	/* GPIO2 */
+#define VR41XX_PMUINT_GPIO3    0x8000	/* GPIO3 */
+
+#define VR41XX_PMUCNTREG	__preg16(KSEG1 + 0x0B0000A2)	/* PMU Control Register (R/W) */
+#define VR41XX_PMUWAITREG	__preg16(KSEG1 + 0x0B0000A8)	/* PMU Wait Counter Register (R/W) */
+#define VR41XX_PMUDIVREG	__preg16(KSEG1 + 0x0B0000AC)	/* PMU Divide Mode Register (R/W) */
+#define VR41XX_DRAMHIBCTL	__preg16(KSEG1 + 0x0B0000B2)	/* DRAM Hibernate Control Register (R/W) */
+
+// Real Time Clock Unit (RTC)
+#define VR41XX_ETIMELREG	__preg16(KSEG1 + 0x0B0000C0)	/* Elapsed Time L Register (R/W) */
+#define VR41XX_ETIMEMREG	__preg16(KSEG1 + 0x0B0000C2)	/* Elapsed Time M Register (R/W) */
+#define VR41XX_ETIMEHREG	__preg16(KSEG1 + 0x0B0000C4)	/* Elapsed Time H Register (R/W) */
+#define VR41XX_ECMPLREG		__preg16(KSEG1 + 0x0B0000C8)	/* Elapsed Compare L Register (R/W) */
+#define VR41XX_ECMPMREG		__preg16(KSEG1 + 0x0B0000CA)	/* Elapsed Compare M Register (R/W) */
+#define VR41XX_ECMPHREG		__preg16(KSEG1 + 0x0B0000CC)	/* Elapsed Compare H Register (R/W) */
+#define VR41XX_RTCL1LREG	__preg16(KSEG1 + 0x0B0000D0)	/* RTC Long 1 L Register (R/W) */
+#define VR41XX_RTCL1HREG	__preg16(KSEG1 + 0x0B0000D2)	/* RTC Long 1 H Register (R/W) */
+#define VR41XX_RTCL1CNTLREG	__preg16(KSEG1 + 0x0B0000D4)	/* RTC Long 1 Count L Register (R) */
+#define VR41XX_RTCL1CNTHREG	__preg16(KSEG1 + 0x0B0000D6)	/* RTC Long 1 Count H Register (R) */
+#define VR41XX_RTCL2LREG	__preg16(KSEG1 + 0x0B0000D8)	/* RTC Long 2 L Register (R/W) */
+#define VR41XX_RTCL2HREG	__preg16(KSEG1 + 0x0B0000DA)	/* RTC Long 2 H Register (R/W) */
+#define VR41XX_RTCL2CNTLREG	__preg16(KSEG1 + 0x0B0000DC)	/* RTC Long 2 Count L Register (R) */
+#define VR41XX_RTCL2CNTHREG	__preg16(KSEG1 + 0x0B0000DE)	/* RTC Long 2 Count H Register (R) */
+#define VR41XX_RTCINTREG	__preg16(KSEG1 + 0x0B0001DE)	/* RTC Interrupt Register (R/W) */
+
+// Deadman's Switch Unit (DSU)
+#define VR41XX_DSUCNTREG	__preg16(KSEG1 + 0x0B0000E0)	/* DSU Control Register (R/W) */
+#define VR41XX_DSUSETREG	__preg16(KSEG1 + 0x0B0000E2)	/* DSU Dead Time Set Register (R/W) */
+#define VR41XX_DSUCLRREG	__preg16(KSEG1 + 0x0B0000E4)	/* DSU Clear Register (W) */
+#define VR41XX_DSUTIMREG	__preg16(KSEG1 + 0x0B0000E6)	/* DSU Elapsed Time Register (R/W) */
+
+// General Purpose I/O Unit (GIU)
+#define VR41XX_GPMD0REG		__preg16(KSEG1 + 0x0B000300)	/* GPIO Mode 0 Register (R/W) */
+#define VR41XX_GPMD1REG		__preg16(KSEG1 + 0x0B000302)	/* GPIO Mode 1 Register (R/W) */
+#define VR41XX_GPMD2REG		__preg16(KSEG1 + 0x0B000304)	/* GPIO Mode 2 Register (R/W) */
+#define VR41XX_GPMD3REG		__preg16(KSEG1 + 0x0B000306)	/* GPIO Mode 3 Register (R/W) */
+#define VR41XX_GPDATHREG	__preg16(KSEG1 + 0x0B000308)	/* GPIO Data High Register (R/W) */
+#define VR41XX_GPDATHREG_GPIO16  0x0001
+#define VR41XX_GPDATHREG_GPIO17  0x0002
+#define VR41XX_GPDATHREG_GPIO18  0x0004
+#define VR41XX_GPDATHREG_GPIO19  0x0008
+#define VR41XX_GPDATHREG_GPIO20  0x0010
+#define VR41XX_GPDATHREG_GPIO21  0x0020
+#define VR41XX_GPDATHREG_GPIO22  0x0040
+#define VR41XX_GPDATHREG_GPIO23  0x0080
+#define VR41XX_GPDATHREG_GPIO24  0x0100
+#define VR41XX_GPDATHREG_GPIO25  0x0200
+#define VR41XX_GPDATHREG_GPIO26  0x0400
+#define VR41XX_GPDATHREG_GPIO27  0x0800
+#define VR41XX_GPDATHREG_GPIO28  0x1000
+#define VR41XX_GPDATHREG_GPIO29  0x2000
+#define VR41XX_GPDATHREG_GPIO30  0x4000
+#define VR41XX_GPDATHREG_GPIO31  0x8000
+#define VR41XX_GPDATLREG	__preg16(KSEG1 + 0x0B00030A)	/* GPIO Data Low Register (R/W) */
+#define VR41XX_GPDATLREG_GPIO0   0x0001
+#define VR41XX_GPDATLREG_GPIO1   0x0002
+#define VR41XX_GPDATLREG_GPIO2   0x0004
+#define VR41XX_GPDATLREG_GPIO3   0x0008
+#define VR41XX_GPDATLREG_GPIO4   0x0010
+#define VR41XX_GPDATLREG_GPIO5   0x0020
+#define VR41XX_GPDATLREG_GPIO6   0x0040
+#define VR41XX_GPDATLREG_GPIO7   0x0080
+#define VR41XX_GPDATLREG_GPIO8   0x0100
+#define VR41XX_GPDATLREG_GPIO9   0x0200
+#define VR41XX_GPDATLREG_GPIO10  0x0400
+#define VR41XX_GPDATLREG_GPIO11  0x0800
+#define VR41XX_GPDATLREG_GPIO12  0x1000
+#define VR41XX_GPDATLREG_GPIO13  0x2000
+#define VR41XX_GPDATLREG_GPIO14  0x4000
+#define VR41XX_GPDATLREG_GPIO15  0x8000
+#define VR41XX_GPINTEN		__preg16(KSEG1 + 0x0B00030C)	/* GPIO Interrupt Enable Register (R/W) */
+#define VR41XX_GPINTMSK		__preg16(KSEG1 + 0x0B00030E)	/* GPIO Interrupt Mask Register (R/W) */
+#define VR41XX_GPINTTYPH	__preg16(KSEG1 + 0x0B000310)	/* GPIO Interrupt Type High Register (R/W) */
+#define VR41XX_GPINTTYPL	__preg16(KSEG1 + 0x0B000312)	/* GPIO Interrupt Type Low Register (R/W) */
+#define VR41XX_GPINTSTAT	__preg16(KSEG1 + 0x0B000314)	/* GPIO Interrupt Status Register (R/W) */
+#define VR41XX_GPHIBSTH		__preg16(KSEG1 + 0x0B000316)	/* GPIO Hibernate Pin State High Register (R/W) */
+#define VR41XX_GPHIBSTL		__preg16(KSEG1 + 0x0B000318)	/* GPIO Hibernate Pin State Low Register (R/W) */
+#define VR41XX_GPSICTL		__preg16(KSEG1 + 0x0B00031A)	/* GPIO Serial Interface Control Register (R/W) */
+#define VR41XX_KEYEN		__preg16(KSEG1 + 0x0B00031C)	/* Keyboard Scan Pin Enable Register (R/W) */
+#define VR41XX_PCS0STRA		__preg16(KSEG1 + 0x0B000320)	/* Programmable Chip Select [0] Start Address Register (R/W) */
+#define VR41XX_PCS0STPA		__preg16(KSEG1 + 0x0B000322)	/* Programmable Chip Select [0] Stop Address Register (R/W) */
+#define VR41XX_PCS0HIA		__preg16(KSEG1 + 0x0B000324)	/* Programmable Chip Select [0] High Address Register (R/W) */
+#define VR41XX_PCS1STRA		__preg16(KSEG1 + 0x0B000326)	/* Programmable Chip Select [1] Start Address Register (R/W) */
+#define VR41XX_PCS1STPA		__preg16(KSEG1 + 0x0B000328)	/* Programmable Chip Select [1] Stop Address Register (R/W) */
+#define VR41XX_PCS1HIA		__preg16(KSEG1 + 0x0B00032A)	/* Programmable Chip Select [1] High Address Register (R/W) */
+#define VR41XX_PCSMODE		__preg16(KSEG1 + 0x0B00032C)	/* Programmable Chip Select Mode Register (R/W) */
+#define VR41XX_LCDGPMODE	__preg16(KSEG1 + 0x0B00032E)	/* LCD General Purpose Mode Register (R/W) */
+#define VR41XX_MISCREG0		__preg16(KSEG1 + 0x0B000330)	/* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
+#define VR41XX_MISCREG1		__preg16(KSEG1 + 0x0B000332)	/* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
+#define VR41XX_MISCREG2		__preg16(KSEG1 + 0x0B000334)	/* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
+#define VR41XX_MISCREG3		__preg16(KSEG1 + 0x0B000336)	/* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
+#define VR41XX_MISCREG4		__preg16(KSEG1 + 0x0B000338)	/* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
+#define VR41XX_MISCREG5		__preg16(KSEG1 + 0x0B00033A)	/* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
+#define VR41XX_MISCREG6		__preg16(KSEG1 + 0x0B00033C)	/* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
+#define VR41XX_MISCREG7		__preg16(KSEG1 + 0x0B00033D)	/* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
+#define VR41XX_MISCREG8		__preg16(KSEG1 + 0x0B000340)	/* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
+#define VR41XX_MISCREG9		__preg16(KSEG1 + 0x0B000342)	/* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
+#define VR41XX_MISCREG10	__preg16(KSEG1 + 0x0B000344)	/* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
+#define VR41XX_MISCREG11	__preg16(KSEG1 + 0x0B000346)	/* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
+#define VR41XX_MISCREG12	__preg16(KSEG1 + 0x0B000348)	/* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
+#define VR41XX_MISCREG13	__preg16(KSEG1 + 0x0B00034A)	/* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
+#define VR41XX_MISCREG14	__preg16(KSEG1 + 0x0B00034C)	/* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
+#define VR41XX_MISCREG15	__preg16(KSEG1 + 0x0B00034E)	/* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
+#define VR41XX_SECIRQMASKL	VR41XX_GPINTEN
+// No SECIRQMASKH for VR4181
+
+// Touch Panel Interface Unit (PIU)
+#define VR41XX_PIUCNTREG	__preg16(KSEG1 + 0x0B000122)	/* PIU Control register (R/W) */
+#define VR41XX_PIUCNTREG_PIUSEQEN	0x0004
+#define VR41XX_PIUCNTREG_PIUPWR		0x0002
+#define VR41XX_PIUCNTREG_PADRST		0x0001
+
+#define VR41XX_PIUINTREG	__preg16(KSEG1 + 0x0B000124)	/* PIU Interrupt cause register (R/W) */
+#define VR41XX_PIUINTREG_OVP		0x8000
+#define VR41XX_PIUINTREG_PADCMD		0x0040
+#define VR41XX_PIUINTREG_PADADP		0x0020
+#define VR41XX_PIUINTREG_PADPAGE1	0x0010
+#define VR41XX_PIUINTREG_PADPAGE0	0x0008
+#define VR41XX_PIUINTREG_PADDLOST	0x0004
+#define VR41XX_PIUINTREG_PENCHG		0x0001
+
+#define VR41XX_PIUSIVLREG	__preg16(KSEG1 + 0x0B000126)	/* PIU Data sampling interval register (R/W) */
+#define VR41XX_PIUSTBLREG	__preg16(KSEG1 + 0x0B000128)	/* PIU A/D converter start delay register (R/W) */
+#define VR41XX_PIUCMDREG	__preg16(KSEG1 + 0x0B00012A)	/* PIU A/D command register (R/W) */
+#define VR41XX_PIUASCNREG	__preg16(KSEG1 + 0x0B000130)	/* PIU A/D port scan register (R/W) */
+#define VR41XX_PIUAMSKREG	__preg16(KSEG1 + 0x0B000132)	/* PIU A/D scan mask register (R/W) */
+#define VR41XX_PIUCIVLREG	__preg16(KSEG1 + 0x0B00013E)	/* PIU Check interval register (R) */
+#define VR41XX_PIUPB00REG	__preg16(KSEG1 + 0x0B0002A0)	/* PIU Page 0 Buffer 0 register (R/W) */
+#define VR41XX_PIUPB01REG	__preg16(KSEG1 + 0x0B0002A2)	/* PIU Page 0 Buffer 1 register (R/W) */
+#define VR41XX_PIUPB02REG	__preg16(KSEG1 + 0x0B0002A4)	/* PIU Page 0 Buffer 2 register (R/W) */
+#define VR41XX_PIUPB03REG	__preg16(KSEG1 + 0x0B0002A6)	/* PIU Page 0 Buffer 3 register (R/W) */
+#define VR41XX_PIUPB10REG	__preg16(KSEG1 + 0x0B0002A8)	/* PIU Page 1 Buffer 0 register (R/W) */
+#define VR41XX_PIUPB11REG	__preg16(KSEG1 + 0x0B0002AA)	/* PIU Page 1 Buffer 1 register (R/W) */
+#define VR41XX_PIUPB12REG	__preg16(KSEG1 + 0x0B0002AC)	/* PIU Page 1 Buffer 2 register (R/W) */
+#define VR41XX_PIUPB13REG	__preg16(KSEG1 + 0x0B0002AE)	/* PIU Page 1 Buffer 3 register (R/W) */
+#define VR41XX_PIUAB0REG	__preg16(KSEG1 + 0x0B0002B0)	/* PIU A/D scan Buffer 0 register (R/W) */
+#define VR41XX_PIUAB1REG	__preg16(KSEG1 + 0x0B0002B2)	/* PIU A/D scan Buffer 1 register (R/W) */
+#define VR41XX_PIUAB2REG	__preg16(KSEG1 + 0x0B0002B4)	/* PIU A/D scan Buffer 2 register (R/W) */
+#define VR41XX_PIUAB3REG	__preg16(KSEG1 + 0x0B0002B6)	/* PIU A/D scan Buffer 3 register (R/W) */
+#define VR41XX_PIUPB04REG	__preg16(KSEG1 + 0x0B0002BC)	/* PIU Page 0 Buffer 4 register (R/W) */
+#define VR41XX_PIUPB14REG	__preg16(KSEG1 + 0x0B0002BE)	/* PIU Page 1 Buffer 4 register (R/W) */
+
+// Audio Interface Unit (AIU)
+#define VR41XX_SODATREG		__preg16(KSEG1 + 0x0B000166)	/* Speaker Output Data Register (R/W) */
+#define VR41XX_SCNTREG		__preg16(KSEG1 + 0x0B000168)	/* Speaker Output Control Register (R/W) */
+#define VR41XX_MIDATREG		__preg16(KSEG1 + 0x0B000170)	/* Mike Input Data Register (R/W) */
+#define VR41XX_MCNTREG		__preg16(KSEG1 + 0x0B000172)	/* Mike Input Control Register (R/W) */
+#define VR41XX_DVALIDREG	__preg16(KSEG1 + 0x0B000178)	/* Data Valid Register (R/W) */
+#define VR41XX_SEQREG		__preg16(KSEG1 + 0x0B00017A)	/* Sequential Register (R/W) */
+#define VR41XX_INTREG		__preg16(KSEG1 + 0x0B00017C)	/* Interrupt Register (R/W) */
+#define VR41XX_SDMADATREG	__preg16(KSEG1 + 0x0B000160)	/* Speaker DMA Data Register (R/W) */
+#define VR41XX_MDMADATREG	__preg16(KSEG1 + 0x0B000162)	/* Microphone DMA Data Register (R/W) */
+#define VR41XX_DAVREF_SETUP	__preg16(KSEG1 + 0x0B000164)	/* DAC Vref setup register (R/W) */
+#define VR41XX_SCNVC_END	__preg16(KSEG1 + 0x0B00016E)	/* Speaker sample rate control (R/W) */
+#define VR41XX_MIDATREG		__preg16(KSEG1 + 0x0B000170)	/* Microphone Input Data Register (R/W) */
+#define VR41XX_MCNTREG		__preg16(KSEG1 + 0x0B000172)	/* Microphone Input Control Register (R/W) */
+#define VR41XX_MCNVC_END	__preg16(KSEG1 + 0x0B00017E)	/* Microphone sample rate control (R/W) */
+
+// Keyboard Interface Unit (KIU)
+#define VR41XX_KIUDAT0		__preg16(KSEG1 + 0x0B000180)	/* KIU Data0 Register (R/W) */
+#define VR41XX_KIUDAT1		__preg16(KSEG1 + 0x0B000182)	/* KIU Data1 Register (R/W) */
+#define VR41XX_KIUDAT2		__preg16(KSEG1 + 0x0B000184)	/* KIU Data2 Register (R/W) */
+#define VR41XX_KIUDAT3		__preg16(KSEG1 + 0x0B000186)	/* KIU Data3 Register (R/W) */
+#define VR41XX_KIUDAT4		__preg16(KSEG1 + 0x0B000188)	/* KIU Data4 Register (R/W) */
+#define VR41XX_KIUDAT5		__preg16(KSEG1 + 0x0B00018A)	/* KIU Data5 Register (R/W) */
+#define VR41XX_KIUSCANREP	__preg16(KSEG1 + 0x0B000190)	/* KIU Scan/Repeat Register (R/W) */
+#define VR41XX_KIUSCANREP_KEYEN      0x8000
+#define VR41XX_KIUSCANREP_SCANSTP    0x0008
+#define VR41XX_KIUSCANREP_SCANSTART  0x0004
+#define VR41XX_KIUSCANREP_ATSTP      0x0002
+#define VR41XX_KIUSCANREP_ATSCAN     0x0001
+#define VR41XX_KIUSCANS		__preg16(KSEG1 + 0x0B000192)	/* KIU Scan Status Register (R) */
+#define VR41XX_KIUWKS		__preg16(KSEG1 + 0x0B000194)	/* KIU Wait Keyscan Stable Register (R/W) */
+#define VR41XX_KIUWKI		__preg16(KSEG1 + 0x0B000196)	/* KIU Wait Keyscan Interval Register (R/W) */
+#define VR41XX_KIUINT		__preg16(KSEG1 + 0x0B000198)	/* KIU Interrupt Register (R/W) */
+#define VR41XX_KIUINT_KDATLOST       0x0004
+#define VR41XX_KIUINT_KDATRDY        0x0002
+#define VR41XX_KIUINT_SCANINT        0x0001
+#define VR41XX_KIUDAT6		__preg16(KSEG1 + 0x0B00018C)	/* Scan Line 6 Key Data Register (R) */
+#define VR41XX_KIUDAT7		__preg16(KSEG1 + 0x0B00018E)	/* Scan Line 7 Key Data Register (R) */
+
+// CompactFlash Controller
+#define VR41XX_PCCARDINDEX	__preg8(KSEG1 + 0x0B0008E0)	/* PC Card Controller Index Register */
+#define VR41XX_PCCARDDATA	__preg8(KSEG1 + 0x0B0008E1)	/* PC Card Controller Data Register */
+#define VR41XX_INTSTATREG	__preg16(KSEG1 + 0x0B0008F8)	/* Interrupt Status Register (R/W) */
+#define VR41XX_INTMSKREG	__preg16(KSEG1 + 0x0B0008FA)	/* Interrupt Mask Register (R/W) */
+#define VR41XX_CFG_REG_1	__preg16(KSEG1 + 0x0B0008FE)	/* Configuration Register 1 */
+
+// LED Control Unit (LED)
+#define VR41XX_LEDHTSREG	__preg16(KSEG1 + 0x0B000240)	/* LED H Time Set register (R/W) */
+#define VR41XX_LEDLTSREG	__preg16(KSEG1 + 0x0B000242)	/* LED L Time Set register (R/W) */
+#define VR41XX_LEDCNTREG	__preg16(KSEG1 + 0x0B000248)	/* LED Control register (R/W) */
+#define VR41XX_LEDASTCREG	__preg16(KSEG1 + 0x0B00024A)	/* LED Auto Stop Time Count register (R/W) */
+#define VR41XX_LEDINTREG	__preg16(KSEG1 + 0x0B00024C)	/* LED Interrupt register (R/W) */
+
+// Serial Interface Unit (SIU / SIU1 and SIU2)
+#define VR41XX_SIURB		__preg8(KSEG1 + 0x0C000010)	/* Receiver Buffer Register (Read) DLAB = 0 (R) */
+#define VR41XX_SIUTH		__preg8(KSEG1 + 0x0C000010)	/* Transmitter Holding Register (Write) DLAB = 0 (W) */
+#define VR41XX_SIUDLL		__preg8(KSEG1 + 0x0C000010)	/* Divisor Latch (Least Significant Byte) DLAB = 1 (R/W) */
+#define VR41XX_SIUIE		__preg8(KSEG1 + 0x0C000011)	/* Interrupt Enable DLAB = 0 (R/W) */
+#define VR41XX_SIUDLM		__preg8(KSEG1 + 0x0C000011)	/* Divisor Latch (Most Significant Byte) DLAB = 1 (R/W) */
+#define VR41XX_SIUIID		__preg8(KSEG1 + 0x0C000012)	/* Interrupt Identification Register (Read) (R) */
+#define VR41XX_SIUFC		__preg8(KSEG1 + 0x0C000012)	/* FIFO Control Register (Write) (W) */
+#define VR41XX_SIULC		__preg8(KSEG1 + 0x0C000013)	/* Line Control Register (R/W) */
+#define VR41XX_SIUMC		__preg8(KSEG1 + 0x0C000014)	/* MODEM Control Register (R/W) */
+#define VR41XX_SIULS		__preg8(KSEG1 + 0x0C000015)	/* Line Status Register (R/W) */
+#define VR41XX_SIUMS		__preg8(KSEG1 + 0x0C000016)	/* MODEM Status Register (R/W) */
+#define VR41XX_SIUSC		__preg8(KSEG1 + 0x0C000017)	/* Scratch Register (R/W) */
+#define VR41XX_SIURESET		__preg8(KSEG1 + 0x0C000019)	/* SIU Reset Register (R/W) */
+#define VR41XX_SIUACTMSK	__preg8(KSEG1 + 0x0C00001C)	/* SIU Activity Mask (R/W) */
+#define VR41XX_SIUACTTMR	__preg8(KSEG1 + 0x0C00001E)	/* SIU Activity Timer (R/W) */
+#define VR41XX_SIURB_2		__preg8(KSEG1 + 0x0C000000)	/* Receive Buffer Register (Read) (R) */
+#define VR41XX_SIUTH_2		__preg8(KSEG1 + 0x0C000000)	/* Transmitter Holding Register (Write) (W) */
+#define VR41XX_SIUDLL_2		__preg8(KSEG1 + 0x0C000000)	/* Divisor Latch (Least Significant Byte) (R/W) */
+#define VR41XX_SIUIE_2		__preg8(KSEG1 + 0x0C000001)	/* Interrupt Enable (DLAB = 0) (R/W) */
+#define VR41XX_SIUDLM_2		__preg8(KSEG1 + 0x0C000001)	/* Divisor Latch (Most Significant Byte) (DLAB = 1) (R/W) */
+#define VR41XX_SIUIID_2		__preg8(KSEG1 + 0x0C000002)	/* Interrupt Identification Register (Read) (R) */
+#define VR41XX_SIUFC_2		__preg8(KSEG1 + 0x0C000002)	/* FIFO Control Register (Write) (W) */
+#define VR41XX_SIULC_2		__preg8(KSEG1 + 0x0C000003)	/* Line Control Register (R/W) */
+#define VR41XX_SIUMC_2		__preg8(KSEG1 + 0x0C000004)	/* Modem Control Register (R/W) */
+#define VR41XX_SIULS_2		__preg8(KSEG1 + 0x0C000005)	/* Line Status Register (R/W) */
+#define VR41XX_SIUMS_2		__preg8(KSEG1 + 0x0C000006)	/* Modem Status Register (R/W) */
+#define VR41XX_SIUSC_2		__preg8(KSEG1 + 0x0C000007)	/* Scratch Register (R/W) */
+#define VR41XX_SIUIRSEL_2	__preg8(KSEG1 + 0x0C000008)	/* SIU IrDA Selectot (R/W) */
+#define VR41XX_SIURESET_2	__preg8(KSEG1 + 0x0C000009)	/* SIU Reset Register (R/W) */
+#define VR41XX_SIUCSEL_2	__preg8(KSEG1 + 0x0C00000A)	/* IrDA Echo-back Control (R/W) */
+#define VR41XX_SIUACTMSK_2	__preg8(KSEG1 + 0x0C00000C)	/* SIU Activity Mask Register (R/W) */
+#define VR41XX_SIUACTTMR_2	__preg8(KSEG1 + 0x0C00000E)	/* SIU Activity Timer Register (R/W) */
+
+
+// USB Module
+#define VR41XX_USBINFIFO	__preg16(KSEG1 + 0x0B000780)	/* USB Bulk Input FIFO (Bulk In End Point) (W) */
+#define VR41XX_USBOUTFIFO	__preg16(KSEG1 + 0x0B000782)	/* USB Bulk Output FIFO (Bulk Out End Point) (R) */
+#define VR41XX_USBCTLFIFO	__preg16(KSEG1 + 0x0B000784)	/* USB Control FIFO (Control End Point) (W) */
+#define VR41XX_USBSTAT		__preg16(KSEG1 + 0x0B000786)	/* Interrupt Status Register (R/W) */
+#define VR41XX_USBINTMSK	__preg16(KSEG1 + 0x0B000788)	/* Interrupt Mask Register (R/W) */
+#define VR41XX_USBCTLREG	__preg16(KSEG1 + 0x0B00078A)	/* Control Register (R/W) */
+#define VR41XX_USBSTPREG	__preg16(KSEG1 + 0x0B00078C)	/* USB Transfer Stop Register (R/W) */
+
+// LCD Controller
+#define VR41XX_HRTOTALREG	__preg16(KSEG1 + 0x0A000400)	/* Horizontal total Register (R/W) */
+#define VR41XX_HRVISIBREG	__preg16(KSEG1 + 0x0A000402)	/* Horizontal Visible Register (R/W) */
+#define VR41XX_LDCLKSTREG	__preg16(KSEG1 + 0x0A000404)	/* Load clock start Register (R/W) */
+#define VR41XX_LDCLKNDREG	__preg16(KSEG1 + 0x0A000406)	/* Load clock end Register (R/W) */
+#define VR41XX_VRTOTALREG	__preg16(KSEG1 + 0x0A000408)	/* Vertical Total Register (R/W) */
+#define VR41XX_VRVISIBREG	__preg16(KSEG1 + 0x0A00040A)	/* Vertical Visible Register (R/W) */
+#define VR41XX_FVSTARTREG	__preg16(KSEG1 + 0x0A00040C)	/* FLM vertical start Register (R/W) */
+#define VR41XX_FVENDREG		__preg16(KSEG1 + 0x0A00040E)	/* FLM vertical end Register (R/W) */
+#define VR41XX_LCDCTRLREG	__preg16(KSEG1 + 0x0A000410)	/* LCD control Register (R/W) */
+#define VR41XX_LCDINRQREG	__preg16(KSEG1 + 0x0A000412)	/* LCD Interrupt request Register (R/W) */
+#define VR41XX_LCDCFGREG0	__preg16(KSEG1 + 0x0A000414)	/* LCD Configuration Register 0 (R/W) */
+#define VR41XX_LCDCFGREG1	__preg16(KSEG1 + 0x0A000416)	/* LCD Configuration Register 1 (R/W) */
+#define VR41XX_FBSTAD1REG	__preg16(KSEG1 + 0x0A000418)	/* Frame Buffer Start Address 1 Register (R/W) */
+#define VR41XX_FBSTAD2REG	__preg16(KSEG1 + 0x0A00041A)	/* Frame Buffer Start Address 2 Register (R/W) */
+#define VR41XX_FBNDAD1REG	__preg16(KSEG1 + 0x0A000420)	/* Frame Buffer End Address 1 Register (R/W) */
+#define VR41XX_FBNDAD2REG	__preg16(KSEG1 + 0x0A000422)	/* Frame Buffer End Address 2 register (R/W) */
+#define VR41XX_FHSTARTREG	__preg16(KSEG1 + 0x0A000424)	/* FLM horizontal Start Register (R/W) */
+#define VR41XX_FHENDREG		__preg16(KSEG1 + 0x0A000426)	/* FLM horizontal End Register (R/W) */
+#define VR41XX_PWRCONREG1	__preg16(KSEG1 + 0x0A000430)	/* Power Control register 1 (R/W) */
+#define VR41XX_PWRCONREG2	__preg16(KSEG1 + 0x0A000432)	/* Power Control register 2 (R/W) */
+#define VR41XX_LCDIMSKREG	__preg16(KSEG1 + 0x0A000434)	/* LCD Interrupt Mask register (R/W) */
+#define VR41XX_CPINDCTREG	__preg16(KSEG1 + 0x0A00047E)	/* Color palette Index and control Register (R/W) */
+#define VR41XX_CPALDATREG	__preg32(KSEG1 + 0x0A000480)	/* Color palette data register (32bits Register) (R/W) */
+
+// physical address spaces
+#define VR41XX_LCD             0x0a000000
+#define VR41XX_INTERNAL_IO_2   0x0b000000
+#define VR41XX_INTERNAL_IO_1   0x0c000000
+#define VR41XX_ISA_MEM         0x10000000
+#define VR41XX_ISA_IO          0x14000000
+#define VR41XX_ROM             0x18000000
+
+// This is the base address for IO port decoding to which the 16 bit IO port address
+// is added.  Defining it to 0 will usually cause a kernel oops any time port IO is
+// attempted, which can be handy for turning up parts of the kernel that make
+// incorrect architecture assumptions (by assuming that everything acts like a PC),
+// but we need it correctly defined to use the PCMCIA/CF controller:
+#define VR41XX_PORT_BASE	(KSEG1 + VR41XX_ISA_IO)
+#define VR41XX_ISAMEM_BASE	(KSEG1 + VR41XX_ISA_MEM)
+
+#endif /* __ASM_MIPS_VR4181_H */
diff -ruN linux-mips/include/asm-mips/vr41xx-platdep.h linux-vr/include/asm-mips/vr41xx-platdep.h
--- linux-mips/include/asm-mips/vr41xx-platdep.h	Wed Dec 31 16:00:00 1969
+++ linux-vr/include/asm-mips/vr41xx-platdep.h	Thu Nov 23 15:05:41 2000
@@ -0,0 +1,655 @@
+/* $Id: vr41xx-platdep.h,v 1.35 2000/11/21 14:18:08 yuasa Exp $
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1999 by Michael Klar
+ */
+#ifndef __ASM_MIPS_VR41XX_PLATDEP_H 
+#define __ASM_MIPS_VR41XX_PLATDEP_H 
+
+/*
+ * This file contains the device-specific defines for VR41xx CPU-based
+ * platforms.  Anything CPU-specific should go in vr41xx.h instead.
+ * Eventually, most, if not all, dependancies on CONFIG_[device_name]
+ * should be moved in here, which should make it easier to add new
+ * device support.
+ */
+
+#include <linux/config.h>
+#include <asm/vr41xx.h>
+
+/*
+ * Here are the macros defined in this file and what they mean.  If not
+ * defined for a platform, reasonable defaults are used.
+ *
+ * DEVICE_IRQ_MASKL	IRQ mask for GPIO ints, to disable some IRQs for
+ *			autodetect.  A bitmask corresponding to IRQ #s
+ *			40 through 55.  A 0 bit means disabled, a 1 bit
+ *			will enable for autodetect only if the line is
+ *			configured as input at boot.
+ * DEVICE_IRQ_MASKH	Same for IRQ #s 56 through 71.  Note that a VR4111
+ * 			or VR4121-based device that uses 32-bit data bus
+ *			should probably set DEVICE_IRQ_MASKH to 0.
+ * ADJUSTED_PORT_BASE	Some devices have ISA IO ports at a different
+ *			offset than the standard.  In particular,
+ *			VRC4171 PCMCIA controller needs an extra offset.
+ *			This value is the virtual address corresponding
+ *			to ISA IO port 0.
+ * For VIDEORAM_* ad FB_*, see drivers/video/sfb.c for description, those
+ * are not used unless Simple Frame Buffer (or maybe one of its
+ * derivatives) is used.
+ * GPIO_BTN_MAP		Default map of GPIO lines to button definition.
+ * GPIO_BTN_PRESS_LOW	Define this if GPIO level 0 corresponds to a
+ *			button press.  Leave undefined if 1 correspods
+ *			to button press.
+ * KBD_SCANLINES	For devices with keyboards, the number of KIU
+ *			scanlines to use.  Default is all 12.
+ *
+ * (more to come...)
+ */
+
+#ifdef CONFIG_CASIO_E10
+#define VIDEORAM_BASE     (KSEG1 + 0x0a000000)
+#define FB_X_RES          240
+#define FB_X_VIRTUAL_RES  1024
+#define FB_Y_RES          320
+#define FB_BPP            2
+#define FB_IS_GREY        1
+#endif
+
+#ifdef CONFIG_CASIO_E15
+#define VIDEORAM_BASE     (KSEG1 + 0x0a000000)
+#define VIDEORAM_SIZE     (256 * 1024) /* ??? */
+#define FB_X_RES          240
+#define FB_X_VIRTUAL_RES  512
+#define FB_Y_RES          320
+#define FB_BPP            4
+#define FB_IS_GREY        1
+#define FB_IS_INVERSE     1
+#endif
+
+#ifdef CONFIG_CASIO_E105
+#define VIDEORAM_BASE     (KSEG1 + 0x0a200000)
+#define FB_X_RES          240
+#define FB_X_VIRTUAL_RES  256
+#define FB_Y_RES          320
+#define FB_BPP            16
+#endif
+
+#ifdef CONFIG_COMPAQ_AERO_15XX
+#define VIDEORAM_BASE     (KSEG1 + 0x0a000000)
+#define ADJUSTED_PORT_BASE (VR41XX_PORT_BASE + 0x01000000)
+#define FB_X_RES          320
+#define FB_Y_RES          240
+#define FB_BPP            4
+#define FB_IS_GREY        1
+#define FB_IS_INVERSE     1
+#define GPIO_BTN_MAP { 0, BTN_AP5, 0, 0, 0, 0, 0, \
+               BTN_EXIT, BTN_POWER, BTN_AP4, BTN_AP3, BTN_AP2, BTN_AP1, 0, \
+               0, 0, BTN_UP, BTN_DOWN, BTN_ACTION, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
+#define VR41XX_ENABLE_SPEAKER()		\
+	{				\
+		unsigned long flags;	\
+		save_and_cli(flags);	\
+		*VR41XX_GIUPODATL |= (VR41XX_GIUPODATL_GPIO33 | \
+				      VR41XX_GIUPODATL_GPIO34); \
+		restore_flags(flags);	\
+	}
+#define VR41XX_DISABLE_SPEAKER()	\
+	{				\
+		unsigned long flags;	\
+		save_and_cli(flags);	\
+		*VR41XX_GIUPODATL &= ~(VR41XX_GIUPODATL_GPIO33 | \
+				       VR41XX_GIUPODATL_GPIO34); \
+		restore_flags(flags);	\
+	}
+#define VR41XX_ENABLE_SERIAL(x)		\
+	*VR41XX_GIUPIODL &= ~VR41XX_GIUPIODL_GPIO15;
+#define VR41XX_DISABLE_SERIAL(x)	\
+	*VR41XX_GIUPIODL |= VR41XX_GIUPIODL_GPIO15;
+#endif
+
+#ifdef CONFIG_COMPAQ_AERO_21XX
+#define VIDEORAM_BASE     (KSEG1 + 0x0a000000)
+#define FB_X_RES          320
+#define FB_Y_RES          240
+#define FB_BPP            8
+#endif
+
+#ifdef CONFIG_EVEREX_FREESTYLE
+#define DEVICE_IRQ_MASKL 0xfffb
+#define DEVICE_IRQ_MASKH 0xffff
+#define ADJUSTED_PORT_BASE (VR41XX_PORT_BASE + 0x01000000)
+#define VIDEORAM_SIZE  (256 * 1024)
+#define FB_X_RES       320
+#define FB_Y_RES       240
+#define FB_BPP         4
+#define FB_IS_GREY     1
+#define FB_IS_INVERSE  1
+#define GPIO_BTN_MAP { 0, BTN_AP5, 0, 0, BTN_UP, BTN_DOWN, BTN_ACTION, \
+		BTN_EXIT, BTN_CONTRAST, BTN_AP1, BTN_AP2, BTN_AP3, BTN_AP4, 0, \
+		0, 0, 0, 0, 0, 0, BTN_BACKLIGHT, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
+#define GPIO_BTN_PRESS_LOW
+#define VR41XX_ENABLE_SERIAL(x)		\
+	*VR41XX_GIUPODATH |= VR41XX_GIUPODATH_GPIO48;
+#define VR41XX_DISABLE_SERIAL(x)	\
+	*VR41XX_GIUPODATH &= ~VR41XX_GIUPODATH_GPIO48;
+
+#define VR41XX_ENABLE_SPEAKER()		\
+	{				\
+		unsigned long flags;	\
+		save_and_cli(flags);	\
+		*VR41XX_GIUPODATL |= VR41XX_GIUPODATL_GPIO44; \
+		restore_flags(flags);	\
+	}
+#define VR41XX_DISABLE_SPEAKER()		\
+	{				\
+		unsigned long flags;	\
+		save_and_cli(flags);	\
+		*VR41XX_GIUPODATL &= ~VR41XX_GIUPODATL_GPIO44; \
+		restore_flags(flags);	\
+	}
+#endif
+
+#ifdef CONFIG_IBM_WORKPAD
+#define DEVICE_IRQ_MASKL 0xffff
+#define DEVICE_IRQ_MASKH 0x0000
+#define ADJUSTED_PORT_BASE (VR41XX_PORT_BASE + 0x01000000)
+#define VIDEORAM_BASE  (KSEG1 + 0x0a000000)
+#define FB_X_RES       640
+#define FB_Y_RES       480
+#define FB_BPP         16
+#define GPIO_BTN_MAP { 0, BTN_AP5, BTN_NOTIFICATION, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
+#define GPIO_BTN_PRESS_LOW
+#define VR41XX_ENABLE_SPEAKER()		\
+	{				\
+		unsigned long flags;	\
+		save_and_cli(flags);	\
+		*VR41XX_GIUPODATH |= VR41XX_GIUPODATH_GPIO49; \
+		restore_flags(flags);	\
+	}
+#define VR41XX_DISABLE_SPEAKER()		\
+	{				\
+		unsigned long flags;	\
+		save_and_cli(flags);	\
+		*VR41XX_GIUPODATH &= ~VR41XX_GIUPODATH_GPIO49; \
+		restore_flags(flags);	\
+	}
+#endif
+
+#ifdef CONFIG_AGENDA_VR3
+#define GPIO_BTN_MAP { \
+	0, 0, 0, 0, 0, 0, 0, BTN_AP2, \
+	BTN_SYNC, BTN_AP1, 0, 0, 0, 0, 0, 0 \
+}
+#undef GPIO_BTN_PRESS_LOW
+#define VR41XX_ENABLE_IRDA()  irda_power(1);
+#define VR41XX_DISABLE_IRDA() irda_power(0);
+#endif
+
+#ifdef CONFIG_NEC_MOBILEPRO_700
+#define VIDEORAM_BASE  (KSEG1 + 0x0a000000)
+#define VIDEORAM_SIZE  (64 * 1024)
+#define FB_X_VIRTUAL_RES  1024
+#define FB_X_RES       640
+#define FB_Y_RES       240
+#define FB_BPP         2
+#define FB_IS_GREY     1
+// GPIO[12] is speaker power on/off bit
+#define VR41XX_ENABLE_SPEAKER()		\
+	{				\
+		unsigned long flags;	\
+		save_and_cli(flags);	\
+		*VR41XX_GIUPIODL |= VR41XX_GIUPIODL_GPIO12; \
+		restore_flags(flags);	\
+	}
+#define VR41XX_DISABLE_SPEAKER()		\
+	{				\
+		unsigned long flags;	\
+		save_and_cli(flags);	\
+		*VR41XX_GIUPIODL &= ~VR41XX_GIUPIODL_GPIO12; \
+		restore_flags(flags);	\
+	}
+#endif
+
+#ifdef CONFIG_NEC_MOBILEPRO_750C
+#define VIDEORAM_BASE  (KSEG1 + 0x13000000)
+#define FB_X_VIRTUAL_RES  1024
+#define FB_X_RES       640
+#define FB_Y_RES       240
+#define FB_BPP         8
+// GPIO[12] is speaker power on/off bit
+#define VR41XX_ENABLE_SPEAKER()		\
+	{				\
+		unsigned long flags;	\
+		save_and_cli(flags);	\
+		*VR41XX_GIUPIODL |= VR41XX_GIUPIODL_GPIO12; \
+		restore_flags(flags);	\
+	}
+#define VR41XX_DISABLE_SPEAKER()		\
+	{				\
+		unsigned long flags;	\
+		save_and_cli(flags);	\
+		*VR41XX_GIUPIODL &= ~VR41XX_GIUPIODL_GPIO12; \
+		restore_flags(flags);	\
+	}
+#endif
+
+#ifdef CONFIG_NEC_MOBILEPRO_770
+// Tested by Jean-Nicolas, thanks!
+#define VIDEORAM_BASE  (KSEG1 + 0x0a000000)
+#define VIDEORAM_SIZE  (640 * 240 * 8)
+#define FB_X_VIRTUAL_RES  800
+#define FB_X_RES       640
+#define FB_Y_RES       240
+#define FB_BPP         16
+// GIUPODAT[12] is speaker power on/off bit confirmed by Checkstuff.exe
+#define VR41XX_ENABLE_SPEAKER()		\
+	{				\
+		unsigned long flags;	\
+		save_and_cli(flags);	\
+		*VR41XX_GIUPODATL |= VR41XX_GIUPODATL_GPIO44; \
+		restore_flags(flags);	\
+	}
+#define VR41XX_DISABLE_SPEAKER()		\
+	{				\
+		unsigned long flags;	\
+		save_and_cli(flags);	\
+		*VR41XX_GIUPODATL &= ~VR41XX_GIUPODATL_GPIO44; \
+		restore_flags(flags);	\
+	}
+#endif
+
+#ifdef CONFIG_NEC_MOBILEPRO_800
+#define VIDEORAM_BASE     (KSEG1 + 0x0a000000)
+#define FB_X_RES          800
+#define FB_Y_RES          600
+#define FB_BPP            16
+// GPIO[12] is speaker power on/off bit
+#define VR41XX_ENABLE_SPEAKER()		\
+	{				\
+		unsigned long flags;	\
+		save_and_cli(flags);	\
+		*VR41XX_GIUPIODL |= VR41XX_GIUPIODL_GPIO12; \
+		restore_flags(flags);	\
+	}
+#define VR41XX_DISABLE_SPEAKER()		\
+	{				\
+		unsigned long flags;	\
+		save_and_cli(flags);	\
+		*VR41XX_GIUPIODL &= ~VR41XX_GIUPIODL_GPIO12; \
+		restore_flags(flags);	\
+	}
+#endif
+
+#ifdef CONFIG_NEC_OSPREY
+// AP4 did strange things, Backlight button GPIO currently used for IOCS16,
+//  AP2 used for debug board Ethernet controller, AP3 just doesn't work
+#define GPIO_BTN_MAP { BTN_CONTRAST, BTN_UP, BTN_DOWN, 0, BTN_AP1, BTN_EXIT, 0, \
+		0, BTN_ACTION, 0, 0, 0, 0, 0, 0, 0 }
+#undef GPIO_BTN_PRESS_LOW
+#endif
+
+#ifdef CONFIG_NEC_UEB30
+#define VIDEORAM_BASE     (KSEG1 + 0x0a000000)
+#define FB_X_RES          640
+#define FB_Y_RES          480
+#define FB_BPP            8
+#endif
+
+#ifdef CONFIG_VADEM_CLIO_1000
+#define VR41XX_ENABLE_SERIAL(x)		\
+	*VR41XX_GIUPODATL |= VR41XX_GIUPODATL_GPIO42;
+#define VR41XX_DISABLE_SERIAL(x)	\
+	*VR41XX_GIUPODATL &= ~VR41XX_GIUPODATL_GPIO42;
+#define KBD_SCANLINES 8
+#endif
+
+#ifdef CONFIG_VADEM_CLIO_1050
+#define KBD_SCANLINES 8
+#define VIDEORAM_BASE   (KSEG1 + 0x0a200000)
+#define FB_X_RES        640
+#define FB_Y_RES        480
+#define FB_BPP          16
+#endif
+
+#ifdef CONFIG_NEC_MOBILEGEAR2_R300
+#define VIDEORAM_BASE  (KSEG1 + 0x0a000000)
+#define VIDEORAM_SIZE  (64 * 1024)
+#define FB_X_VIRTUAL_RES  1024
+#define FB_X_RES       640
+#define FB_Y_RES       240
+#define FB_BPP         2
+#define FB_IS_GREY     1
+// GPIO[12] is speaker power on/off bit
+#define VR41XX_ENABLE_SPEAKER()		\
+	{				\
+		unsigned long flags;	\
+		save_and_cli(flags);	\
+		*VR41XX_GIUPIODL |= VR41XX_GIUPIODL_GPIO12; \
+		restore_flags(flags);	\
+	}
+#define VR41XX_DISABLE_SPEAKER()		\
+	{				\
+		unsigned long flags;	\
+		save_and_cli(flags);	\
+		*VR41XX_GIUPIODL &= ~VR41XX_GIUPIODL_GPIO12; \
+		restore_flags(flags);	\
+	}
+// GPIO[14] is serial power on/off bit
+#define VR41XX_ENABLE_SERIAL(x)		\
+	*VR41XX_GIUPIODL |= VR41XX_GIUPIODL_GPIO14;
+#define VR41XX_DISABLE_SERIAL(x)	\
+	*VR41XX_GIUPIODL &= ~VR41XX_GIUPIODL_GPIO14;
+#endif
+
+#ifdef CONFIG_NEC_MOBILEGEAR2_R320
+#define VIDEORAM_BASE  (KSEG1 + 0x0a000000)
+#define VIDEORAM_SIZE  (64 * 1024)
+#define FB_X_VIRTUAL_RES  640
+#define FB_X_RES       640
+#define FB_Y_RES       240
+#define FB_BPP         2
+#define FB_IS_GREY     1
+// GPIO[12] is speaker power on/off bit
+#define VR41XX_ENABLE_SPEAKER()		\
+	{				\
+		unsigned long flags;	\
+		save_and_cli(flags);	\
+		*VR41XX_GIUPIODL |= VR41XX_GIUPIODL_GPIO12; \
+		restore_flags(flags);	\
+	}
+#define VR41XX_DISABLE_SPEAKER()		\
+	{				\
+		unsigned long flags;	\
+		save_and_cli(flags);	\
+		*VR41XX_GIUPIODL &= ~VR41XX_GIUPIODL_GPIO12; \
+		restore_flags(flags);	\
+	}
+// GPIO[14] is serial power on/off bit
+#define VR41XX_ENABLE_SERIAL(x)		\
+	*VR41XX_GIUPIODL |= VR41XX_GIUPIODL_GPIO14;
+#define VR41XX_DISABLE_SERIAL(x)	\
+	*VR41XX_GIUPIODL &= ~VR41XX_GIUPIODL_GPIO14;
+#endif
+
+#ifdef CONFIG_NEC_MOBILEGEAR2_R430
+#define DEVICE_IRQ_MASKL 0xffff
+#define DEVICE_IRQ_MASKH 0x0000
+#define VIDEORAM_BASE  (KSEG1 + 0x0a180100)
+#define VIDEORAM_SIZE  (640 * 240 * 8)
+#define FB_X_VIRTUAL_RES  640
+#define FB_X_RES       640
+#define FB_Y_RES       240
+#define FB_BPP         16
+// GIUPODAT[12] is speaker power on/off bit confirmed by Checkstuff.exe
+#define VR41XX_ENABLE_SPEAKER()		\
+	{				\
+		unsigned long flags;	\
+		save_and_cli(flags);	\
+		*VR41XX_GIUPODATL |= VR41XX_GIUPODATL_GPIO44; \
+		restore_flags(flags);	\
+	}
+#define VR41XX_DISABLE_SPEAKER()		\
+	{				\
+		unsigned long flags;	\
+		save_and_cli(flags);	\
+		*VR41XX_GIUPODATL &= ~VR41XX_GIUPODATL_GPIO44; \
+		restore_flags(flags);	\
+	}
+// GPIO[14] is serial power on/off bit
+#define VR41XX_ENABLE_SERIAL(x)		\
+	*VR41XX_GIUPIODL |= VR41XX_GIUPIODL_GPIO14;
+#define VR41XX_DISABLE_SERIAL(x)	\
+	*VR41XX_GIUPIODL &= ~VR41XX_GIUPIODL_GPIO14;
+#endif
+
+
+#ifdef CONFIG_NEC_MOBILEGEAR2_R500
+#define VIDEORAM_BASE  (KSEG1 + 0x13000000)
+#define VIDEORAM_SIZE  (640 * 240 * 8)
+#define FB_X_VIRTUAL_RES  1024
+#define FB_X_RES       640
+#define FB_Y_RES       240
+#define FB_BPP         8
+// #define FB_IS_GRAY     1
+// GPIO[12] is speaker power on/off bit
+#define VR41XX_ENABLE_SPEAKER()		\
+	{				\
+		unsigned long flags;	\
+		save_and_cli(flags);	\
+		*VR41XX_GIUPIODL |= VR41XX_GIUPIODL_GPIO12; \
+		restore_flags(flags);	\
+	}
+#define VR41XX_DISABLE_SPEAKER()		\
+	{				\
+		unsigned long flags;	\
+		save_and_cli(flags);	\
+		*VR41XX_GIUPIODL &= ~VR41XX_GIUPIODL_GPIO12; \
+		restore_flags(flags);	\
+	}
+// GPIO[14] is serial power on/off bit
+#define VR41XX_ENABLE_SERIAL(x)		\
+	*VR41XX_GIUPIODL |= VR41XX_GIUPIODL_GPIO14;
+#define VR41XX_DISABLE_SERIAL(x)	\
+	*VR41XX_GIUPIODL &= ~VR41XX_GIUPIODL_GPIO14;
+#endif
+
+#ifdef CONFIG_NEC_MOBILEGEAR2_R510
+// Not tested yet
+#define VIDEORAM_BASE  (KSEG1 + 0x0a000000)
+#define VIDEORAM_SIZE  (640 * 240 * 8)
+#define FB_X_VIRTUAL_RES  1024
+#define FB_X_RES       640
+#define FB_Y_RES       240
+#define FB_BPP         8
+// GIUPODAT[12] is speaker power on/off bit confirmed by Checkstuff.exe
+#define VR41XX_ENABLE_SPEAKER()		\
+	{				\
+		unsigned long flags;	\
+		save_and_cli(flags);	\
+		*VR41XX_GIUPODATL |= VR41XX_GIUPODATL_GPIO44; \
+		restore_flags(flags);	\
+	}
+#define VR41XX_DISABLE_SPEAKER()		\
+	{				\
+		unsigned long flags;	\
+		save_and_cli(flags);	\
+		*VR41XX_GIUPODATL &= ~VR41XX_GIUPODATL_GPIO44; \
+		restore_flags(flags);	\
+	}
+// GPIO[14] is serial power on/off bit
+#define VR41XX_ENABLE_SERIAL(x)		\
+	*VR41XX_GIUPIODL |= VR41XX_GIUPIODL_GPIO14;
+#define VR41XX_DISABLE_SERIAL(x)	\
+	*VR41XX_GIUPIODL &= ~VR41XX_GIUPIODL_GPIO14;
+#endif
+
+#ifdef CONFIG_NEC_MOBILEGEAR2_R520
+#define VIDEORAM_BASE  (KSEG1 + 0x0a000000)
+#define VIDEORAM_SIZE  (640 * 240 * 8)
+#define FB_X_VIRTUAL_RES  800
+#define FB_X_RES       640
+#define FB_Y_RES       240
+#define FB_BPP         16
+// GIUPODAT[12] is speaker power on/off bit confirmed by Checkstuff.exe
+#define VR41XX_ENABLE_SPEAKER()		\
+	{				\
+		unsigned long flags;	\
+		save_and_cli(flags);	\
+		*VR41XX_GIUPODATL |= VR41XX_GIUPODATL_GPIO44; \
+		restore_flags(flags);	\
+	}
+#define VR41XX_DISABLE_SPEAKER()		\
+	{				\
+		unsigned long flags;	\
+		save_and_cli(flags);	\
+		*VR41XX_GIUPODATL &= ~VR41XX_GIUPODATL_GPIO44; \
+		restore_flags(flags);	\
+	}
+// GPIO[14] is serial power on/off bit
+#define VR41XX_ENABLE_SERIAL(x)		\
+	*VR41XX_GIUPIODL |= VR41XX_GIUPIODL_GPIO14;
+#define VR41XX_DISABLE_SERIAL(x)	\
+	*VR41XX_GIUPIODL &= ~VR41XX_GIUPIODL_GPIO14;
+#endif
+
+#ifdef CONFIG_NEC_MOBILEGEAR2_R530
+#define DEVICE_IRQ_MASKL 0xffff
+#define DEVICE_IRQ_MASKH 0x0000
+#define VIDEORAM_BASE  (KSEG1 + 0x0a180100)
+#define VIDEORAM_SIZE  (640 * 240 * 8)
+#define FB_X_VIRTUAL_RES  640
+#define FB_X_RES       640
+#define FB_Y_RES       240
+#define FB_BPP         16
+// GIUPODAT[12] is speaker power on/off bit confirmed by Checkstuff.exe
+#define VR41XX_ENABLE_SPEAKER()		\
+	{				\
+		unsigned long flags;	\
+		save_and_cli(flags);	\
+		*VR41XX_GIUPODATL |= VR41XX_GIUPODATL_GPIO44; \
+		restore_flags(flags);	\
+	}
+#define VR41XX_DISABLE_SPEAKER()		\
+	{				\
+		unsigned long flags;	\
+		save_and_cli(flags);	\
+		*VR41XX_GIUPODATL &= ~VR41XX_GIUPODATL_GPIO44; \
+		restore_flags(flags);	\
+	}
+// GPIO[14] is serial power on/off bit
+#define VR41XX_ENABLE_SERIAL(x)		\
+	*VR41XX_GIUPIODL |= VR41XX_GIUPIODL_GPIO14;
+#define VR41XX_DISABLE_SERIAL(x)	\
+	*VR41XX_GIUPIODL &= ~VR41XX_GIUPIODL_GPIO14;
+#endif
+
+#ifdef CONFIG_DOCOMO_SIGMARION
+#define VIDEORAM_BASE  (KSEG1 + 0x0a000000)
+#define VIDEORAM_SIZE  (640 * 240 * 8)
+#define FB_X_VIRTUAL_RES  640
+#define FB_X_RES       640
+#define FB_Y_RES       240
+#define FB_BPP         16
+// GIUPODAT[12] is speaker power on/off bit confirmed by Checkstuff.exe
+#define VR41XX_ENABLE_SPEAKER()		\
+	{				\
+		unsigned long flags;	\
+		save_and_cli(flags);	\
+		*VR41XX_GIUPODATL |= VR41XX_GIUPODATL_GPIO44; \
+		restore_flags(flags);	\
+	}
+#define VR41XX_DISABLE_SPEAKER()		\
+	{				\
+		unsigned long flags;	\
+		save_and_cli(flags);	\
+		*VR41XX_GIUPODATL &= ~VR41XX_GIUPODATL_GPIO44; \
+		restore_flags(flags);	\
+	}
+// GPIO[14] is serial power on/off bit
+#define VR41XX_ENABLE_SERIAL(x)		\
+	*VR41XX_GIUPIODL |= VR41XX_GIUPIODL_GPIO14;
+#define VR41XX_DISABLE_SERIAL(x)	\
+	*VR41XX_GIUPIODL &= ~VR41XX_GIUPIODL_GPIO14;
+#endif
+
+#ifdef CONFIG_NEC_MOBILEGEAR2_R700
+// Not tested yet
+#define VIDEORAM_BASE  (KSEG1 + 0x0a000000)
+#define VIDEORAM_SIZE  (640 * 240 * 8)
+#define FB_X_VIRTUAL_RES  800
+#define FB_X_RES       800
+#define FB_Y_RES       600
+#define FB_BPP         16
+// GPIO[12] is speaker power on/off bit
+#define VR41XX_ENABLE_SPEAKER()		\
+	{				\
+		unsigned long flags;	\
+		save_and_cli(flags);	\
+		*VR41XX_GIUPIODL |= VR41XX_GIUPIODL_GPIO12; \
+		restore_flags(flags);	\
+	}
+#define VR41XX_DISABLE_SPEAKER()	\
+	{				\
+		unsigned long flags;	\
+		save_and_cli(flags);	\
+		*VR41XX_GIUPIODL &= ~VR41XX_GIUPIODL_GPIO12; \
+		restore_flags(flags);	\
+	}
+// PODAT[14](GPIO[46]) is serial power on/off bit
+#define VR41XX_ENABLE_SERIAL(x)		\
+	*VR41XX_GIUPODATL |= VR41XX_GIUPODATL_GPIO46;
+#define VR41XX_DISABLE_SERIAL(x)	\
+	*VR41XX_GIUPODATL &= ~VR41XX_GIUPODATL_GPIO46;
+#endif
+
+#ifdef CONFIG_NEC_HARRIER
+#define VIDEORAMBASE   (KSEG1 + 0x10400000)
+#define FB_X_RES       800
+#define FB_Y_RES       600
+#define FB_BPP         8
+#define VIDEORAM_SIZE (FB_X_RES * FB_Y_RES * FB_BPP / 8)
+#define KBD_SCANLINES 8
+#define GPIO_BTN_MAP { 					\
+	    BTN_AP1, 0, 0, BTN_AP2,			\
+	    0, 0, 0, BTN_BACKLIGHT,			\
+	    0, BTN_AP3, 0, 0,				\
+	    BTN_AP4, 0, 0, 0,				\
+	    0, 0, 0, 0,					\
+	    0, 0, 0, 0,					\
+	    0, 0, 0, 0,					\
+	    0, 0, 0, 0,					\
+	    0, 0, 0, 0, 				\
+	    0, 0, 0, 0, 				\
+	    BTN_AP25, BTN_AP26, BTN_AP27, BTN_AP28,	\
+	    BTN_AP29, BTN_AP30, BTN_AP31, BTN_AP32,	\
+	    BTN_AP33, BTN_AP34, BTN_AP35, BTN_AP36	\
+	}
+#endif
+
+// Some reasonable defaults
+
+#ifndef DEVICE_IRQ_MASKL
+#define DEVICE_IRQ_MASKL 0xffff
+#endif
+
+#ifndef DEVICE_IRQ_MASKH
+#ifndef CONFIG_CPU_VR4181
+#define DEVICE_IRQ_MASKH 0xffff
+#endif
+#endif
+
+#ifndef ADJUSTED_PORT_BASE
+#define ADJUSTED_PORT_BASE VR41XX_PORT_BASE
+#endif
+
+#ifndef VR41XX_ENABLE_SPEAKER
+#define	VR41XX_ENABLE_SPEAKER()		do { } while (0)
+#endif
+#ifndef VR41XX_DISABLE_SPEAKER
+#define	VR41XX_DISABLE_SPEAKER()	do { } while (0)
+#endif
+
+#ifndef VR41XX_ENABLE_SERIAL
+#define VR41XX_ENABLE_SERIAL(x)		do { } while (0)
+#endif
+#ifndef VR41XX_DISABLE_SERIAL
+#define VR41XX_DISABLE_SERIAL(x)	do { } while (0)
+#endif
+
+#ifndef VR41XX_ENABLE_IRDA
+#define VR41XX_ENABLE_IRDA()		do { } while (0)
+#endif
+#ifndef VR41XX_DISABLE_IRDA
+#define VR41XX_DISABLE_IRDA()		do { } while (0)
+#endif
+
+#ifndef KBD_SCANLINES
+#define KBD_SCANLINES 12
+#endif
+
+#endif /* __ASM_MIPS_VR41XX_PLATDEP_H */
diff -ruN linux-mips/include/asm-mips/vr41xx.h linux-vr/include/asm-mips/vr41xx.h
--- linux-mips/include/asm-mips/vr41xx.h	Wed Dec 31 16:00:00 1969
+++ linux-vr/include/asm-mips/vr41xx.h	Thu Nov 23 11:57:43 2000
@@ -0,0 +1,28 @@
+/* $Id: vr41xx.h,v 1.14 2000/11/15 20:04:24 mikemac Exp $
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1999 by Michael Klar
+ */
+#ifndef __ASM_MIPS_VR41XX_H 
+#define __ASM_MIPS_VR41XX_H 
+
+#ifdef __KERNEL__
+
+#include <linux/config.h>
+
+#ifdef CONFIG_CPU_VR4181
+#include <asm/vr4181.h>
+#else
+#ifdef CONFIG_CPU_VR4122
+#include <asm/vr4122.h>
+#else
+#include <asm/vr4121.h>
+#endif
+#endif
+
+#endif /* __KERNEL__ */
+
+#endif
diff -ruN linux-mips/include/asm-mips/vrc4171.h linux-vr/include/asm-mips/vrc4171.h
--- linux-mips/include/asm-mips/vrc4171.h	Wed Dec 31 16:00:00 1969
+++ linux-vr/include/asm-mips/vrc4171.h	Sun Sep 10 13:29:18 2000
@@ -0,0 +1,457 @@
+/*
+ * linux/include/asm-mips/vrc4171.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1999 by Steve K. Longerbeam
+ * Copyright (C) 2000 Michael Klar <wyldfier@iname.com>
+ */
+
+#ifndef __ASM_MIPS_VRC4171_H_
+#define __ASM_MIPS_VRC4171_H_
+
+#include <asm/vr41xx.h>
+
+//
+// LCD display and PCMCIA controller base addresses
+//
+#define VRC4171_LCD_BASE    (KSEG1 + VR41XX_LCD)
+#define VRC4171_LCDMEM_BASE VRC4171_LCD_BASE
+#define VRC4171_LCDREG_BASE (VRC4171_LCD_BASE + 0x00800000)
+#define VRC4171_PCMCIA_BASE (KSEG1 + VR41XX_ISA_IO + 0x01000000)
+ 
+#define VRC4171_Config1          __preg16(VRC4171_PCMCIA_BASE + 0x05fe)
+#define VRC4171_Config2          __preg16(VRC4171_PCMCIA_BASE + 0x05fc)
+#define VRC4171_IntrStat         __preg16(VRC4171_PCMCIA_BASE + 0x05fa)
+#define VRC4171_GPIOControlData  __preg16(VRC4171_PCMCIA_BASE + 0x05ee)
+
+// NOTE: These reg defs are unconfirmed by documentation.  In fact, I'm
+// not real sure where they came from.  This may be a VRC4171 vs VRC4171A
+// issue, since the only documentation available is for VRC4171A.  MFK
+#define VRC4171_PCS0UpperStrtStp __preg16(VRC4171_PCMCIA_BASE + 0x05ec)
+#define VRC4171_PCS0LowerStart   __preg16(VRC4171_PCMCIA_BASE + 0x05ea)
+#define VRC4171_PCS0LowerStop    __preg16(VRC4171_PCMCIA_BASE + 0x05e8)
+#define VRC4171_PCS1UpperStrtStp __preg16(VRC4171_PCMCIA_BASE + 0x05e6)
+#define VRC4171_PCS1LowerStart   __preg16(VRC4171_PCMCIA_BASE + 0x05e4)
+#define VRC4171_PCS1LowerStop    __preg16(VRC4171_PCMCIA_BASE + 0x05e2)
+
+// These reg defs are per the VRC4171A documentation:
+#define VRC4171A_PCS0UpperStart  __preg16(VRC4171_PCMCIA_BASE + 0x05ec)
+#define VRC4171A_PCS0LowerStart  __preg16(VRC4171_PCMCIA_BASE + 0x05ea)
+#define VRC4171A_PCS0UpperStop   __preg16(VRC4171_PCMCIA_BASE + 0x05e8)
+#define VRC4171A_PCS0LowerStop   __preg16(VRC4171_PCMCIA_BASE + 0x05e6)
+#define VRC4171A_PCS1UpperStart  __preg16(VRC4171_PCMCIA_BASE + 0x05e4)
+#define VRC4171A_PCS1LowerStart  __preg16(VRC4171_PCMCIA_BASE + 0x05e2)
+#define VRC4171A_PCS1UpperStop   __preg16(VRC4171_PCMCIA_BASE + 0x05de)
+#define VRC4171A_PCS1LowerStop   __preg16(VRC4171_PCMCIA_BASE + 0x05dc)
+
+// The PCIC Index and Data registers
+#define VRC4171_PCICINDEX        __preg8(VRC4171_PCMCIA_BASE + 0x03e0)
+#define VRC4171_PCICDATA         __preg8(VRC4171_PCMCIA_BASE + 0x03e1)
+
+// The LCD registers
+#define VRC4171_PanelSelect      __preg16(VRC4171_LCDREG_BASE + 0x0000)
+#define VRC4171_LCDPanelCtl      __preg16(VRC4171_LCDREG_BASE + 0x0002)
+#define VRC4171_PowerModeCtl     __preg16(VRC4171_LCDREG_BASE + 0x0004)
+#define VRC4171_MCLKEnable       __preg16(VRC4171_LCDREG_BASE + 0x0006)
+#define VRC4171_VCLKEnable       __preg16(VRC4171_LCDREG_BASE + 0x0008)
+#define VRC4171_VidFIFOMemIntCtl __preg16(VRC4171_LCDREG_BASE + 0x000A)
+#define VRC4171_PixelAdjVertHalf __preg16(VRC4171_LCDREG_BASE + 0x000C)
+#define VRC4171_HorzDisplayCtl   __preg16(VRC4171_LCDREG_BASE + 0x0010)
+#define VRC4171_HorzRetrCtl      __preg16(VRC4171_LCDREG_BASE + 0x0012)
+#define VRC4171_VertDispEndCtl   __preg16(VRC4171_LCDREG_BASE + 0x0014)
+#define VRC4171_VertDispCtl      __preg16(VRC4171_LCDREG_BASE + 0x0016)
+#define VRC4171_VertRetrStartCtl __preg16(VRC4171_LCDREG_BASE + 0x0018)
+#define VRC4171_VertRetrEndCtl   __preg16(VRC4171_LCDREG_BASE + 0x001A)
+#define VRC4171_StartingAddress  __preg16(VRC4171_LCDREG_BASE + 0x001C)
+#define VRC4171_Offset           __preg16(VRC4171_LCDREG_BASE + 0x001E)
+#define VRC4171_HardwareCurCtl   __preg16(VRC4171_LCDREG_BASE + 0x0020)
+#define VRC4171_HardwareCurXPos  __preg16(VRC4171_LCDREG_BASE + 0x0022)
+#define VRC4171_HardwareCurYPos  __preg16(VRC4171_LCDREG_BASE + 0x0024)
+#define VRC4171_HardwareCurClr0A __preg16(VRC4171_LCDREG_BASE + 0x0026)
+#define VRC4171_HardwareCurClr0B __preg16(VRC4171_LCDREG_BASE + 0x0028)
+#define VRC4171_HardwareCurClr1A __preg16(VRC4171_LCDREG_BASE + 0x002A)
+#define VRC4171_HardwareCurClr1B __preg16(VRC4171_LCDREG_BASE + 0x002C)
+#define VRC4171_HardwareCurOrign __preg16(VRC4171_LCDREG_BASE + 0x002E)
+#define VRC4171_RAMWriteAddress  __preg16(VRC4171_LCDREG_BASE + 0x0040)
+#define VRC4171_RAMWritePort0    __preg16(VRC4171_LCDREG_BASE + 0x0042)
+#define VRC4171_RAMWritePort1    __preg16(VRC4171_LCDREG_BASE + 0x0044)
+// Note: RAMRead doesn't seem to work on VRC4171, maybe another VRC4171A diff
+#define VRC4171_RAMReadAddress   __preg16(VRC4171_LCDREG_BASE + 0x0046)
+#define VRC4171_RAMReadPort0     __preg16(VRC4171_LCDREG_BASE + 0x0048)
+#define VRC4171_RAMReadPort1     __preg16(VRC4171_LCDREG_BASE + 0x004A)
+#define VRC4171_ScratchPadReg0   __preg16(VRC4171_LCDREG_BASE + 0x0050)
+#define VRC4171_ScratchPadReg1   __preg16(VRC4171_LCDREG_BASE + 0x0052)
+
+//-----------------------------------------------------------
+// Configuration I Register (VRC4171_Config1) Bit Definitions
+//-----------------------------------------------------------
+
+#define SLOT_B_NONE                        0x0000
+#define SLOT_B_PCMCIA                      0x4000
+#define SLOT_B_COMP_FLASH                  0x8000
+#define SLOT_B_MINI                        0xc000
+#define SLOT_B_MASK                        0xc000
+#define EN_OR                              0x2000
+#define EN_VCLK                            0x1000
+#define EN_BUSCLK                          0x0800
+#define IO_UADEC                           0x0200
+#define VMCLK_DIV8                         0x01c0
+#define VMCLK_DIV7                         0x0180
+#define VMCLK_DIV6                         0x0140
+#define VMCLK_DIV5                         0x0100
+#define VMCLK_DIV4                         0x00c0
+#define VMCLK_DIV3                         0x0080
+#define VMCLK_DIV2                         0x0040
+#define VMCLK_DIV1                         0x0000
+#define VCLK_DIV8                          0x0038
+#define VCLK_DIV7                          0x0030
+#define VCLK_DIV6                          0x0028
+#define VCLK_DIV5                          0x0020
+#define VCLK_DIV4                          0x0018
+#define VCLK_DIV3                          0x0010
+#define VCLK_DIV2                          0x0008
+#define VCLK_DIV1                          0x0000
+
+//------------------------------------------------------------
+// Configuration II Register (VRC4171_Config2) Bit Definitions
+//------------------------------------------------------------
+#define SIL_REV_MASK         0xf000
+#define  REV_VRC4171A        0x2000
+#define  REV_VRC4171         0x1000
+#define MCLK_EN              0x0400
+#define READ_HOLD_DELAY_NONE 0x0000
+#define READ_HOLD_DELAY_7    0x0004
+#define READ_HOLD_DELAY_X1   0x0008
+#define READ_HOLD_DELAY_14   0x000c
+#define IOCH_R1              0x0002
+
+
+
+//--------------------------------------------------------//
+// Register Index Values
+//--------------------------------------------------------//
+typedef enum {
+    IndexChipRevision = 0,         // 0x00
+    IndexInterfaceStatus,          // 0x01
+    IndexPowerControl,             // 0x02
+    IndexIntrAndGeneralControl,    // 0x03
+    IndexCardStatusChange,         // 0x04
+    IndexCardStatusIntrConfig,     // 0x05
+    IndexMappingEnable,            // 0x06
+    IndexIoWindowControl,          // 0x07
+    IndexIomap0StartAddrLow,       // 0x08
+    IndexIomap0StartAddrHi,        // 0x09
+    IndexIomap0EndAddrLow,         // 0x0a
+    IndexIomap0EndAddrHi,          // 0x0b
+    IndexIomap1StartAddrLow,       // 0x0c
+    IndexIomap1StartAddrHi,        // 0x0d
+    IndexIomap1EndAddrLow,         // 0x0e
+    IndexIomap1EndAddrHi,          // 0x0f
+    IndexMemmap0StartAddrLow,      // 0x10
+    IndexMemmap0StartAddrHi,       // 0x11
+    IndexMemmap0EndAddrLow,        // 0x12
+    IndexMemmap0EndAddrHi,         // 0x13
+    IndexMemmap0AddrOffsetLow,     // 0x14
+    IndexMemmap0AddrOffsetHi,      // 0x15
+    IndexMiscControl,              // 0x16
+    IndexFifoControl,              // 0x17
+    IndexMemmap1StartAddrLow,      // 0x18
+    IndexMemmap1StartAddrHi,       // 0x19
+    IndexMemmap1EndAddrLow,        // 0x1a
+    IndexMemmap1EndAddrHi,         // 0x1b
+    IndexMemmap1AddrOffsetLow,     // 0x1c
+    IndexMemmap1AddrOffsetHi,      // 0x1d
+    IndexGlobalControl,            // 0x1e
+    IndexVoltageSense,             // 0x1f
+    IndexMemmap2StartAddrLow,      // 0x20
+    IndexMemmap2StartAddrHi,       // 0x21
+    IndexMemmap2EndAddrLow,        // 0x22
+    IndexMemmap2EndAddrHi,         // 0x23
+    IndexMemmap2AddrOffsetLow,     // 0x24
+    IndexMemmap2AddrOffsetHi,      // 0x25
+    IndexAtaControl,               // 0x26
+    IndexReserved0,                // 0x27
+    IndexMemmap3StartAddrLow,      // 0x28
+    IndexMemmap3StartAddrHi,       // 0x29
+    IndexMemmap3EndAddrLow,        // 0x2a
+    IndexMemmap3EndAddrHi,         // 0x2b
+    IndexMemmap3AddrOffsetLow,     // 0x2c
+    IndexMemmap3AddrOffsetHi,      // 0x2d
+    IndexReserved1,                // 0x2e
+    IndexVoltageSelect,            // 0x2f
+    IndexMemmap4StartAddrLow,      // 0x30
+    IndexMemmap4StartAddrHi,       // 0x31
+    IndexMemmap4EndAddrLow,        // 0x32
+    IndexMemmap4EndAddrHi,         // 0x33
+    IndexMemmap4AddrOffsetLow,     // 0x34
+    IndexMemmap4AddrOffsetHi,      // 0x35
+    IndexIomap0AddrOffsetLow,      // 0x36
+    IndexIomap0AddrOffsetHi,       // 0x37
+    IndexIomap1AddrOffsetLow,      // 0x38
+    IndexIomap1AddrOffsetHi,       // 0x39
+    IndexSetupTiming0,             // 0x3a
+    IndexCommandTiming0,           // 0x3b
+    IndexRecoveryTiming0,          // 0x3c
+    IndexSetupTiming1,             // 0x3d
+    IndexCommandTiming1,           // 0x3e
+    IndexRecoveryTiming1           // 0x3f
+} vrc4171pcm_index_t;
+
+
+// To access Slot B PCIC data registers, add the following
+// to the index values above.
+#define SLOT_B_INDEX_OFFSET           0x40
+
+//--------------------------------------------------------//
+// SOCKET                                                 //
+// Data Register                                          //
+
+//--------------------------------------------------------//
+// REGISTER INDEX No.00 Bit Definitions
+//--------------------------------------------------------//
+#define SLOT_REV_MASK     0x0f
+#define IF_TYPE_MASK      0xc0
+#define   IF_TYPE_IO_MEM  0x80
+
+//--------------------------------------------------------//
+// REGISTER INDEX No.01 Bit Definitions
+//--------------------------------------------------------//
+#define CARD_POWER_ON                          (1<<6)
+#define READY_BUSY                             (1<<5)
+#define WRITE_PROTECT                          (1<<4)
+#define CARD_DETECT_CD2                        (1<<3)
+#define CARD_DETECT_CD1                        (1<<2)
+#define BATTERY_VOLTAGE_DETECT_BVD2            (1<<1)
+#define BATTERY_VOLTAGE_DETECT_BVD1            (1<<0)
+
+//--------------------------------------------------------//
+// REGISTER INDEX No.02 Bit Definitions
+//--------------------------------------------------------//
+#define OUTPUT_ENABLE                                0x80
+#define POWER_ENABLE                                 0x10
+#define VPP_SELECT_MASK                              0x03
+
+//--------------------------------------------------------//
+// REGISTER INDEX No.03 Bit Definitions
+//--------------------------------------------------------//
+
+#define RING_INDICATE_ENABLE                         0x80 // 
+#define CARD_RESET                                   0x40 // 
+#define CARD_IS_IO                                   0x20 // 
+#define ENABLE_MANAGE_INT                            0x10 // 
+#define IO_IRQ_BIT_OFFSET                            0
+
+//--------------------------------------------------------//
+// REGISTER INDEX No.04 Bit Definitions
+//--------------------------------------------------------//
+#define DETECT_CHANGE                                0x08 // 
+#define READY_CHANGE                                 0x04 // 
+#define BATTERY_WARNING                              0x02 // 
+#define BATTERY_DEAD_OR_STS_CHG                      0x01 // 
+
+//--------------------------------------------------------//
+// REGISTER INDEX No.05 Bit Definitions
+//--------------------------------------------------------//
+
+#define CSC_IRQ_BIT_OFFSET                           4
+#define CARD_DETECT_ENABLE                           0x08 // 
+#define READY_ENABLE                                 0x04 // 
+#define BATTERY_WARNING_ENABLE                       0x02 // 
+#define BATTERY_DEAD_STSCHG_ENABLE                   0x01 // 
+
+//--------------------------------------------------------//
+// REGISTER INDEX No.06 Bit Definitions
+//--------------------------------------------------------//
+
+#define IOMAP1_ENABLE                                0x80 // 
+#define IOMAP0_ENABLE                                0x40 // 
+#define MEMCS16_DECODE                               0x20 // 
+#define MEMMAP4_ENABLE                               0x10 // 
+#define MEMMAP3_ENABLE                               0x08 // 
+#define MEMMAP2_ENABLE                               0x04 // 
+#define MEMMAP1_ENABLE                               0x02 // 
+#define MEMMAP0_ENABLE                               0x01 // 
+
+//--------------------------------------------------------//
+// REGISTER INDEX No.07 Bit Definitions
+//--------------------------------------------------------//
+
+#define TIMING_REGISTER_SELECT1                      0x80 // 
+//                                                   0x40 // 
+#define AUTO_SIZE_IO_WINDOW1                         0x20 // 
+#define IO_WINDOW1_SIZE                              0x10 // 
+#define TIMING_REGISTER_SELECT0                      0x08 // 
+//                                                   0x04 // 
+#define AUTO_SIZE_IO_WINDOW0                         0x02 // 
+#define IO_WINDOW0_SIZE                              0x01 // 
+
+#define IO_WINDOW0_WS                                0x04
+#define IO_WINDOW1_WS                                0x40
+
+//--------------------------------------------------------//
+// REGISTER INDEX No.08 ,0C Bit Definitions
+//                                                        //
+// I/O MAP0,1 START ADDRESS LOW : START ADDRESS Bit 7-0   //
+//--------------------------------------------------------//
+
+//--------------------------------------------------------//
+// REGISTER INDEX No.09 ,0D Bit Definitions
+//                                                        //
+// I/O MAP0,1 START ADDRESS HIGH : START ADDRESS Bit 15-8 //
+//--------------------------------------------------------//
+
+//--------------------------------------------------------//
+// REGISTER INDEX No.0A ,0E Bit Definitions
+//                                                        //
+// I/O MAP0,1 END ADDRESS LOW : END ADDRESS Bit 7-0       //
+//--------------------------------------------------------//
+
+//--------------------------------------------------------//
+// REGISTER INDEX No.0B ,0F Bit Definitions
+//                                                        //
+// I/O MAP0,1 END ADDRESS HIGH : END ADDRESS Bit 15-8     //
+//--------------------------------------------------------//
+
+//--------------------------------------------------------//
+// REGISTER INDEX No.10,18,20,28,30 Bit Definitions
+//                                                        //
+// MEMORY MAP0,1,2,3,4 START ADDRESS LOW                  //
+//                               : START ADDRESS Bit 19-12//
+//--------------------------------------------------------//
+
+//--------------------------------------------------------//
+// REGISTER INDEX No.11,19,21,29,31 Bit Definitions
+//                                                        //
+// MEMORY MAP0,1,2,3,4 START ADDRESS HIGH                 //
+//                               : START ADDRESS Bit 23-20//
+//--------------------------------------------------------//
+
+#define WINDOW_DATA_SIZE                             0x80 // 
+
+//--------------------------------------------------------//
+// REGISTER INDEX No.12,1A,22,2A,32 Bit Definitions
+//                                                        //
+// MEMORY MAP0,1,2,3,4 END ADDRESS LOW                    //
+//                             : END ADDRESS Bit 19-12    //
+//--------------------------------------------------------//
+
+//--------------------------------------------------------//
+// REGISTER INDEX No.13,1B,23,2B,33 Bit Definitions
+//                                                        //
+// MEMORY MAP0,1,2,3,4 END ADDRESS HIGH                   //
+//                             : END ADDRESS Bit 23-20    //
+//--------------------------------------------------------//
+
+#define CARD_TIMER_SELECT_HI                         0x80 // 
+#define CARD_TIMER_SELECT_LOW                        0x40 // 
+
+//--------------------------------------------------------//
+// REGISTER INDEX No.14,1C,24,2C,34 Bit Definitions
+//                                                        //
+// MEMORY MAP0,1,2,3,4 ADDRESS OFFSET LOW                 //
+//                             : OFFSET ADDRESS Bit 19-12 //
+//--------------------------------------------------------//
+
+//--------------------------------------------------------//
+// REGISTER INDEX No.15,1D,25,2D,35 Bit Definitions
+//                                                        //
+// MEMORY MAP0,1,2,3,4 ADDRESS OFFSET HIGH                //
+//                             : OFFSET ADDRESS Bit 25-20 //
+//--------------------------------------------------------//
+
+#define WINDOW_WRITE_PROTECT                         0x80 // 
+#define REG_SETTING                                  0x40 // 
+
+//--------------------------------------------------------//
+// REGISTER INDEX No.16 Bit Definitions
+//--------------------------------------------------------//
+
+#define INPACK_ENABLE                                0x80 // 
+//                                                   0x40 // 
+//                                                   0x20 // 
+#define SPEAKER_ENABLE                               0x10 // 
+#define PULSE_SYSTEM_IRQ                             0x08 // 
+#define PLUSE_MANAGEMENT_INTERUPT                    0x04 // 
+#define VCC3_3                                       0x02 // 
+#define DETECT_5V                                    0x01 // 
+#define DLY16INH                                     0x01
+
+//--------------------------------------------------------//
+// REGISTER INDEX No.17 Bit Definitions
+//--------------------------------------------------------//
+
+#define EMPTY_WRITE_FIFO                             0x80 // 
+//                                                   0x40 // 
+//                                                   0x20 // 
+//                                                   0x10 // 
+//                                                   0x08 // 
+//                                                   0x04 // 
+//                                                   0x02 // 
+//                                                   0x01 // 
+
+//--------------------------------------------------------//
+// REGISTER INDEX No.1E Bit Definitions
+//--------------------------------------------------------//
+#define CLRPMIRQ                  0x10
+#define IRQPM_EN                  0x08
+#define EXWRBK                    0x04
+
+//--------------------------------------------------------//
+// REGISTER INDEX No.1F Bit Definitions
+//--------------------------------------------------------//
+
+#define CHIP_IDENTIFICATION_HI                       0x80 // 
+#define CHIP_IDENTIFICATION_LOW                      0x40 // 
+#define DUAL_SIGLE_SLOT                              0x20 // 
+#define CL_PD67_REV_LEVEL_BIT2                       0x10 // 
+#define CL_PD67_REV_LEVEL_BIT1                       0x08 // 
+#define CL_PD67_REV_LEVEL_BIT0                       0x04 // 
+#define VS2                                          0x02
+#define VS1                                          0x01
+#define VOLTAGE_SENSE_B_SHIFT                        2
+
+//--------------------------------------------------------//
+// REGISTER INDEX No.26 Bit Definitions
+//--------------------------------------------------------//
+
+#define A25_CSEL                                     0x80 // 
+#define A24_M_S                                      0x40 // 
+#define A23_VU                                       0x20 // 
+#define A22                                          0x10 // 
+#define A21                                          0x08 // 
+//                                                   0x04 // 
+#define SPEAKER_IS_LED_INPUT                         0x02 // 
+#define ATA_MORD                                     0x01 // 
+
+//--------------------------------------------------------//
+// REGISTER INDEX No.2F Bit Definitions
+//--------------------------------------------------------//
+#define VCC_SELECT_MASK              0x03
+
+//
+// Mode Control Register 2
+//
+#define DIRECT_VOLTAGE_SWITCH_ENABLE       (1<<3)
+#define INPUT_ACKNOWLIEDGE_ENABLE          (1<<2)
+#define IREQ_SENSE_SELECTION               (1<<1)
+#define VOLTAGE_SELECTION                  (1<<0)
+#define VSELECT2                           (1<<1)
+#define VSELECT1                           (1<<0)
+#define VOLTAGE_LIMIT_SHIFT                2
+#define VOLTAGE_SELECT_MASK                0x3
+
+//--------------------------------------------------------//
+// REGISTER INDEX No.3c Bit Definitions
+//--------------------------------------------------------//
+#define INTERNAL_VOLTAGE_SENSE     0x4
+
+//--------------------------------------------------------//
+// REGISTER INDEX No.3b & 7b Bit Definitions
+//--------------------------------------------------------//
+#define GP_OUTPUT                  0x30
+
+
+#endif // __ASM_MIPS_VRC4171_H_
diff -ruN linux-mips/include/asm-mips/vrc4173.h linux-vr/include/asm-mips/vrc4173.h
--- linux-mips/include/asm-mips/vrc4173.h	Wed Dec 31 16:00:00 1969
+++ linux-vr/include/asm-mips/vrc4173.h	Wed Nov 15 12:09:44 2000
@@ -0,0 +1,214 @@
+/* $Id: vrc4173.h,v 1.1 2000/11/15 20:09:44 mikemac Exp $
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000 by Michael R. McDonald
+ */
+#ifndef __ASM_MIPS_VRC4173_H 
+#define __ASM_MIPS_VRC4173_H 
+
+#include <asm/addrspace.h>
+
+#define VRC4173_IO_EXTENT	4096
+#define VRC4173_SYSINT_MASK	0x0179	/* No doze, AC97, PCMCIA, nor KIU */
+#define VRC4173_SELECTREG_MASK	0x7	/* Enable touch panel, PS2 1&2, and GPIO[0-15] */
+
+/* VRC4173 subfunction devices */
+#define USB_DEV		0
+#define PCMCIA2_DEV	1
+#define PCMCIA1_DEV	2
+#define PS2AUX_DEV	3
+#define PS2KBD_DEV	4
+#define PIU_DEV		5
+#define AIU_DEV		6
+#define KIU_DEV		7
+#define GIU_DEV		8
+#define AC97_DEV	9
+
+/* DMA Address Unit (DMAAU) */
+#define VRC4173_AIUIBALREG	0x000	/* AIU IN DMA Base Address Register Low (R/W) */
+#define VRC4173_AIUIBAHREG	0x002	/* AIU IN DMA Base Address Register High (R/W) */
+#define VRC4173_AIUIALREG	0x004	/* AIU IN DMA Address Register Low (R/W) */
+#define VRC4173_AIUIAHREG	0x006	/* AIU IN DMA Address Register High (R/W) */
+#define VRC4173_AIUOBALREG	0x008	/* AIU OUT DMA Base Address Register Low (R/W) */
+#define VRC4173_AIUOBAHREG	0x00A	/* AIU OUT DMA Base Address Register High (R/W) */
+#define VRC4173_AIUOALREG	0x00C	/* AIU OUT DMA Address Register Low (R/W) */
+#define VRC4173_AIUOAHREG	0x00E	/* AIU OUT DMA Address Register High (R/W) */
+#define VRC4173_FIRBALREG	0x010	/* FIR DMA Base Address Register Low (R/W) */
+#define VRC4173_FIRBAHREG	0x012	/* FIR DMA Base Address Register High (R/W) */
+#define VRC4173_FIRALREG	0x014	/* FIR DMA Address Register Low (R/W) */
+#define VRC4173_FIRAHREG	0x016	/* FIR DMA Address Register High (R/W) */
+
+/* DMA Control Unit (DCU) */
+#define VRC4173_DMARSTREG	0x020	/* DMA Reset Register */
+#define VRC4173_DMAIDLEREG	0x022	/* DMA Sequencer Status Register */
+#define VRC4173_DMASENREG	0x024	/* DMA Sequencer Enable Register */
+#define VRC4173_DMAMSKREG	0x026	/* DMA Mask Register */
+#define VRC4173_DMAREQREG	0x028	/* DMA Request Register */
+
+/* Clock Mask Unit (CMU) */
+#define VRC4173_CMUCLKMSK	0x040	/* 4173 CMU Clock Mask Register */
+#define VRC4173_CMUSRST		0x042	/* 4173 CMU Soft Reset Register */
+
+/* Interrupt Control Unit (ICU) */
+#define VRC4173_SYSINT1REG	0x060	/* Level 1 System interrupt register 1 */
+#define VRC4173_PIUINTREG_RO	0x062	/* Level 2 PIU interrupt register */
+#define VRC4173_AIUINTREG	0x064	/* Level 2 AIU interrupt register */
+#define VRC4173_KIUINTREG	0x066	/* Level 2 KIU interrupt register */
+#define VRC4173_GIULINTREG	0x068	/* Level 2 GIU interrupt register Low */
+#define VRC4173_GIUHINTREG	0x06A	/* Level 2 GIU interrupt register High */
+#define VRC4173_MSYSINT1REG	0x06C	/* Level 1 mask system interrupt register 1 */
+#define VRC4173_MPIUINTREG	0x06E	/* Level 2 mask PIU interrupt register */
+#define VRC4173_MAIUINTREG	0x070	/* Level 2 mask AIU interrupt register */
+#define VRC4173_MKIUINTREG	0x072	/* Level 2 mask KIU interrupt register */
+#define VRC4173_MGIULINTREG	0x074	/* Level 2 mask GIU interrupt register Low */
+#define VRC4173_MGIUHINTREG	0x076	/* Level 2 mask GIU interrupt register High */
+
+/* General Purpose I/O Unit (GIU) */
+#define VRC4173_GIUDIRL		0x080	/* GPIO Input/Output Select Register L */
+#define VRC4173_GIUDIRH		0x082	/* GPIO Input/Output Select Register H */
+#define VRC4173_GIUPIODL	0x084	/* GPIO Port Input/Output Data Register L */
+#define VRC4173_GIUPIODH	0x086	/* GPIO Port Input/Output Data Register H */
+#define VRC4173_GIUINTSTATL	0x088	/* GPIO Interrupt Status Register L */
+#define VRC4173_GIUINTSTATH	0x08A	/* GPIO Interrupt Status Register H */
+#define VRC4173_GIUINTENL	0x08C	/* GPIO Interrupt Enable Register L */
+#define VRC4173_GIUINTENH	0x08E	/* GPIO Interrupt Enable Register H */
+#define VRC4173_GIUINTTYPL	0x090	/* GPIO Interrupt Type (Edge/Level) Select Register */
+#define VRC4173_GIUINTTYPH	0x092	/* GPIO Interrupt Type (Edge/Level) Select Register */
+#define VRC4173_GIUINTALSELL	0x094	/* GPIO Interrupt Active Level Select Register L */
+#define VRC4173_GIUINTALSELH	0x096	/* GPIO Interrupt Active Level Select Register H */
+#define VRC4173_GIUINTHTSELL	0x098	/* GPIO Interrupt Hold/Through Select Register L */
+#define VRC4173_GIUINTHTSELH	0x09A	/* GPIO Interrupt Hold/Through Select Register H */
+#define VRC4173_SELECTREG	0x09E	/* GPIO Port Output Data Enable Register */
+
+#define VRC4173_SELECT_GPIO_L	1
+#define VRC4173_SELECT_PS2_2	2
+#define VRC4173_SELECT_PS2_1	4
+#define VRC4173_SELECT_GPIO_H	8
+
+#define VRC4173_GIUPIODH_GPIO20		0x0010
+#define VRC4173_GIUPIODH_GPIO19		0x0008
+#define VRC4173_GIUPIODH_GPIO18		0x0004
+#define VRC4173_GIUPIODH_GPIO17		0x0002
+#define VRC4173_GIUPIODH_GPIO16		0x0001
+#define VRC4173_GIUPIODL_GPIO15		0x8000
+#define VRC4173_GIUPIODL_GPIO14		0x4000
+#define VRC4173_GIUPIODL_GPIO13		0x2000
+#define VRC4173_GIUPIODL_GPIO12		0x1000
+#define VRC4173_GIUPIODL_GPIO11		0x0800
+#define VRC4173_GIUPIODL_GPIO10		0x0400
+#define VRC4173_GIUPIODL_GPIO9		0x0200
+#define VRC4173_GIUPIODL_GPIO8		0x0100
+#define VRC4173_GIUPIODL_GPIO7		0x0080
+#define VRC4173_GIUPIODL_GPIO6		0x0040
+#define VRC4173_GIUPIODL_GPIO5		0x0020
+#define VRC4173_GIUPIODL_GPIO4		0x0010
+#define VRC4173_GIUPIODL_GPIO3		0x0008
+#define VRC4173_GIUPIODL_GPIO2		0x0004
+#define VRC4173_GIUPIODL_GPIO1		0x0002
+#define VRC4173_GIUPIODL_GPIO0		0x0001
+
+/* Touch Panel Interface Unit (PIU) */
+#define VRC4173_PIUCNTREG	0x0A2	/* PIU Control register (R/W) */
+#define VRC4173_PIUCNTREG_PIUSEQEN	0x0004
+#define VRC4173_PIUCNTREG_PIUPWR	0x0002
+#define VRC4173_PIUCNTREG_PADRST	0x0001
+#define VRC4173_PIUCNTREG_STATE_DISABLE		0
+#define VRC4173_PIUCNTREG_STATE_STANDBY		1
+#define VRC4173_PIUCNTREG_STATE_PORTSCAN	2
+#define VRC4173_PIUCNTREG_STATE_WAITPEN		4
+#define VRC4173_PIUCNTREG_STATE_PENSCAN		5
+#define VRC4173_PIUCNTREG_STATE_NEXTSCAN	6
+#define VRC4173_PIUCNTREG_STATE_CMDSCAN		7
+
+#define VRC4173_PIUINTREG		0x0A4	/* PIU Interrupt cause register (R/W) */
+#define VRC4173_PIUINTREG_OVP		0x8000
+#define VRC4173_PIUINTREG_PADCMD	0x0040
+#define VRC4173_PIUINTREG_PADADP	0x0020
+#define VRC4173_PIUINTREG_PADPAGE1	0x0010
+#define VRC4173_PIUINTREG_PADPAGE0	0x0008
+#define VRC4173_PIUINTREG_PADDLOST	0x0004
+#define VRC4173_PIUINTREG_PENCHG	0x0001
+
+#define VRC4173_PIUSIVLREG	0x0A6	/* PIU Data sampling interval register (R/W) */
+#define VRC4173_PIUSTBLREG	0x0A8	/* PIU A/D converter start delay register (R/W) */
+#define VRC4173_PIUCMDREG	0x0AA	/* PIU A/D command register (R/W) */
+#define VRC4173_PIUASCNREG	0x0B0	/* PIU A/D port scan register (R/W) */
+#define VRC4173_PIUAMSKREG	0x0B2	/* PIU A/D scan mask register (R/W) */
+#define VRC4173_PIUCIVLREG	0x0BE	/* PIU Check interval register (R) */
+#define VRC4173_PIUPB00REG	0x0C0	/* PIU Page 0 Buffer 0 register (R/W) */
+#define VRC4173_PIUPB01REG	0x0C2	/* PIU Page 0 Buffer 1 register (R/W) */
+#define VRC4173_PIUPB02REG	0x0C4	/* PIU Page 0 Buffer 2 register (R/W) */
+#define VRC4173_PIUPB03REG	0x0C6	/* PIU Page 0 Buffer 3 register (R/W) */
+#define VRC4173_PIUPB10REG	0x0C8	/* PIU Page 1 Buffer 0 register (R/W) */
+#define VRC4173_PIUPB11REG	0x0CA	/* PIU Page 1 Buffer 1 register (R/W) */
+#define VRC4173_PIUPB12REG	0x0CC	/* PIU Page 1 Buffer 2 register (R/W) */
+#define VRC4173_PIUPB13REG	0x0CE	/* PIU Page 1 Buffer 3 register (R/W) */
+#define VRC4173_PIUAB0REG	0x0D0	/* PIU A/D scan Buffer 0 register (R/W) */
+#define VRC4173_PIUAB1REG	0x0D2	/* PIU A/D scan Buffer 1 register (R/W) */
+#define VRC4173_PIUPB04REG	0x0DC	/* PIU Page 0 Buffer 4 register (R/W) */
+#define VRC4173_PIUPB14REG	0x0DE	/* PIU Page 1 Buffer 4 register (R/W) */
+
+/* Audio Interface Unit (AIU) */
+#define VRC4173_MDMADATREG	0x0E0	/* Mike DMA Data Register (R/W) */
+#define VRC4173_SDMADATREG	0x0E2	/* Speaker DMA Data Register (R/W) */
+#define VRC4173_SODATREG	0x0E6	/* Speaker Output Data Register (R/W) */
+#define VRC4173_SCNTREG		0x0E8	/* Speaker Output Control Register (R/W) */
+#define VRC4173_SCNVRREG	0x0EA	/* Speaker Conversion Rate Register (R/W) */
+#define VRC4173_MIDATREG	0x0F0	/* Mike Input Data Register (R/W) */
+#define VRC4173_MCNTREG		0x0F2	/* Mike Input Control Register (R/W) */
+#define VRC4173_MCNVRREG	0x0F4	/* Mike Conversion Rate Register (R/W) */
+#define VRC4173_DVALIDREG	0x0F8	/* Data Valid Register (R/W) */
+#define VRC4173_SEQREG		0x0FA	/* Sequential Register (R/W) */
+#define VRC4173_INTREG		0x0FC	/* Interrupt Register (R/W) */
+
+/* Keyboard Interface Unit (KIU) of the VRC4173 */
+#define VRC4173_KIUDAT0		0x100	/* KIU Data0 Register (R/W) */
+#define VRC4173_KIUDAT1		0x102	/* KIU Data1 Register (R/W) */
+#define VRC4173_KIUDAT2		0x104	/* KIU Data2 Register (R/W) */
+#define VRC4173_KIUDAT3		0x106	/* KIU Data3 Register (R/W) */
+#define VRC4173_KIUDAT4		0x108	/* KIU Data4 Register (R/W) */
+#define VRC4173_KIUDAT5		0x10A	/* KIU Data5 Register (R/W) */
+#define VRC4173_KIUSCANREP	0x110	/* KIU Scan/Repeat Register (R/W) */
+#define VRC4173_KIUSCANREP_KEYEN	0x8000
+#define VRC4173_KIUSCANREP_SCANSTP	0x0008
+#define VRC4173_KIUSCANREP_SCANSTART	0x0004
+#define VRC4173_KIUSCANREP_ATSTP	0x0002
+#define VRC4173_KIUSCANREP_ATSCAN	0x0001
+#define VRC4173_KIUSCANS	0x112	/* KIU Scan Status Register (R) */
+#define VRC4173_KIUWKS		0x114	/* KIU Wait Keyscan Stable Register (R/W) */
+#define VRC4173_KIUWKI		0x116	/* KIU Wait Keyscan Interval Register (R/W) */
+#define VRC4173_KIUINT		0x118	/* KIU Interrupt Register (R/W) */
+#define VRC4173_KIUINT_KDATLOST		0x0004
+#define VRC4173_KIUINT_KDATRDY		0x0002
+#define VRC4173_KIUINT_SCANINT		0x0001
+#define VRC4173_KIURST		0x11A	/* KIU Reset Register (W) */
+#define VRC4173_KIUGPEN		0x11C	/* KIU General Purpose Output Enable (R/W) */
+#define VRC4173_SCANLINE	0x11E	/* KIU Scan Line Register (R/W) */
+
+// PS2 Interface Unit (PSIU) of the VRC4173
+#define VRC4173_PS2CH1DATA	0x120	/* PS2 Channel 1 Data Register (R/W) */
+#define VRC4173_PS2CH1CTRL	0x122	/* PS2 Channel 1 Control Register (R/W) */
+#define VRC4173_PS2CH1RST	0x124	/* PS2 Channel 1 Reset Register (R/W) */
+
+#define VRC4173_PS2CH2DATA	0x140	/* PS2 Channel 2 Data Register (R/W) */
+#define VRC4173_PS2CH2CTRL	0x142	/* PS2 Channel 2 Control Register (R/W) */
+#define VRC4173_PS2CH2RST	0x144	/* PS2 Channel 2 Reset Register (R/W) */
+
+/* AC97 Unit (AC97U) */
+#define VRC4173_AC97_INT_STATUS		0x000	/* Interrupt Clear/Status Register */
+#define VRC4173_AC97_CODEC_WR		0x004	/* Codec Write Register */
+#define VRC4173_AC97_CODEC_RD		0x008	/* Codec Read Register */
+#define VRC4173_AC97_ACLINK_CTRL	0x01C	/* ACLINK Control Register */
+
+#define VRC4173_AC97_CODEC_WR_RWC	(1<<23)	/* sets read/write command */
+#define VRC4173_AC97_CODEC_WR_WRDY	(1<<31)	/* write ready */
+
+#define VRC4173_AC97_CODEC_RD_RDRDY	(1<<30)	/* Read Data Ready */
+#define VRC4173_AC97_CODEC_RD_DMASK	0xffff	/* Read Data Mask */
+
+#define VRC4173_AC97_ACLINK_CTRL_SYNC_ON	(1<<30)	/* Codec sync bit */
+
+#endif /* __ASM_MIPS_VRC4173_H */
diff -ruN linux-mips/include/linux/buttons.h linux-vr/include/linux/buttons.h
--- linux-mips/include/linux/buttons.h	Wed Dec 31 16:00:00 1969
+++ linux-vr/include/linux/buttons.h	Thu Nov 23 11:57:44 2000
@@ -0,0 +1,89 @@
+/* $Id: buttons.h,v 1.3 2000/11/15 20:03:07 mikemac Exp $
+ *
+ * Data defines for button input
+ *
+ * This was created for the NEC VR41xx GPIO button driver, but should be
+ * general enough that it applies to other platforms as well.
+ *
+ * Copyright (c) 2000 Michael Klar <wyldfier@iname.com>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef _LINUX_BUTTONS_H
+#define _LINUX_BUTTONS_H
+
+
+#define BTN_PRESS	0x8000
+#define BTN_RELEASE	0
+
+#define BTN_STATE_MASK	0x8000
+#define BTN_DATA_MASK	0x0fff
+
+/*
+ * The button definitions:
+ *
+ * Feel free to add more.  With 4096 potential vlaues, we're not going to
+ * run out any time soon.  Note that the application types listed for the
+ * BTN_AP buttons are only suggestions for which AP buttons to assign to
+ * which physical button based on button icon, and may not be applicable
+ * to platforms that are not productivity-oriented.
+ */
+
+#define BTN_POWER		0
+#define BTN_ACTION		1
+#define BTN_EXIT		2
+#define BTN_UP			3
+#define BTN_DOWN		4
+#define BTN_CONTRAST		5
+#define BTN_BACKLIGHT		6
+#define BTN_NORTH		7
+#define BTN_SOUTH		8
+#define BTN_EAST		9
+#define BTN_WEST		10
+#define BTN_NOTIFICATION	11
+#define BTN_SYNC		12
+
+#define BTN_AP1			256	// Task list
+#define BTN_AP2			257	// Address book
+#define BTN_AP3			258	// Notepad
+#define BTN_AP4			259	// Calendar
+#define BTN_AP5			260	// Voice recorder
+#define BTN_AP6			261
+#define BTN_AP7			262
+#define BTN_AP8			263
+#define BTN_AP9			264
+#define BTN_AP10		265
+#define BTN_AP11		266
+#define BTN_AP12		267
+#define BTN_AP13		268
+#define BTN_AP14		269
+#define BTN_AP15		270
+#define BTN_AP16		271
+
+#define BTN_AP17		272
+#define BTN_AP18		273
+#define BTN_AP19		274
+#define BTN_AP20		275
+#define BTN_AP21		276
+#define BTN_AP22		277
+#define BTN_AP23		278
+#define BTN_AP24		279
+#define BTN_AP25		280
+#define BTN_AP26		281
+#define BTN_AP27		282
+#define BTN_AP28		283
+#define BTN_AP29		284
+#define BTN_AP30		285
+#define BTN_AP31		286
+#define BTN_AP32		287
+
+#define BTN_AP33		288
+#define BTN_AP34		289
+#define BTN_AP35		290
+#define BTN_AP36		291
+#define BTN_AP37		292
+
+#endif /* _LINUX_BUTTONS_H */
diff -ruN linux-mips/include/linux/fb.h linux-vr/include/linux/fb.h
--- linux-mips/include/linux/fb.h	Mon Sep 11 23:53:49 2000
+++ linux-vr/include/linux/fb.h	Thu Nov 23 15:05:26 2000
@@ -30,6 +30,19 @@
 #define FBIOGET_GLYPH           0x4615
 #define FBIOGET_HWCINFO         0x4616
 
+/* For Linux VR */
+#define FBIOGET_BACKLIGHT       0x4620
+#define FBIOPUT_BACKLIGHT       0x4621
+#define FBIOGET_CONTRAST        0x4622
+#define FBIOPUT_CONTRAST        0x4623
+#define FBIO_POWER              0x4624
+
+int display_get_backlight(void);
+int display_set_backlight(int n);
+int display_get_contrast(void);
+int display_set_contrast(int n);
+int display_power(int n);
+
 #define FB_TYPE_PACKED_PIXELS		0	/* Packed Pixels	*/
 #define FB_TYPE_PLANES			1	/* Non interleaved planes */
 #define FB_TYPE_INTERLEAVED_PLANES	2	/* Interleaved planes	*/
diff -ruN linux-mips/include/linux/if.h linux-vr/include/linux/if.h
--- linux-mips/include/linux/if.h	Sun Feb 20 13:53:54 2000
+++ linux-vr/include/linux/if.h	Sat Jul 15 08:17:02 2000
@@ -59,7 +59,7 @@
 {
 	unsigned long mem_start;
 	unsigned long mem_end;
-	unsigned short base_addr; 
+	unsigned long base_addr; 
 	unsigned char irq;
 	unsigned char dma;
 	unsigned char port;
diff -ruN linux-mips/include/linux/linkage.h linux-vr/include/linux/linkage.h
--- linux-mips/include/linux/linkage.h	Sat Jun 24 22:46:58 2000
+++ linux-vr/include/linux/linkage.h	Sat Jul  1 11:32:42 2000
@@ -1,7 +1,11 @@
 #ifndef _LINUX_LINKAGE_H
 #define _LINUX_LINKAGE_H
 
+#ifdef __KERNEL__
+// Only use config.h if compiling kernel.
+// Others will have to #define CONFIG_X86_ALIGNMENT_16 if necessary.  bdl
 #include <linux/config.h>
+#endif
 
 #ifdef __cplusplus
 #define CPP_ASMLINKAGE extern "C"
diff -ruN linux-mips/include/linux/miscdevice.h linux-vr/include/linux/miscdevice.h
--- linux-mips/include/linux/miscdevice.h	Fri Nov 10 00:17:06 2000
+++ linux-vr/include/linux/miscdevice.h	Thu Nov 23 15:04:40 2000
@@ -13,6 +13,8 @@
 #define APOLLO_MOUSE_MINOR 7
 #define PC110PAD_MINOR 9
 #define ADB_MOUSE_MINOR 10
+#define VR41XX_TPANEL_MINOR 11
+#define R39XX_TPANEL_MINOR 12     /* FIXME: Not OK'd with hpa yet */
 #define WATCHDOG_MINOR		130	/* Watchdog timer     */
 #define TEMP_MINOR		131	/* Temperature Sensor */
 #define RTC_MINOR 135
@@ -20,6 +22,7 @@
 #define SUN_OPENPROM_MINOR 139
 #define NVRAM_MINOR 144
 #define I2O_MINOR 166
+#define VR41XX_BUTTONS_MINOR 180
 #define MICROCODE_MINOR		184
 #define MISC_DYNAMIC_MINOR 255
 
diff -ruN linux-mips/include/linux/pci_ids.h linux-vr/include/linux/pci_ids.h
--- linux-mips/include/linux/pci_ids.h	Fri Nov 10 00:17:29 2000
+++ linux-vr/include/linux/pci_ids.h	Thu Nov 23 11:57:44 2000
@@ -316,9 +316,14 @@
 #define PCI_DEVICE_ID_MIRO_36050	0x5601
 
 #define PCI_VENDOR_ID_NEC		0x1033
+#define PCI_DEVICE_ID_NEC_VRC4173_USB   0x0035
+#define PCI_DEVICE_ID_NEC_NAPCCARD	0x003e
 #define PCI_DEVICE_ID_NEC_PCX2		0x0046
 #define PCI_DEVICE_ID_NEC_NILE4		0x005a
 #define PCI_DEVICE_ID_NEC_VRC5476       0x009b
+#define PCI_DEVICE_ID_NEC_VRC4173	0x00a5
+#define PCI_DEVICE_ID_NEC_VRC4173_AC97  0x00a6
+#define PCI_DEVICE_ID_NEC_VR4122	0x00be
 
 #define PCI_VENDOR_ID_FD		0x1036
 #define PCI_DEVICE_ID_FD_36C70		0x0000
@@ -1140,6 +1145,9 @@
 
 #define PCI_VENDOR_ID_NETVIN		0x4a14
 #define PCI_DEVICE_ID_NETVIN_NV5000SC	0x5000
+
+#define PCI_VENDOR_ID_MEDIAQ		0x4d51
+#define PCI_DEVICE_ID_MEDIAQ_MQ200	0x0200
 
 #define PCI_VENDOR_ID_S3		0x5333
 #define PCI_DEVICE_ID_S3_PLATO_PXS	0x0551
diff -ruN linux-mips/include/linux/sched.h linux-vr/include/linux/sched.h
--- linux-mips/include/linux/sched.h	Fri Nov 10 00:17:40 2000
+++ linux-vr/include/linux/sched.h	Thu Nov 23 15:03:49 2000
@@ -552,7 +552,9 @@
 extern int in_group_p(gid_t);
 extern int in_egroup_p(gid_t);
 
+#if 0 // removed for VR41xx PCMCIA support
 extern void release(struct task_struct * p);
+#endif
 
 extern void proc_caches_init(void);
 extern void flush_signals(struct task_struct *);
diff -ruN linux-mips/include/linux/serial.h linux-vr/include/linux/serial.h
--- linux-mips/include/linux/serial.h	Mon Sep 11 23:54:01 2000
+++ linux-vr/include/linux/serial.h	Wed Sep 13 08:16:40 2000
@@ -81,6 +81,7 @@
 #define SERIAL_IO_HUB6	1
 #define SERIAL_IO_MEM	2
 #define SERIAL_IO_GSC	3
+#define SERIAL_VADDR	4
 
 struct serial_uart_config {
 	char	*name;
diff -ruN linux-mips/include/linux/tpanel.h linux-vr/include/linux/tpanel.h
--- linux-mips/include/linux/tpanel.h	Wed Dec 31 16:00:00 1969
+++ linux-vr/include/linux/tpanel.h	Mon Dec 27 12:12:30 1999
@@ -0,0 +1,31 @@
+/* $Id: tpanel.h,v 1.3 1999/12/27 20:12:30 brad Exp $
+ *
+ * Touch Panel Data Structures
+ * by Michael Klar, wyldfier@iname.com
+ *
+ * Created for the touch panel interface built into the NEC VR41xx family of
+ * CPUs, but should be applicable to other touch panel hardware
+ */
+
+#ifndef _LINUX_TPANEL_H
+#define _LINUX_TPANEL_H
+
+#include <linux/ioctl.h>
+
+/*
+ * The scan interval and settling time can be set via IOCTL, but the defualt
+ * of .01 sec and 480us should suffice for most applications.  The argument to
+ * these IOCTL calls is a struct of the values in microseconds, but note that
+ * the hardware may have a less precise interval.  If so, the value will be
+ * rounded and the actual value returned back.
+ */
+
+struct scanparam {
+	unsigned int	interval;
+	unsigned int	settletime;
+};
+
+#define TPGETSCANPARM _IOR( 0xB0, 0x00, struct scanparam )
+#define TPSETSCANPARM _IOW( 0xB0, 0x01, struct scanparam )
+
+#endif /* _LINUX_TPANEL_H */