From 26b4c8f71f91d22e081b27814782686edde0c90a Mon Sep 17 00:00:00 2001 From: Antoine Brodin Date: Fri, 1 Jan 2021 10:11:34 +0000 Subject: Revert r559792 to unbreak INDEX and bulk -a It seems a lot of reverse dependencies were missed With hat: portmgr --- www/node10/files/patch-deps_v8_src_arm_cpu-arm.cc | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 www/node10/files/patch-deps_v8_src_arm_cpu-arm.cc (limited to 'www/node10/files/patch-deps_v8_src_arm_cpu-arm.cc') diff --git a/www/node10/files/patch-deps_v8_src_arm_cpu-arm.cc b/www/node10/files/patch-deps_v8_src_arm_cpu-arm.cc new file mode 100644 index 000000000000..ceafdbfaa376 --- /dev/null +++ b/www/node10/files/patch-deps_v8_src_arm_cpu-arm.cc @@ -0,0 +1,22 @@ +--- deps/v8/src/arm/cpu-arm.cc.orig 2018-08-15 13:53:24 UTC ++++ deps/v8/src/arm/cpu-arm.cc +@@ -7,6 +7,9 @@ + #ifdef __QNXNTO__ + #include // for cache flushing. + #undef MAP_TYPE ++#elif defined(__FreeBSD__) ++#include ++#include // for cache flushing. + #else + #include // for cache flushing. + #endif +@@ -24,6 +27,9 @@ void CpuFeatures::FlushICache(void* star + #if !defined(USE_SIMULATOR) + #if V8_OS_QNX + msync(start, size, MS_SYNC | MS_INVALIDATE_ICACHE); ++#elif defined(__FreeBSD__) ++ struct arm_sync_icache_args args = { .addr = (uintptr_t)start, .len = size }; ++ sysarch(ARM_SYNC_ICACHE, (void *)&args); + #else + register uint32_t beg asm("r0") = reinterpret_cast(start); + register uint32_t end asm("r1") = beg + size; -- cgit v1.2.3