From 26b4c8f71f91d22e081b27814782686edde0c90a Mon Sep 17 00:00:00 2001 From: Antoine Brodin Date: Fri, 1 Jan 2021 10:11:34 +0000 Subject: Revert r559792 to unbreak INDEX and bulk -a It seems a lot of reverse dependencies were missed With hat: portmgr --- .../files/patch-third__party_zlib_arm__features.c | 97 ++++++++++++++++++++++ 1 file changed, 97 insertions(+) create mode 100644 devel/electron5/files/patch-third__party_zlib_arm__features.c (limited to 'devel/electron5/files/patch-third__party_zlib_arm__features.c') diff --git a/devel/electron5/files/patch-third__party_zlib_arm__features.c b/devel/electron5/files/patch-third__party_zlib_arm__features.c new file mode 100644 index 000000000000..3710c3fd1a5f --- /dev/null +++ b/devel/electron5/files/patch-third__party_zlib_arm__features.c @@ -0,0 +1,97 @@ +--- third_party/zlib/arm_features.c.orig 2019-04-20 12:09:23 UTC ++++ third_party/zlib/arm_features.c +@@ -8,83 +8,30 @@ + + #include "zutil.h" + +-int ZLIB_INTERNAL arm_cpu_enable_crc32 = 0; +-int ZLIB_INTERNAL arm_cpu_enable_pmull = 0; +- +-#if !defined(_MSC_VER) + #include + #include ++#include ++#include + +-#if defined(ARMV8_OS_ANDROID) +-#include +-#elif defined(ARMV8_OS_LINUX) +-#include +-#include +-#else +-#error ### No ARM CPU features detection in your platform/OS +-#endif ++int ZLIB_INTERNAL arm_cpu_enable_crc32 = 0; ++int ZLIB_INTERNAL arm_cpu_enable_pmull = 0; + + static pthread_once_t cpu_check_inited_once = PTHREAD_ONCE_INIT; + + static void init_arm_features(void) + { +- uint64_t flag_crc32 = 0, flag_pmull = 0, capabilities = 0; ++#if defined (__aarch64__) ++ uint64_t id_aa64isar0; + +-#if defined(ARMV8_OS_ANDROID) +- flag_crc32 = ANDROID_CPU_ARM_FEATURE_CRC32; +- flag_pmull = ANDROID_CPU_ARM_FEATURE_PMULL; +- capabilities = android_getCpuFeatures(); +-#elif defined(ARMV8_OS_LINUX) +- #if defined(__aarch64__) +- flag_crc32 = HWCAP_CRC32; +- flag_pmull = HWCAP_PMULL; +- capabilities = getauxval(AT_HWCAP); +- #elif defined(__ARM_NEON) || defined(__ARM_NEON__) +- /* The use of HWCAP2 is for getting features of newer ARMv8-A SoCs +- * while running in 32bits mode (i.e. aarch32). +- */ +- flag_crc32 = HWCAP2_CRC32; +- flag_pmull = HWCAP2_PMULL; +- capabilities = getauxval(AT_HWCAP2); +- #endif +-#endif +- +- if (capabilities & flag_crc32) +- arm_cpu_enable_crc32 = 1; +- +- if (capabilities & flag_pmull) ++ id_aa64isar0 = READ_SPECIALREG(ID_AA64ISAR0_EL1); ++ if (ID_AA64ISAR0_AES(id_aa64isar0) == ID_AA64ISAR0_AES_PMULL) + arm_cpu_enable_pmull = 1; ++ if (ID_AA64ISAR0_CRC32(id_aa64isar0) == ID_AA64ISAR0_CRC32_BASE) ++ arm_cpu_enable_crc32 = 1; ++#endif + } + + void ZLIB_INTERNAL arm_check_features(void) + { + pthread_once(&cpu_check_inited_once, init_arm_features); + } +-#else +-#include +- +-static BOOL CALLBACK _arm_check_features(PINIT_ONCE once, +- PVOID param, +- PVOID *context); +-static INIT_ONCE cpu_check_inited_once = INIT_ONCE_STATIC_INIT; +- +- +-void ZLIB_INTERNAL arm_check_features(void) +-{ +- InitOnceExecuteOnce(&cpu_check_inited_once, _arm_check_features, +- NULL, NULL); +-} +- +-static BOOL CALLBACK _arm_check_features(PINIT_ONCE once, +- PVOID param, +- PVOID *context) +-{ +- if (IsProcessorFeaturePresent(PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE)) +- arm_cpu_enable_crc32 = 1; +- +- if (IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE)) +- arm_cpu_enable_pmull = 1; +- +- return TRUE; +-} +-#endif /* _MSC_VER */ -- cgit v1.2.3