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| author | John Marino <marino@FreeBSD.org> | 2014-08-18 15:41:36 +0000 |
|---|---|---|
| committer | John Marino <marino@FreeBSD.org> | 2014-08-18 15:41:36 +0000 |
| commit | d96901c32071af932aae9f83d0faaaf0f5c9ab80 (patch) | |
| tree | 86ef8fa3dd6da82ad1b94169720283f086f86606 /cad/p5-Verilog-Perl | |
| parent | - Update from 4.320.1 to 4.320.2 (diff) | |
Stage cad/cider. Mark BROKEN on F10+ caused by bmake
This port generates a makefile and then passes it to "make" via stdin,
which makes it different to troubleshoot. When I finally saw the file
in order to figure out why several internal static libraries weren't
getting built leading to some programs not getting built, I saw a
generic static library target made up of variables. fmake likes it;
bmake does not.
I tried USES+= fmake along with some patching but I must have missed
some hardcoded "make" commands because bmake got called again. This
software is 20 years old so I finally gave it. It got a stay of
execution by getting staged. If somebody wants to study a target that
bmake just doesn't get, this is a good place to start.
Diffstat (limited to 'cad/p5-Verilog-Perl')
0 files changed, 0 insertions, 0 deletions